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Week 6 A

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23 views18 pages

Week 6 A

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Gqgqg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 10

Logic Synthesis, Part 1

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
Outline

Write Synthesizable Code

Write Synthesis Script

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Synthesizable Verilog

• Top-down design
– top-level module
– example: module MyChip_ASIC();
– lower-level modules
– initially empty placeholders, or stubs

• Functionally identical or equivalent

3
Logic Circuit Synthesis

• Combinational circuit
– continuous assignment

– always statement
– contains only signals with no edges
– level-sensitive list

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Logic Circuit Synthesis

• Combinational circuit
– concatenation or bit reduction

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Logic Circuit Synthesis

• Example 3-8 decoder

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Logic Circuit Synthesis

• Don’ts
– miss signals in the sensitivity list
– use variables before assignment

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Logic Circuit Synthesis

• Multiplexers
– imply a MUX using case

– if not always assign to an input, might imply latch

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Logic Circuit Synthesis

• Case statement
– include default to be exhaustive
– don’t care x, gives synthesizer flexibility

9
Logic Circuit Synthesis

• Sequential logic
– edge sensitive always block, with non-blocking
• Example: D Flip Flop
• Don’t use “@ clk”
– will have latch
– we hate latch

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Logic Circuit Synthesis

• Sequential logic
– initialize the memory element by specifying reset
– use a template

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Logic Circuit Synthesis

• Datapath synthesis
– bus-wide arithmetic and other bus-wide operations
– example: 32-bit multiplier
– Synopsys DesignWare library
– use directives

12
Logic Circuit Synthesis

• Hand instantiation
– generic logic netlist
– to ensure a particular cell be included

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Finite-State Machine Synthesis

• Encoding style

• Style template
– using two always blocks
– using single always blocks
– using a function for combinational logic

• Example
– http://www.asic-world.com/tidbits/verilog_fsm.html

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Non-Synthesizable Constructs

• Initial, events: used only in test bench


• Real, time (delay with #)
– data not supported by synthesizer
• Comparison to x and z

• Assign (to register)


• Fork – join
– test bench only
• Primitives
– only gate level primitives are supported
• Table

15
Write Synthesizable Code

• Use meaningful names for signals and variables


• Don't mix level and edge sensitive elements in the same always
block
• Avoid mixing positive and negative edge-triggered flip-flops
• Use parentheses to optimize logic structure
• Use continuous assign statements for simple combo logic
• Use nonblocking for sequential and blocking for combo logic
• Don't mix blocking and nonblocking assignments in the same
always block (even if Design compiler supports them!!)
• Be careful with multiple assignments to the same variable
• Define if-else or case statements explicitly

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Synopsys Design Compiler

• Tutorial posted on class website


• Follow the step-by-step instruction before Wed
lecture

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Questions?

Comments?

Discussion?

18

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