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Week 14 A

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17 views

Week 14 A

Uploaded by

Gqgqg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 22

Design Compiler in Depth

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
Timeline

• Class project tasks


– logic synthesis
– design optimization and iteration
– place and route
– final report
• Project milestones
– 12/7: in-class presentation
– 12/12: final report due
– hard deadlines, not extendable
• Lecture plans
– 11/30: 30min team meeting
– 12/5: last lecture, Encounter tips, conclusion

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Feedback from Mid-Project Reports

• Synthesizable Verilog code style


– If-else, case: complete default branch
– DO NOT mix blocking and non-blocking statements
– proper FSM implementation
– clocked Always block, reset and sensitivity list
• Testbench setup
– instantiate memory
– simulation termination
– endianess (Bitcoin)
• To-do list
– logic synthesis
– place and route

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Design Compiler User Guide

• Develop HDL files


– Chapter 3, “Preparing design files for synthesis”
• Specify libraries
– Chapter 4, “Working with libraries”
• Read design
– Chapter 5, “Working with designs in memory”
• Define design environment
– Chapter 6, “Defining the design environment”
• Set design constraints
– Chapter 7, “Defining design constraints”
• Select compile strategy
• Synthesize and optimize the design
– Chapter 8, “Optimizing the design”

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Organize the Design Data

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HDL Coding for Synthesis

• FSM

• Sensitivity list
• Incomplete control statement

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HDL Coding for Synthesis

• Value assignments
– use nonblocking assignments within sequential always
– use blocking assignments within combinational always
• Constant definition

• Guidelines for identifiers, expressions, and


functions

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Design Terminology and Objects

• Flat vs Hierarchical Designs

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Designs, Instances, and References

• analyze
• elaborate
• read_file
• link: link_library, search_path

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Ungroup Hierarchies Automatically

• compile_ultra
– by default, perform delay-based auto-ungrouping

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Edit Designs

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Edit Designs

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Define the Design Environment

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Model the System Interface

• Define drive characteristics for input ports

• Define load on input and output ports

• Define fanout loads on output ports

• (Similarly) Set logic constraints on ports


– define ports as logically equivalent
– define logically opposite input ports
– allow assignment of any signal to an input
– always one or zero
– unconnected

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Define Design Constraints

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Summary of Design Rule Commands

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Optimization Constraints

• Timing constraints (performance and speed)


– input and output delays (synchronous paths)
– minimum and maximum delay (asynchronous paths)
– note: set_fix_hold

• Maximum area
– number of gates

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Cost Function Calculation

• Design rule cost function

• Max delay cost function

• Min delay cost function

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Optimize the Design

• Architecture optimization
– sharing common subexpressions
– sharing resources
– reordering operators
– selecting DesignWare implementations, etc.
• Logic-level optimization
– structuring
– flattening
• Gate-level optimization
– mapping
– delay optimization
– design rule fixing
– area optimization

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Optimization Example

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Top-Down Optimization

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Bottom-Up Optimization

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Mixed Optimization

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Suggested Reading

• Partitioning for Synthesis


– Chapter 3 (3-4)
• Working with Attributes
– Chapter 5 (5-40)
• Define Design Constraints
– Chapter 6
– reporting constraints
– characterize subdesigns
• Optimize the Design
– Chapter 7

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Questions?

Comments?

Discussion?

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