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Week 10 B

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13 views22 pages

Week 10 B

Uploaded by

Gqgqg
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lecture 18

Design For Test (DFT)

Xuan ‘Silvia’ Zhang


Washington University in St. Louis

http://classes.engineering.wustl.edu/ese461/
ASIC Test

• Two Stages
– Wafer test, one die at a time, using probe card
• production tester applies signals generated by a
test program (test vectors) and measures the ASIC
test response.
• either the customer, or the ASIC manufacture, or
both, develops the test program
– Final test, after packaging, board level
• Failure Analysis
– Determine the failure mechanism
– Due to the soldering process, electrostatic damage
during handling, or others between shipping and testing
– If the problem is from ASIC fabrication, the test
program may be inadequate
– Board level failure field repair are expensive

2
Importance of Test

• Defect level is used to measure product quality


– 10 defective chips in 100,000 => defect level is 0.1
percent or 100ppm
– Average quality level (AQL) = 1 – defect level

3
Boundary Scan Test

• Joint Test Action Group (JTAG) 2.0, or IEEE


Standard 1149.1
– boundary – Scan Test (BST) standard, using a 4/5-wire
interface
– for PCB and packaging testing
• Add a special logic cell to each ASIC I/O pad
– these cells are joined together to form a chain and
create a boundary-scan shift register

4
BST Cells

• Two sequential elements


– capture flip-flop and update flip-flop
– reversible and can be used for both input and output

5
ASIC Faults

• Fabrication of ASIC may introduce a defect that


in turn may cause a fault.
• Two common type of defects in metallization
– Underetching the metal : bridge or short circuit
– Overetching the metal: break or open circuits
• Other defects
– Dicing, mounting, wafer probing, wire bonding
– Electrical, thermal, corrosion, stress, adhesion failure,
cracking, contaminated chemicals, dirty environment

6
Reliability

• Infant Mortality
– if defects are nonfatal but to cause failures early in the
life of a product.
• Bathtub Curve
– failure rates decrease rapidly to a low value that
remains steady until the end of life when failure rates
increase again.
• Wearout Mechanism
– hot-electron wearout, electromigration, etc.

7
Reliability

• Burn-in Test
– catch susceptible early failure
– operating an ASIC in an elevated temperature accelerates
this type of failure, or apply additional stresses, such as
elevated current or voltage
• Metrics
– mean time between failures (MTBF) for a repairable produce
– mean time to failure (MTTF) for a fatal failure
– failure in time (FITs) when 1 fit equals a single failure in
10^9 hours
– sum the FITs for all the components in a product to
determine an overall measure for the product reliability

The overall failure rate for this system is 5 + 50x10 + 50x15 + 100x6 = 1855 FITs.
8
Fault Models

• Open-Circuit Fault
– bad contact
• Short-Circuit Fault
– accidentally connected
– also called bridging faults
• Degradation Fault
– parametric fault: incorrect switching threshold
– delay fault: a critical path being slower than
specification
• Physical Fault vs. Logical Fault

9
Fault Models

10
Physical Faults

F1 is a short between m1 lines and


connects node n1 to VSS.
F2 is an open on the poly layer and
disconnects the gate of transistor t1
from the rest of the circuit.
F3 is an open on the poly layer and
disconnects the gate of transistor t3
from the rest of the circuit.
F4 is a short on the poly layer and
connects the gate of transistor t4 to
the gate of transistor t5.
F5 is an open on m1 and disconnects
node n4 from the output Z1.
F6 is a short on m1 and connects
nodes p5 and p6.
F7 is a nonfatal defect that causes
necking on m1.

11
Logical Faults

Stuck-at Fault model F1 translates to node n1 being stuck at


0, equivalent to A1 being stuck at 1.
1. Stuck at 1 fault (SA1 or s@1)
F2 result in node n1 remaining high,
2. Stuck at 0 fault (SA0 or s@0) equivalent to A1 being stuck at 0.
F3 will affect half of the n -channel
pull-down stack and may result in a
degradation fault. The cell will still
work, but the fall time at the output
will double. A fault such as this is
extremely hard to detect.
F4 is a bridging fault whose effect
depends on the relative strength of the
transistors driving this node.
F5 completely disables half of the n -
channel pulldown stack and will result
in a degradation fault.
F6 shorts the output node to VDD and is
equivalent to Z1 stuck at 1.
F7 If this line did break due to
electromigration the cell could no
longer pull Z1 up to VDD. This would
translate to a Z1 stuck at 0. This fault
would probably be fatal and stop the
ASIC working. 12
Stuck-at Fault Models

• Stuck-at-0
– represent a signal that is permanently low regardless of
the other signals that normally control the node
• Stuck-at-1
– represent a signal that is permanently high regardless
of the other signals that normally control the node
• Example
– assume that you have a two-input AND gate that has a
stuck-at-0 fault on the output pin
– regardless of the logic level of the two inputs, the
output is always 0

13
Stuck-at Fault Models

• Preconditions for Detecting


– the node of a stuck-at fault must be controllable and
observable for the fault to be detected
• Controllable Node
– if you can drive it to a specified logic value by setting
the primary inputs to specific values
– a primary input is an input that can be directly
controlled in the test environment
• Observable Node
– if you can predict the response on it and propagate the
fault effect to the primary outputs where you can
measure the response
– a primary output is an output that can be directly
observed in the test environment

14
Automatic Test-Pattern Generation

• D(etect)-Calculus
• Enabling Value
– propagate a signal
• Controlling Value
– opposite of
enabling value
– fix the output

15
Automatic Test-Pattern Generation

• Find an input vector to test a fault origin


• Work backward until reach a PI (primary input)
• Work forward using sensitized path to a PO
– a wave of D’s is called the D-frontier

16
Design for Test (DFT)

• Insert scan chain in netlist


– replacing flip-flops with multiplexed flip-flops

• Increase observability/controllability of non-


sequential logic throughout the chip

17
Built-in Self-Test (BIST)

• LFSR (Linear feedback shift register)


– Based on primitive polynomials
• PRBS (pseudorandom binary sequence)

• Initial state is not all zeros


• Maximal length sequence

18
Built-in Self-Test (BIST)

• Serial input signature register (SISR)


• Data compaction (compression)
• Signature (at the end of input sequence) analysis

• If input sequence and SISR are long enough, it is


unlikely (though possible) that two different
input sequences will produce the same signature

19
Built-in Self-Test (BIST)

20
Reference

• ASIC ebook, Chapter 14

21
Questions?

Comments?

Discussion?

22

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