RTL8304MB-CG

SINGLE-CHIP 4-PORT 10/100M ETHERNET

SWITCH CONTROLLER

DATASHEET
(CONFIDENTIAL: Development Partners Only)

Rev. 1.0
26 May 2014
Track ID: JATR-8275-15

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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Datasheet

COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.

REVISION HISTORY
Revision Release Date Summary
1.0 2014/05/26 First release.

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Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................3
4. BLOCK DIAGRAM ...........................................................................................................................................................4
5. PIN ASSIGNMENTS .........................................................................................................................................................5
5.1. PIN ASSIGNMENTS DIAGRAM .......................................................................................................................................5
5.2. PACKAGE IDENTIFICATION ...........................................................................................................................................5
5.3. PIN ASSIGNMENTS TABLE ............................................................................................................................................6
6. PIN DESCRIPTIONS.........................................................................................................................................................7
6.1. PIN ASSIGNMENT CODES .............................................................................................................................................7
6.2. MEDIA CONNECTION PINS ...........................................................................................................................................7
6.3. RMII PORT MAC INTERFACE PINS ..............................................................................................................................7
6.4. MISCELLANEOUS PINS .................................................................................................................................................8
6.5. PORT LED PINS ...........................................................................................................................................................8
6.6. STRAPPING PINS ...........................................................................................................................................................9
6.7. LDO PINS ..................................................................................................................................................................10
6.8. POWER AND GND PINS ..............................................................................................................................................10
7. BASIC FUNCTIONAL DESCRIPTION........................................................................................................................11
7.1. SWITCH CORE FUNCTION OVERVIEW.........................................................................................................................11
7.1.1. Flow Control ........................................................................................................................................................11
7.1.1.1 IEEE 802.3x Full Duplex Flow Control........................................................................................................................11
7.1.1.2 Half Duplex Back Pressure ...........................................................................................................................................11
7.1.2. Address Search, Learning, and Aging ..................................................................................................................12
7.1.3. Half Duplex Operation .........................................................................................................................................12
7.1.4. InterFrame Gap....................................................................................................................................................12
7.1.5. Illegal Frame........................................................................................................................................................12
7.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW ...............................................................................................................13
7.2.1. Auto-Negotiation ..................................................................................................................................................13
7.2.2. 10Base-T Transmit Function ................................................................................................................................13
7.2.3. 10Base-T Receive Function ..................................................................................................................................13
7.2.4. Link Monitor.........................................................................................................................................................13
7.2.5. 100Base-TX Transmit Function............................................................................................................................13
7.2.6. 100Base-TX Receive Function..............................................................................................................................13
7.2.7. Power-Down Mode...............................................................................................................................................14
7.2.8. Crossover Detection and Auto Correction ...........................................................................................................14
7.2.9. Polarity Detection and Correction .......................................................................................................................14
7.3. GENERAL FUNCTION OVERVIEW ................................................................................................................................15
7.3.1. Power-On Sequence .............................................................................................................................................15
7.3.2. Setup and Configuration.......................................................................................................................................16
7.3.3. Serial EEPROM Example.....................................................................................................................................17
7.3.3.1 EEPROM Device Operation .........................................................................................................................................17
7.3.3.2 EEPROM Size Selection...............................................................................................................................................19
7.3.4. SMI .......................................................................................................................................................................19
7.3.5. RMII Port (The 4th Port)......................................................................................................................................20
7.3.5.1 RMII .............................................................................................................................................................................20
7.3.6. Head-Of-Line Blocking ........................................................................................................................................20
7.3.7. Filtering/Forwarding Reserved Control Frame ...................................................................................................21
7.3.8. Loop Detection .....................................................................................................................................................21

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7.3.9. Reg.0.14 PHY Digital Loopback Return to Internal.............................................................................................23
7.3.10. LDO for 1.0V Power Generation.....................................................................................................................24
7.3.11. Crystal/Oscillator ............................................................................................................................................24
8. ADVANCED FUNCTION DESCRIPTION...................................................................................................................25
8.1. VLAN FUNCTION ......................................................................................................................................................25
8.1.1. VLAN Description ................................................................................................................................................25
8.1.2. Port-Based VLAN .................................................................................................................................................26
8.1.3. IEEE 802.1Q Tagged-VID Based VLAN ..............................................................................................................26
8.1.4. Insert/Remove/Replace Tag..................................................................................................................................26
8.1.5. Ingress and Egress Rules......................................................................................................................................27
8.2. IEEE 802.1P REMARKING FUNCTION .........................................................................................................................27
8.3. QOS FUNCTION ..........................................................................................................................................................28
8.3.1. Bandwidth Control ...............................................................................................................................................28
8.3.1.1 Output (TX) Bandwidth Control...................................................................................................................................28
8.3.1.2 Input (RX) Bandwidth Control .....................................................................................................................................29
8.3.2. Priority Assignment ..............................................................................................................................................29
8.3.2.1 Queue Number Selection ..............................................................................................................................................29
8.3.2.2 Port-Based Priority Assignment....................................................................................................................................29
8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment..................................................................................................................30
8.3.2.4 DSCP-Based Priority Assignment ................................................................................................................................30
8.3.2.5 IP Address-Based Priority.............................................................................................................................................30
8.3.2.6 Reassigned Priority .......................................................................................................................................................30
8.3.2.7 RLDP-Based Priority ....................................................................................................................................................30
8.3.2.8 Packet Priority Selection...............................................................................................................................................31
8.4. LOOKUP TABLE FUNCTION ........................................................................................................................................32
8.4.1. Function Description............................................................................................................................................32
8.4.2. Address Search, Learning, and Aging ..................................................................................................................32
8.4.3. Lookup Table Definition.......................................................................................................................................34
8.5. STORM FILTER FUNCTION ..........................................................................................................................................34
8.6. INPUT AND OUTPUT DROP FUNCTION ........................................................................................................................35
8.7. LED FUNCTION..........................................................................................................................................................36
8.8. ENERGY-EFFICIENT ETHERNET (EEE) .......................................................................................................................37
8.9. CABLE DIAGNOSIS .....................................................................................................................................................37
9. CHARACTERISTICS......................................................................................................................................................38
9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ...............................................................................................38
9.2. OPERATING RANGE ....................................................................................................................................................38
9.3. DC CHARACTERISTICS ...............................................................................................................................................38
9.4. DIGITAL TIMING CHARACTERISTICS ..........................................................................................................................39
9.4.1. RMII Interface Timing..........................................................................................................................................39
9.4.1.1 RMII Timing.................................................................................................................................................................39
9.4.2. LED Timing ..........................................................................................................................................................39
9.4.3. Reception/Transmission Data Timing of SMI Interface .......................................................................................40
9.4.4. EEPROM Auto-Load Timing................................................................................................................................41
10. MECHANICAL DIMENSIONS.................................................................................................................................42
10.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................43
11. ORDERING INFORMATION ...................................................................................................................................43

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List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................6
TABLE 2. MEDIA CONNECTION PINS..............................................................................................................................................7
TABLE 3. RMII PORT MAC INTERFACE PINS ................................................................................................................................7
TABLE 4. MISCELLANEOUS PINS ...................................................................................................................................................8
TABLE 5. PORT LED PINS..............................................................................................................................................................8
TABLE 6. STRAPPING PINS .............................................................................................................................................................9
TABLE 7. LDO PINS.....................................................................................................................................................................10
TABLE 8. POWER AND GND PINS ................................................................................................................................................10
TABLE 9. BASIC SMI READ/WRITE CYCLES ................................................................................................................................19
TABLE 10. EXTENDED SMI MANAGEMENT FRAME FORMAT ........................................................................................................19
TABLE 11. RESERVED ETHERNET MULTICAST ADDRESSES...........................................................................................................21
TABLE 12. LOOP FRAME FORMAT .................................................................................................................................................22
TABLE 13. CRYSTAL AND OSCILLATOR REQUIREMENTS ...............................................................................................................24
TABLE 14. VLAN TABLE ..............................................................................................................................................................25
TABLE 15. VLAN ENTRY .............................................................................................................................................................25
TABLE 16. L2 TABLE 4-WAY HASH INDEX METHOD ....................................................................................................................33
TABLE 17. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS .................................................................................................38
TABLE 18. OPERATING RANGE......................................................................................................................................................38
TABLE 19. DC CHARACTERISTICS .................................................................................................................................................38
TABLE 20. RMII TIMING ...............................................................................................................................................................39
TABLE 21. LED TIMING ................................................................................................................................................................39
TABLE 22. SMI TIMING.................................................................................................................................................................40
TABLE 23. EEPROM AUTO-LOAD TIMING CHARACTERISTICS ....................................................................................................41
TABLE 24. ORDERING INFORMATION ............................................................................................................................................43

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List of Figures
FIGURE 1. BLOCK DIAGRAM ..........................................................................................................................................................4
FIGURE 2. PIN ASSIGNMENTS ........................................................................................................................................................5
FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING ...................................................................................................11
FIGURE 4. POWER-ON SEQUENCE ................................................................................................................................................15
FIGURE 5. RESET .........................................................................................................................................................................16
FIGURE 6. START AND STOP DEFINITION .....................................................................................................................................18
FIGURE 7. OUTPUT ACKNOWLEDGE ............................................................................................................................................18
FIGURE 8. RANDOM READ ...........................................................................................................................................................18
FIGURE 9. SEQUENTIAL READ .....................................................................................................................................................18
FIGURE 10. RMII SIGNAL DIAGRAM .............................................................................................................................................20
FIGURE 11. LOOP EXAMPLE ..........................................................................................................................................................21
FIGURE 12. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION .....................................................................................22
FIGURE 13. LOOP EXAMPLE 2 .......................................................................................................................................................23
FIGURE 14. REG. 0.14 LOOPBACK .................................................................................................................................................23
FIGURE 15. PACKET-SCHEDULING DIAGRAM ................................................................................................................................28
FIGURE 16. RTL8304MB PRIORITY ASSIGNMENT DIAGRAM .......................................................................................................29
FIGURE 17. BROADCAST INPUT DROP VS. OUTPUT DROP ..............................................................................................................35
FIGURE 18. MULTICAST INPUT DROP VS. OUTPUT DROP...............................................................................................................35
FIGURE 19. FLOATING AND PULL-HIGH OF LED PINS FOR LED ...................................................................................................36
FIGURE 20. RECEPTION DATA TIMING OF SMI INTERFACE ...........................................................................................................40
FIGURE 21. TRANSMISSION DATA TIMING OF SMI INTERFACE .....................................................................................................40
FIGURE 22. EEPROM AUTO-LOAD TIMING..................................................................................................................................41

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1. General Description
The RTL8304MB-CG is a 4-port 10/100M Ethernet switch controller that integrates memory, four
MACs, and three physical layer transceivers for 10Base-T and 100Base-TX operation into a single chip.
It supports an RMII interface for external devices to connect to the 4th MAC. The external device could
be a routing engine, HomePNA, HomePlug, or VDSL transceiver depending on the application. In order
to accomplish diagnostics in complex network systems, the RTL8304MB provides a loopback feature in
each port.

The RTL8304MB supports several advanced QoS functions with four-level priority queues to improve
multimedia or real-time networking applications, including:
• Multi-priority assignment
• Differential queue weight
• Port-based rate limitation
• Queue-based rate limitation

The RTL8304MB supports 16 VLAN groups. These can be configured as port-based VLANs and/or
802.1Q tag-based VLANs. The RTL8304MB also supports VLAN learning, with four Independent
VLAN Learning (IVL) filtering databases. The RTL8304MB contains a 2K-entry address lookup table. A
4-way associative hash algorithm avoids hash collisions and maintains forwarding performance.
Maximum packet length can be 2048 bytes. Three types of independent storm filter are provided to filter
packet storms, and an intelligent switch engine prevents Head-of-Line blocking problems.

The RTL8304MB supports Energy-Efficient Ethernet mode (EEE; defined in IEEE 802.3az) to minimize
system power consumption. Energy-Efficient Ethernet supports Low Power Idle Mode. When Low Power
Idle Mode is enabled, systems on both sides of the link can disable portions of the functionality and save
power during periods of low link utilization.

To simplify the peripheral power circuit, the RTL8304MB integrates one LDO regulator to generate 1.0V
from a 3.3V input power, and needs only one external diode.

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2. Features
Basic Switching Functions Security and Management

„ 4-port switch controller with memory and „ Supports reserved control frame filtering
transceiver for 10Base-T and 100Base-TX
„ Supports advanced storm filtering
„ Non-blocking wire-speed reception and
transmission and non-head-of-line-blocking „ Optional EEPROM interface for
forwarding configuration

„ Complies with IEEE 802.3/802.3u auto- VLAN Functions

negotiation
„ Supports up to 16 VLAN groups
„ Built-in high efficiency SRAM for packet
„ Flexible 802.1Q port/tag-based VLAN
buffer, with 2K-entry lookup table and two
4-way associative hash algorithms „ Supports four IVLs
„ 2048 byte maximum packet length „ Leaky VLAN for
unicast/multicast/broadcast/ARP packets
„ Flow control fully supported
‹ Half duplex: Back pressure flow control Power Saving Functions

‹ Full duplex: IEEE 802.3x flow control „ Supports Energy-Efficient Ethernet (EEE)
function (IEEE 802.3az)
„ Supports RMII interface for embedded
system such as set top box or TV box. „ Link Down Power Saving Mode
‹ RMII REFCLK output or input Diagnostic Functions
Service Quality
„ Supports hardware loop detection function
„ Supports high performance QoS function on with LEDs and buzzer to indicate the
each port existence of a loop

‹ Supports 4-level priority queues „ Supports cable diagnosis (RTCT function)

‹ Weighted round robin service
„ Flexible LED indicators
‹ Supports strict priority
‹ RTCT status indication
‹ Input/Output port bandwidth control
‹ Loop status indication
‹ Queue-based bandwidth control
‹ LEDs blink upon reset for LED
‹ 1Q-based, Port-based, DSCP-based, IP diagnostics
address-based, and other types of priority
assignments Other Features

„ Supports IEEE 802.1p Traffic Re-marking „ Optional MDI/MDIX auto crossover for
plug-and-play

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„ Physical layer port Polarity Detection and „ Single 3.3V power input can be transformed
Correction function by integrating an LDO regulator to generate
1.0V from 3.3V via a low-cost external
„ Robust baseline wander correction for Diode
improved 100Base-TX performance
„ Low power, 1.0/3.3V, 55nm CMOS
„ 25MHz crystal or 3.3V OSC input technology

„ 48-pin QFN ‘Green’ package

3. System Applications
„ 4-port switch (10Base-T & 100Base-TX)
„ Set-top box or TV box

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4. Block Diagram

Figure 1. Block Diagram

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5. Pin Assignments
5.1. Pin Assignments Diagram

Figure 2. Pin Assignments

5.2. Package Identification

Green package is indicated by a ‘G’ in the location marked ‘TXXXX’ in Figure 2.

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5.3. Pin Assignments Table

‘Type’ codes used in the following table: A=Analog, G=Ground, I=Input, O=Output, I/O=Input/Output,
PU=Pin with Pull-Up Resistor, PD=Pin with Pull-Down Resistor.

Table 1. Pin Assignments Table

Name Pin No. Type Name Pin No. Type
TXOP[1] 1 AI/O INT/FCTRL_STA 26 I/OPU
TXON[1] 2 AI/O SCL/MDC 27 I/OPU
RXIN[1] 3 AI/O SDA/MDIO 28 I/OPU
RXIP[1] 4 AI/O RESETB 29 IPU
AVDDL 5 AP LDIND/DIS_LD 30 I/OPU
DVDDL 6 P P0LED/DIS_EEE 31 I/OPD
AVDDL 7 AP DVDDH 32 P
RXIP[2] 8 AI/O P1LED/RMA_MODE 33 I/OPD
RXIN[2] 9 AI/O P2LED/UNKOWN_MULTI 34 I/OPD
TXON[2] 10 AI/O DVDDL 35 P
TXOP[2] 11 AI/O V10OUT 36 AO
AVDDH 12 AP V33IN 37 AP
DUP_STA 13 I/OPD AVDDHPLL 38 AP
SPD_STA 14 I/OPD XO 39 O
TXD[1]/CLK_DIR 15 I/OPD XI 40 I
TXD[0]/IF_SEL[0] 16 I/OPD AVDDLPLL 41 AP
TXEN 17 I/OPD IBREF 42 AO
IF_SEL[1] 18 I/OPD AVDDL 43 AP
DVDDH 19 P RXIP[0] 44 AI/O
REFCLK 20 I/OPD RXIN[0]] 45 AI/O
CRS_DV 21 I/OPD TXON[0] 46 AI/O
RXD[0] 22 I/OPD TXOP[0] 47 AI/O
RXD[1] 23 I/OPD AVDDH 48 AP
DVDDL 24 P E-PAD E-PAD G
RMII_LINK_STA 25 I/OPD

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6. Pin Descriptions
6.1. Pin Assignment Codes
I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor;
(Typical Value is about 75KΩ) (Typical Value is about 75KΩ)

IPD: Input Pin With Pull-Down Resistor; OPD: Output Pin With Pull-Down Resistor;
(Typical Value is about 75KΩ) (Typical Value is about 75KΩ)

I/OPU: IPU and OPU I/OPD: IPD and OPD

6.2. Media Connection Pins

Table 2. Media Connection Pins
Pin Name Pin No. Type Drive (mA) Description
RXIP2/RXIN2 8, 9 AI/O - Differential Receive Data Input.
RXIP1/RXIN1 4, 3 Port0-2 support 10Base-T, 100Base-TX.
RXIP0/RXIN0 44,45
TXOP2/TXON2 11, 10 AI/O - Differential Transmit Data Output.
TXOP1/TXON1 1,2 Port0-2 support 10Base-T, 100Base-TX.
TXOP0/TXON0 47, 46

6.3. RMII Port MAC Interface Pins

Table 3. RMII Port MAC Interface Pins
Pin Name Pin No. Type Description Default
RXD[1:0] 23, 22, I/OPD Pins receive data of MAC. -
CRS_DV 21 IPD Pin is used as CRS_DV. -
REFCLK 20 I/OPD Pin is used as REFCLK output or input based on configuration. -
TXD[1:0] 15, 16, I/OPD Pins transmit data of MAC. -
TXEN 17 I/OPD Pin is used as TXEN -

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Pin Name Pin No. Type Description Default
RMII_LNK_STA 25 IPD Provides RMII port (4th port) Link Status for MAC module in real 0
time.
This pin sets the link status of the RMII port MAC module in real-
time.
0: MAC3 is link down
1: MAC3 is link up

6.4. Miscellaneous Pins

As the output of the RTL8304MB is 3.3V, the serial EEPROM and external device must be 3.3V
compatible.
Table 4. Miscellaneous Pins
Pin Name Pin No. Type Drive (mA) Description
LDIND 30 I/OPU 10 Loop Indication Used by LED and Buzzer.
INT 26 I/OPU 4 Setting any flag bit in the interrupt event flag register will cause this
pin to be pulled low and output logical ‘0’. Only when all flag bits in
the interrupt event flag register are cleared, this pin will be pulled
high and output logical ‘1’.
SCL/MDC 27 I/OPU 4 I2C Interface Clock for EEPROM Auto Load when Power On.
After power on, this pin is MDC/MDIO Interface Clock for access
registers.
SDA/MDIO 28 I/OPU 4 I2C Interface Data Input/Output for EEPROM Auto Load when
Power On.
After power on, this pin is MDC/MDIO Interface Data Input/Output
for access registers.
RESETB 29 IPU - System Pin Reset Input.
XI 40 AI - 25MHz Crystal Clock Input.
The clock tolerance is ±50ppm.
XO 39 AO - 25MHz Crystal Clock Output Pin.
When the pin of XI is using an oscillator this pin should be floating.
IBREF 42 AO - Reference Resistor for PHY Bandgap.
A 2.49KΩ (1%) resistor should be connected between IBREF and
GND.

6.5. Port LED Pins

All LED statuses are represented as active-low or high depending on input strapping.
Those pins that are dual-function pins are output for LED, or input for strapping. Below are LED
descriptions only.
Table 5. Port LED Pins
Pin Name Pin No. Type Drive (mA) Description
P0LED 31 I/OPD 10 LED for Port0 Status Indication.
P1LED 33 I/OPD 10 LED for Port1 Status Indication.
P2 LED 34 I/OPD 10 LED for Port2 Status Indication.

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6.6. Strapping Pins

Pins that are dual function pins are outputs for LED or inputs for strapping. Below are strapping
descriptions only.
Table 6. Strapping Pins
Pin Name Pin No. Type Default Description
DISLD 30 I/OPU - Disable Loop Detection Function.
(LDIND) 0: Enable
1: Disable (default)
DIS_EEE 31 I/OPD - Disable EEE Function.
(P0LED) 0: Enable EEE function (default)
1: Disable EEE function
RMAMODE 33 I/OPD - RMA Mode Select.
(P1LED) 0: Mode0 is selected (default)
01-80-c2-00-00-02 is drop and 01-80-c2-00-00-11 ~
01-80-c2-00-00-1F, 01-80-c2-00-00-21 packets are
forwarded.
1: Mode1 is selected
01-80-c2-00-00-02 is forward and 01-80-c2-00-00-11 ~
01-80-c2-00-00-1F, 01-80-c2-00-00-21 packets are
dropped.
UNKOWN_MULTI 34 I/OPD - Enable Unknown Multicast Data Packet Drop.
(P2LED) 0: Forward all unknown multicast data packet (default)
1: Drop all unknown multicast data packet (except
IGMP/MLD and RMA packet)
CLK_DIR 15 I/OPD - RMII Interface REFCLK Direction Select
(TXD1) 0: REFCLK is input
1: REFCLK outputs 50MHz clock.
IF_SEL[0] 16 I/OPD - MAC3 Interface Select.
(TXD0) 00: Disable MAC3 interface(default)
01: Reserved
10: Reserved
11: RMII interface
IF_SEL[1] 18 I/OPD - MAC3 Interface Select.
00: Disable MAC3 interface(default)
01:Reserved
10: Reserved
11: RMII interface
SPD_STA 14 I/OPD - Force MAC3 Speed.
0: MAC3 is 10Mbps
1: MAC3 is 100Mbps,
DUP_STA 13 I/OPD - Force MAC3 Duplex.
0: MAC3 is half duplex
1: MAC3 is full duplex
FCTRL_STA 26 I/OPU - Force MAC3 Flow Control.
(INT) 0: MAC3 is disabled
1: MAC3 is enabled

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6.7. LDO Pins

Table 7. LDO Pins
Pin Name Pin No. Type Drive (mA) Description
V10OUT 36 AO - LDO 1.0V Output.
V33IN 37 AP - LDO 3.3V Input.

6.8. Power and GND Pins

Table 8. Power and GND Pins
Pin Name Pin No. Type Description
AVDDH 12, 48 AP Analog Power 3.3V.
AVDDL 5, 7, 43 AP Analog Power 1.0V.
AVDDHPLL 38 AP Power 3.3V for PLL.
AVDDLPLL 41 AP Power 1.0V for PLL.
DVDDH 19, 32 P Digital Power 3.3V for IO Pin.
DVDDL 6, 24, 35 P Digital Power 1.0V for Core Voltage.
GND E-PAD G Ground for Whole Chip.

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7. Basic Functional Description

7.1. Switch Core Function Overview
7.1.1. Flow Control
The RTL8304MB supports IEEE 802.3x full duplex flow control, force mode full duplex flow control,
and optional half duplex backpressure.
7.1.1.1 IEEE 802.3x Full Duplex Flow Control
For UTP with auto-negotiation ability, the pause ability of full duplex flow control is enabled by internal
registers via SMI on a per-port basis after reset. IEEE 802.3x flow control’s ability is auto-negotiated
between the remote device and the RTL8304MB. If the auto-negotiation result of the IEEE 802.3x pause
ability is ‘Enabled’, the full duplex 802.3x flow control function is enabled. Otherwise, the full duplex
IEEE 802.3x flow control function is disabled.
7.1.1.2 Half Duplex Back Pressure
There are two mechanisms for half duplex backpressure; collision-based or carrier-based.
Collision-Based Backpressure (Jam Mode)
If the buffer is ready to overflow, this mechanism will force a collision. When the link partner detects this
collision, the transmission is rescheduled.
The Reschedule procedure is:
• The RTL8304MB will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal
(pattern is 0xAA). The RTL8304MB will then drive TXEN to low
• When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01),
it will then drive RXDV to low
• The link partner waits for a random back-off time then re-sends the packet. The timing is shown in
Figure 3

Figure 3. Collision-Based Backpressure Signal Timing

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Carrier-Based Backpressure (Defer Mode)
If the buffer is about to overflow, this mechanism will send an 0xAA pattern to defer the other station’s
transmission. The RTL8304MB will continuously send the defer signal until the buffer overflow is
resolved.

7.1.2. Address Search, Learning, and Aging

When a packet is received, the RTL8304MB will use the destination MAC address and FID to index the
2048-entry lookup table. If the indexed entry is valid, the received packet will be forwarded to the
corresponding destination port. Otherwise, the RTL8304MB will broadcast the packet. This is the
‘Address Search’.
The RTL8304MB then combines the source MAC address and the FID to index the 2048-entry lookup
table. If the entry is not in the table it will record the source MAC address and add switching information.
If this is an occupied entry, it will update the entry with new information when LRU is enabled. This is
called ‘Learning’.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The lookup engine will update the time stamp information of an entry whenever the corresponding source
MAC address appears. An entry will be invalid (aged-out) if its time stamp information is not refreshed
by the address learning process during the aging time period. The aging time of the RTL8304MB is
between 200 and 400 seconds.

7.1.3. Half Duplex Operation

In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. A
controlled randomization process called ‘truncated binary exponential backoff’ determines the scheduling
of the retransmissions. At the end of enforcing a collision (jamming), the switch delays before attempting
to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The number of slot
times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer
‘r’ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). IEEE 802.3 defines the backoffLimit as 10.

7.1.4. InterFrame Gap

The InterFrame Gap is 9.6µs for 10Mbps Ethernet and 960ns for 100Mbps Fast Ethernet.

7.1.5. Illegal Frame

Illegal frames such as CRC error packets, runt packets (length < 64 bytes), and oversize packets (length >
maximum length), will be discarded.
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7.2. Physical Layer Functional Overview

7.2.1. Auto-Negotiation
The RTL8304MB obtains the states of duplex, speed, and flow control ability for each port through the
auto-negotiation mechanism defined in the IEEE 802.3 specifications. During auto-negotiation, each port
advertises its ability to its link partner and compares its ability with advertisements received from its link
partner. By default, the RTL8304MB advertises full capabilities (100Full, 100Half, 10Full, 10Half)
together with flow control ability. The RTL8304MB also advertises the Energy Efficient Ethernet (EEE)
capability to the link partner.

7.2.2. 10Base-T Transmit Function

The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.

7.2.3. 10Base-T Receive Function

The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.

7.2.4. Link Monitor

The 10Base-T link pulse detection circuit continually monitors the RXIP/RXIN pins for the presence of
valid link pulses. Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN
signal pairs.

7.2.5. 100Base-TX Transmit Function

The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects are significantly reduced.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven into the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
further reduces EMI emissions.

7.2.6. 100Base-TX Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A De-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.

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7.2.7. Power-Down Mode

The RTL8304MB implements power-down mode on a per-port basis. Setting MII Reg.0.11 forces the
corresponding port of the RTL8304MB to enter power-down mode. This disables all transmit/receive
functions, except SMI (Serial Management Interface: MDC/MDIO, also known as MII Management
Interface).

7.2.8. Crossover Detection and Auto Correction

During the link setup phase, the RTL8304MB checks whether it receives active signals on every port in
order to determine if a connection can be established. In cases where the receiver data pin pair is
connected to the transmitter data pin pair of the peer device and vice versa, the RTL8304MB
automatically changes its configuration and swaps receiver/transmitter data pins as required. If a port is
connected to a PC or NIC with MDI-X interface with a crossover cable, the RTL8304MB will
reconfigure the port to ensure proper connection. This replaces the DIP switch commonly used for
reconfiguring a port on a hub or switch.
Note: IEEE 802.3 compliant forced mode 100M ports with Auto-crossover have link problems with NWay
(Auto-Negotiation) ports. It is recommended to not use Auto-crossover for forced 100M.

7.2.9. Polarity Detection and Correction

For better noise immunity and lower interference to ambient devices, the Ethernet electrical signal on a
twisted-pair cable is transmitted in differential form. That is, the signal is transmitted on two wires in each
direction with inverse polarities (+/-). If wiring on the connector is faulty, or a faulty transformer is used,
the two inputs to a transceiver may carry signals with opposite but incorrect polarities. As a direct
consequence, the transceiver will not work properly.
When the RTL8304MB operates in 10Base-T mode, it automatically reverses the polarity of its two
receiver input pins if it detects that the polarities of the incoming signals on the pins is incorrect.
However, this feature is unnecessary when the RTL8304MB is operating in 100Base-TX mode.

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7.3. General Function Overview

7.3.1. Power-On Sequence
Two power voltage types are required for RTL8304MB normal operation, 3.3V and 1.0V. The 1.0V is
converted from 3.3V via the LDO of the RTL8304MB.
• Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than
2.6V (±5%) after Ta
• Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than
0.71V (±10%) after Tb
• Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal
operating range)
• Td is the moment that the pin reset signal is de-asserted
• Te is the moment that the RTL8304MB device is ready to be accessed by an external CPU

Figure 4. Power-On Sequence

The requirements are:

• The time of Ta should be between 500us and 20ms
• The sequence of Ta is always less than Tb for the LDO of the RTL8304MB. In principle, the sequence
of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended
• The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The
EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM
• Reset

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Depending on the type of reset, the whole or just part of the RTL8304MB is initialized. There are several
ways to reset the RTL8304MB.
• Hardware reset for the whole chip via pin RESET# or power-on
• Soft reset for packet buffer, queue, and MIB counter via register SoftReset
• PHY software reset for each PHY by register reset
Hardware Reset: Power-on, or pull the RESET# pin low for at least 1µs. The RTL8304MB resets the
whole chip and after all power is ready and the RESET# pin is de-asserted, it gets initial values from pins
and serial EEPROM.
Soft Reset: The RTL8304MB does not reset the LUT, LED circuit, and all registers, and does not load
data from serial EEPROM and pins to registers. The packet buffer, queue, and MIB counter will be reset.
After changing the queue number via SMI (Serial Management Interface), the external device must
perform a soft reset in order to update the configuration.
PHY Software Reset: Write bit15 of Reg0 of a PHY as 1. The RTL8304MB will then reset this PHY.
Hardware Reset

Strap pin Load EEPROM

upon reset upon reset

Figure 5. Reset

Some setting values for operation modes are latched from those corresponding mode pins upon hardware
reset. ‘Upon reset’ is defined as a short time after the end of a hardware reset. Other advanced
configuration parameters may be latched from serial EEPROM.

7.3.2. Setup and Configuration

The RTL8304MB can be configured easily and flexibly by:
• Hardware pins upon reset
• Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings)
• Internal registers (including PHY registers for each port and global MAC registers) accessed via SMI
(Serial Management Interface: MDC/MDIO, also known as MII Management Interface)
There are three methods of configuration:
• Only hardware pins for normal switch applications
• Hardware pins and serial EEPROM for advanced switch applications
• Hardware pins and internal registers via SMI for applications with processor

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Two types of pins, each with internal pull-high or pull-low resistors, are used for configuration:
• Input/Output pins used for strapping upon reset and used as output pins after reset
• Input/Output pins used for strapping upon reset and used as LED indicator pins after reset. The LED
statuses are represented as active-low or high depending on input strapping
Pins with default value=0 are internal pull-low and use I/O pads. They can be left floating to set the input
value as low, but should not be connected to VDD without a pull-high resistor.
The serial EEPROM shares two pins, SCL/MDC and SDA/MDIO, with SMI, and is optional for
advanced configuration. SCL/MDC and SDA/MDIO are tri-state during hardware reset (pin RESET#=0).
The RTL8304MB will try to automatically find the serial EEPROM upon reset.
Internal registers can still be accessed after reset via SMI (pin SCL/MDC and SDA/MDIO). Serial
EEPROM signals and SMI signals must not exist at the same time.

7.3.3. Serial EEPROM Example

Both the 24LC01/02/04/08/16 and 24C01/02/04/08/16 can be used with the RTL8304MB. The interface
is a 2-wire serial EEPROM interface providing 1K/2K/4K/8K/16K bits of storage space. The EEPROM
must be 3.3V compatible.
7.3.3.1 EEPROM Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor. Data on the
SDA pin may change only during SCL low time periods. Data changes during SCL high periods will
indicate a start or stop condition as defined below. The SCL frequency is 200 kHz.
Start Condition
A high-to-low transition of SDA with SCL high is the start condition and must precede any other
command.
Stop Condition
A low-to-high transition of SDA with SCL high is a stop condition.
Acknowledge
All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The EEPROM
sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Random Read
A random read requires a ‘dummy’ byte write sequence to load in the data word address.
Sequential Read
For the RTL8304MB, the sequential reads are initiated by a random address read. After the EEPROM
receives a data word, it responds with an acknowledgement. As long as the EEPROM receives an
acknowledgement, it will continue to increment the data word address and clock out sequential data
words in series.

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Figure 6. Start and Stop Definition

Figure 7. Output Acknowledge

Figure 8. Random Read

Read ACK ACK Stop

Device
Address

SDA

Data n Data n +1 Data n +x

R/W ACK ACK ACK NO ACK
Figure 9. Sequential Read

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7.3.3.2 EEPROM Size Selection
The RTL8304MB supports five serial EEPROM sizes —1k bits, 2k bits, 4k bits, 8k bits and 16k bits. Via
the auto-download operation, the RTL8304MB decides the size of the data downloaded to the
RTL8304MB from the EEPROM according to the value of the 2nd byte data in the serial EEPROM.
If the 2nd byte data = 0x01, 0x02, 0x04, 0x08 or 0x16, it means the data size is 1k bits, 2k bits, 4k bits, 8k
bits or 16k bits respectively. The value of the 2nd byte should accord with the actual EEPROM data size.
For example, the value of the 2nd byte cannot be ‘0x02’ when the 24(L)C02 is used.

7.3.4. SMI
The SMI (Serial Management Interface) is also known as the MII Management Interface, and consists of
two signals (MDIO and MDC). It allows external devices with SMI master mode (MDC is output) to
control the state of the PHY and internal registers (SMI slave mode: MDC is input). MDC is an input
clock for the RTL8304MB to latch MDIO on its rising edge. The clock can run from DC to 2.5MHz.
MDIO is a bi-directional connection used to write data to, or read data from the RTL8304MB. The PHY
address is from 0 to 7.
Table 9. Basic SMI Read/Write Cycles
Preamble Start OP Code PHYAD REGAD Turn Around Data Idle
(32 bits) (2 bits) (2 bits) (5 bits) (5 bits) (2 bits) (16 bits)
Read 1……..1 01 10 A4A3A2A1A0 R4R3R2R1R0 Z0 D15…….D0 Z*
Write 1……..1 01 01 A4A3A2A1A0 R4R3R2R1R0 10 D15…….D0 Z*
*: High-impedance. During idle time MDIO state is determined by an external 1.5KΩ pull-up resistor.

For MDIO Manageable Device (MMD) access, the RTL8304MB supports the extended SMI format.
Table 10. Extended SMI Management Frame Format
Frame PRE ST OP PHYAD DEVAD TA DATA IDLE
Address 1…1 00 00 AAAAA EEEEE 10 AAAAAAAAAAAAAAAA Z
Write 1…1 00 01 AAAAA EEEEE 10 DDDDDDDDDDDDDDDD Z
Read 1…1 00 11 AAAAA EEEEE Z0 DDDDDDDDDDDDDDDD Z
Post-Read-Increment-Address 1…1 00 10 AAAAA EEEEE Z0 DDDDDDDDDDDDDDDD Z

To guarantee the first successful SMI transaction after power-on reset, the external device should delay a
few moments before issuing the first SMI Read/Write Cycle relative to the rising edge of reset.

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7.3.5. RMII Port (The 4th Port)

The RTL8304MB is a 3-port Fast Ethernet switch with one extra RMII port for specific applications. It
integrates embedded SRAM for packet storage, four MACs, and three physical layer transceivers for
10Base-T and 100Base-TX, into a single chip.
7.3.5.1 RMII
RMII (Reduced MII) is used in 10/100Mbps mode only. The reference clock pin of the RTL8304MB’s
RMII can be configured to output a 50MHz clock, or be driven by an external clock source. Figure 10
shows the RTL8304MB output a 50MHz clock signal diagram.
RTL8304MB RMII External CPU or PHY

TXD [1:0] TXD[1:0]

TXEN TXEN

RXD [1:0] RXD[1:0]

CRS_DV CRSDV
50MHz
REFCLK REFCLK

Figure 10. RMII Signal Diagram

7.3.6. Head-Of-Line Blocking

The RTL8304MB incorporates a mechanism to prevent Head-Of-Line blocking problems when flow
control is disabled. When the flow control function is disabled, the RTL8304MB first checks the
destination address of the incoming packet. If the destination port is congested, the RTL8304MB will
discard this packet to avoid blocking the next packet, which is going to a non-congested port.

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7.3.7. Filtering/Forwarding Reserved Control Frame

The RTL8304MB supports the ability to forward or drop the frames of the IEEE 802.1 specified reserved
Ethernet multicast addresses.
Table 11. Reserved Ethernet Multicast Addresses
B: Broadcast (Search the Look-Up Table) D: Drop
Assignment Value Available Action
Bridge Group Address 01-80-C2-00-00-00 D, B (Default)
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE 01-80-C2-00-00-01 D (Default), B
Operation
IEEE 802.3ad Slow_Protocols-Multicast Address 01-80-C2-00-00-02 D (Default), B
IEEE 802.1X PAE Address 01-80-C2-00-00-03 D, B (Default)
Reserved for Future Standards 01-80-C2-00-00-04~01-80-C2-00-00-0D, D (Default), B
01-80-C2-00-00-0F
LLDP IEEE Std 802.1AB Link Layer Discovery 01-80-C2-00-00-0E D, B (Default)
Protocol Multicast Address
All LANs Bridge Management Group Address 01-80-C2-00-00-10 D (Default), B
Reserved for 01-80-C2-00-00-1x 01-80-C2-00-00-11~01-80-C2-00-00-1F D, B (Default)
GMRP Address 01-80-C2-00-00-20 D (Default), B
GVRP Address 01-80-C2-00-00-21 D, B (Default)
Reserved for use by Multiple Registration Protocol 01-80-C2-00-00-22~01-80-C2-00-00-2F D (Default), B
(MRP) Applications
802.1ag PDU CCM/LTM 01-80-C2-00-00-31~ 01-80-C2-00-00-3F D, B (Default)

7.3.8. Loop Detection

Loops should be avoided between switch applications. The simplest loop as shown below results in:
1) Unicast frame duplication; 2) Broadcast frame multiplication; 3) Address table non-convergence.
Frames are transmitted from Switch1 to Switch 2 via Link 1, and then returned to Switch 1 via Link 2.

Figure 11. Loop Example

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The loop detect function can be enabled/disabled via strapping pin or registers. When the loop detection
function is enabled, the RTL8304MB sends out a broadcast 64-byte loop frame (the frequency is
configured by register) and sniffs for the sent loop frame on each port to detect whether there is a network
loop (or bridge loop). If a loop is detected, the RTL8304MB will drive the external LEDs and buzzer
alarm.
• The LED driven by the LDIND pin will blink
• The LEDs driven by port LED pins (see Table 5, page 8) of the ports on which the network loop is
detected will all blink simultaneously
• The buzzer driven by the LDIND pin will buzz at the same frequency as the LED blinks
Both passive and active buzzers can be supported. The resonant frequency for the passive buzzer is
approximately 2kHz. The buzzer and all LEDs will turn on/off simultaneously. In Figure 12, T1 is the
turned-off period and T2 is the turned-on period. T1 and T2 are equal and can be configured to 400ms or
800ms.

Figure 12. LED and Buzzer Control Signal for Loop Detection

Loop status, LED, and buzzer indications can be cleared when one of the following conditions occurs.
• Loop frame is not detected in the next loop detection period
• The loop port links down
The Loop frame length is 64 bytes. Its format is shown below.
Table 12. Loop Frame Format
48-bit 48-bit 16-bit 16-bit 12-bit 4-bit 352-bit 16-bit
FFFF FFFF FFFF SID 8899 2300 000 TTL 0000 CRC

In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If
an EEPROM is not used, a unique SID should be assigned via SMI after reset. The TTL (Time-To-Live)
field is used to avoid a storm triggered by the loop frame. The TTL field in the loop frame will decrease
by 1 when it passes through an RTL8304MB whose MAC address is not equal to the SID of the loop
frame. The RTL8304MB will drop a loop frame in which the TTL is the minimum value (0001 is the
minimum value. 0000, meaning 16, is the maximum value). The initial value of the TTL field can be
configured via SMI or EEPROM.

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In Figure 13, device A, B, and C are in a loop. Device D connects to device B. Device D generates a loop
frame with an initial TTL value 3 then sends to device B. When the loop frame arrives at device C, the
TTL value decreases to 2. It turns to 1 when the loop frame is transmitted to device A, and then the loop
frame is dropped by the device A. If device D generates loop frames without the TTL mechanism, the
loop frames will cause a storm in the loop of devices A, B, and C. The RTL8304MB provides an option
to assign high priority to loop frames to reduce the possibility of erroneous loop frame dropping, and
thereby enhance loop detection.

Figure 13. Loop Example 2

7.3.9. Reg.0.14 PHY Digital Loopback Return to Internal

The digital loopback mode of the PHY (return to internal MAC) may be enabled on a per-port basis by
setting MII Reg.0.14 to 1. In digital loopback mode, the TXD of the PHY is transferred directly to the
RXD of the PHY, with TXEN changed to CRS_DV, and returns to the MAC via an internal MII. The
data stream coming from the MAC will not egress to the physical medium, and an incoming data stream
from the network medium will be blocked in this mode. The packets will be looped back in 10Mbps full
duplex or 100Mbps full duplex mode. This function is especially useful for diagnostic purposes. For
example, a NIC can be used to send broadcast frames into Port 0 of the RTL8304MB and set Port 1 to
Reg0.14 Loopback. The frame will be looped back to Port 0, so the received packet count can be checked
to verify that the switch device is good. In this example, Port 0 can be 10M or 100M, and full or half
duplex.

Figure 14. Reg. 0.14 Loopback

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As the RTL8304MB only supports digital loopback in full duplex mode, PHY Reg.0.8 for each port will
always be kept on 1 when digital loopback is enabled. The digital loopback only functions on broadcast
packets (DA=FF-FF-FF-FF-FF-FF). In loopback mode, the link LED of the loopback port should always
be ON, and the Speed and Duplex LED combined to reflect the link status (100full/10full) correctly,
regardless of what the previous status of this loopback port was.

7.3.10. LDO for 1.0V Power Generation

The RTL8304MB can use an internal LDO to generate 1.0V from a 3.3V power supply. This 1.0V is used
for the digital core and analog receiver circuits. Do not use the LDO for other chips, even if the rating is
enough.
Do not connect an inductor (bead) directly between the V10OUT pin and AVDDLPLL pin. This will
adversely affect the stability of the 1.0V power to a significant degree. Please refer to the reference design
for details.

7.3.11. Crystal/Oscillator
When using a crystal, the RTL8304MB should connect a loading capacitor from each pin of XI and XO
to ground. Whether using an oscillator or driving an external 25MHz clock from another device, the
external clock should be fed into the XI pin. The following table shows the requirements of the crystal
and oscillator.
Table 13. Crystal and Oscillator Requirements
Nominal Frequency 25.000 MHz
Frequency Tolerance ±50ppm Max.
Temperature Characteristics ±50ppm in Operating Temperature Range
Equivalent Series Resistance of Crystal 50 Ohm Max.
XTALI/OSC Input Clock Jitter Tolerance (in 5KHz to 2.5MHz Range) 250ps Max.
Duty Cycle 40%~60%

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8. Advanced Function Description

8.1. VLAN Function
8.1.1. VLAN Description
The RTL8304MB supports 16 VLAN groups with the 16-entry VLAN table (see Table 14 and Table 15).
These can be configured as port-based VLANs and/or IEEE 802.1Q tag-based VLANs. The RTL8304MB
supports four IVLs, with the mapping information in the VLAN table. The contents of the VLAN table
can be configured via SMI or EEPROM. Multiple ingress filtering and egress filtering options provide
various VLAN admit rules for the RTL8304MB. The RTL8304MB also provides flexible VLAN tag
insert/remove function based on port and VID.
Table 14. VLAN Table
Entry Index VLAN ID Membership UNTAG_MSK FID
VLAN Entry 0 VLAN ID A[11:0] VLAN ID A membership [3:0] VLAN ID A UNTAG_MSK [3:0] FID[1:0]
VLAN Entry 1 VLAN ID B [11:0] VLAN ID B membership [3:0] VLAN ID B UNTAG_MSK [3:0] FID[1:0]
…… …… …… …… ……
VLAN Entry 15 VLAN ID P [11:0] VLAN ID P membership [3:0] VLAN ID P UNTAG_MSK [3:0] FID[1:0]

Table 15. VLAN Entry

Field Description Bits
VID The VLAN ID for Search. 12
The VID of the ingress packet will be compared with this field.
MBR VLAN Member Port Set. 4
If the bit in this field is ‘1’, the corresponding port is a member port of the VLAN
specified by the VID field.
UNTAG SET VLAN Untag Set. 4
If the bit in this field is ‘1’, egress packets from the corresponding port will be VLAN-
untagged.
PRIORITY VID-Based Priority. 2
The priority assigned to all ingress packets of the VLAN specified by the VID field.
FID The FID is Used by Lookup Table for IVL Application. 12

The main VLAN features of the RTL8304MB are as follows:

• Supports up to 16 VLAN groups
• Flexible IEEE 802.1Q port/tag-based VLAN
• Four IVLs
• Leaky VLAN for ARP broadcast/unicast/multicast packets
• Leaky inter-VLAN mirror function
• VLAN tag Insert/Remove function

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8.1.2. Port-Based VLAN

The 16 VLAN membership registers designed into the RTL8304MB provide full flexibility for users to
configure the member ports to associate with different VLAN groups in the VLAN table. Each port can
join more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port’s VLAN members. The RTL8304MB supports VLAN indexes for each port to individually
index this port to one of the 16 VLAN membership registers. A port that is not included in a VLAN’s
member set cannot transmit packets to this VLAN.
For non-VLAN tagged frames, the RTL8304MB performs port-based VLAN. The VLAN ID associated
with the port-based VLAN index setting is the Port VID (PVID) of this port. The VLAN tag with the
ingress port’s PVID can be inserted (or replace the VID with a PVID for VLAN-tagged packets) into the
packet on egress. The RTL8304MB also provides an option to admit VLAN tagged packets with a
specific PVID only. When IEEE 802.1Q tag-aware VLAN is enabled, the VLAN tag admit control and
non-PVID discard are enabled at the same time. Non-tagged packets and packets with an incorrect PVID
will be dropped.
The RTL8304MB supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on
egress. The PVID in the inserted (or replaced) VLAN tag on egress can indicate the source port of the
packet. Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8304MB also provides an option to admit VLAN tagged packets with a specific PVID only. If this
function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.

8.1.3. IEEE 802.1Q Tagged-VID Based VLAN

The RTL8304MB supports 16 VLAN entries to perform IEEE 802.1Q-tagged VID-based VLAN
mapping. The RTL8304MB uses a 12-bit explicit identifier in the VLAN tag to associate received packets
with a VLAN. If the VID of a VLAN-tagged frame does not match any of the 16 VLAN entries, the
RTL8304MB will drop the frame. Otherwise, the RTL8304MB compares the explicit identifier in the
VLAN tag with the 16 VLAN IDs to determine the VLAN association of this packet, and then forwards
this packet to the member set of this VLAN. Two VIDs are reserved for special purposes. One of them is
all 1’s, which is reserved and currently unused. The other is all 0’s, which indicates a priority tag. A
priority-tagged frame should be treated as an untagged frame.
When ‘802.1Q tag aware VLAN’ is enabled, the RTL8304MB performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q
tag aware VLAN’ is disabled, the RTL8304MB performs only port-based VLAN mapping both on non-
tagged and tagged frames.

8.1.4. Insert/Remove/Replace Tag

The RTL8304MB supports the VLAN Insertion/Removal/replacing action for each port. The 802.1Q
VLAN tags can be inserted, removed, or replaced based on the port’s setting.

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8.1.5. Ingress and Egress Rules

The RTL8304MB provides flexible VLAN ingress and egress rules to permit comprehensive traffic
control. The RTL8304MB can filter packets on ingress according to the tag condition of the packet. For a
normalized VLAN application and VLAN translation application, each of the RTL8304MB ports can be
independently configured to:
• ‘admit all frames’
• ‘admit only tagged frames’
• ‘admit only untagged frames’
Note: The priority tagged frame (VID=0) will be treated as an untagged frame.
The RTL8304MB also can optionally discard a frame associated with a VLAN of which the ingress port
is not in the member set.
For the egress filter, the RTL8304MB drops the frame if this frame belongs to a VLAN but its egress port
is not one of the VLAN’s member ports. However, there are 5 leaky options to provide exceptions for
special applications.
• ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup
table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress
rule
• ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to
all the multicast address group member sets, ignoring the VLAN member set domain limitation
• ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded
to all the other ports, ignoring the VLAN member set domain limitation
• ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule
• ‘Inter-VLAN mirror function’ enables the inter-VLAN mirror function, ignoring the VLAN member
set domain limitation. The default value is ‘Enable the inter-VLAN mirror’

8.2. IEEE 802.1p Remarking Function

The RTL8304MB provides IEEE 802.1p Remarking ability. Each port can enable or disable IEEE 802.1p
Remarking ability.
In addition, there is a RTL8304MB global IEEE 802.1p Remarking Table. When one port enables 802.1p
Remarking ability, 2-bit priority (not QID) determined by the RTL8304MB is mapped to 3-bit priority
according to the 1p Remarking Table.
If the port’s 1p remarking function is enabled, transmitting VLAN tagged packets will have the 1Q
VLAN tag’s Priority field replaced with the 3-bit 1p remarking Priority.
When the VLAN tags are inserted to non-tagged packets, the inserted tag’s priority will accord with the
1p remarking table, even if the port’s 1p remarking function is disabled. When the VLAN tag is replaced
on tagged packets and the 1p remarking function is disabled, the VLAN tag’s VID will be replaced but
the priority will not change. For a VLAN-tagged packet, the VID and 3-bit priority can be replaced by the
RTL8304MB independently.

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8.3. QoS Function

8.3.1. Bandwidth Control
8.3.1.1 Output (TX) Bandwidth Control
The RTL8304MB supports MIN-MAX packet scheduling.
Packet scheduling offers three modes:
• Type I leaky bucket, which specifies the average rate of one queue (see Figure 15; only Q2 and Q3
have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in
steps of 64kbps
• Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee
the minimal packet rate of one queue
• Port bandwidth control (type II leaky bucket) to control the bandwidth of the whole port. The port rate
can be configured from 0kbps to the line rate in steps of 64kbps
In addition, the RTL8304MB can select one of the two sets of packet-scheduling configurations according
to the packet-scheduling mode. Figure 15 shows the RTL8304MB packet-scheduling diagram.

Figure 15. Packet-Scheduling Diagram

Weighted Round Robin (WRR)

WRR adds weighting on the basis of Round Robin; for example, assume Q3:Q2:Q1:Q0: 4:3:2:1, then the
transmit order will be:
Q0->
Q1->Q1->
Q2->Q2->Q2->
Q3->Q3->Q3->Q3->
WRR guarantees a minimal packet rate for one queue only.
If there is strict priority (only in Q2 and Q3) and WRR at the same time, the queue with strict priority has
higher priority than WRR. When the scheduler scans queues, queues with strict priority are scanned first,
and then the other queues are scanned according to WRR. If there is more than one queue with strict
priority, the queue with the bigger QID has higher priority.
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8.3.1.2 Input (RX) Bandwidth Control
Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on flow
control status. The input bandwidth can also be configured from 0kbps to the line rate in steps of 64kbps.

8.3.2. Priority Assignment

Priority assignment specifies the priority of a received packet according to various rules. The
RTL8304MB can recognize the QoS priority information of incoming packets to give a different egress
service priority.
The RTL8304MB identifies the priority of packets based on several types of QoS priority information:
• Port-based priority
• IEEE 802.1p/Q VLAN Priority Tag
• DSCP Priority field
• IP Address
• Reassigned priority
• RLDP priority
Below is a block diagram of the priority assignment.

Figure 16. RTL8304MB Priority Assignment Diagram

8.3.2.1 Queue Number Selection

In the RTL8304MB, the output queue number can be set. All ports follow a global configuration. The
maximum number of output queues per port is 4. After changing the queue number via SMI (Serial
Management Interface), the external device must perform a soft reset in order to update the configuration.
8.3.2.2 Port-Based Priority Assignment
Each physical port is assigned a 2-bit priority level. Packets received from a high-priority port are sent to
the high-priority queue of the destination port. Port-based priority can be disabled by register setting.

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8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment
In IEEE 802.1Q-based priority assignment, when a packet is VLAN-tagged or priority-tagged, the 3-bit
priority is specified by tag. When a packet is untagged, the 802.1Q-based priority is assigned to the
default 2-bit priority information of a physical port. So, each port must provide a default 2-bit priority
(every received packet must be assigned a 2-bit 1Q-Based Priority). When the priority comes from a
packet, the 1Q-based priority is acquired by mapping 3-bit tag priority to 2-bit priority though an
RTL8304MB 1Q-based Priority Mapping Table. The 1Q-based priority can be disabled.
8.3.2.4 DSCP-Based Priority Assignment
DSCP (Differentiated Services Code Point)-based priority assignment maps the DSCP of an IP packet to
2-bit priority information through a DSCP to priority table, as DSCP is only in the IP packet. A non-IP
packet (such as a Layer 2 frame, ARP, etc) will get a NULL instead of a 2-bit priority. For an IPv6 IP
header, DSCP-based priority assignment acquires the DSCP value according to the class of IPv6 header.
In the RTL8304MB, DSCP-based priority assignment provides a DSCP to Priority Table of all DSCP
value. If the DSCP of a packet is not matched in the table, the DSCP-based priority is 2’b00. The DSCP-
based priority can be disabled by register.
8.3.2.5 IP Address-Based Priority
When IP-based priority is enabled, any incoming packets with source or destination IP address equal to
the configuration in register IP Priority Address [A] and IP Priority Mask [A], or IP Priority Address [B]
and IP Priority Mask [B] will be set to a 2-bit priority.
IP priority [A] and IP priority [B] may be enabled or disabled independently. IP address-based priority
can be enabled or disabled by the control register.
8.3.2.6 Reassigned Priority
RTL8304MB can reassign the priority mainly according to the packets’ DMAC information. This
function is used to differentiate the priority of the Layer 2 control packet, broadcast packet, multicast
packet, unicast packet, and so on.
8.3.2.7 RLDP-Based Priority
To support the loop detection effectively, the RTL8304MB provides the RLDP-based priority
assignment. When it is enabled, the pre-defined priority will be assigned to all RLDP packets.

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8.3.2.8 Packet Priority Selection
As one received packet may simultaneously support several priority assignment mechanisms, e.g., Port-
Based Priority, 1Q-Based Priority, DSCP-Based Priority, it may get several different priority values.
• RLDP-based priority has the highest priority
• If RLDP-based priority is disabled, the final priority is equal to the reassigned priority
• If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address
priority
• If RLDP-based priority, reassigned priority and IP address priority are disabled, the following rules
are used to decide a final priority for the other five types of priority
There is a 2-bit register for each of the three types of priority that represent the weight of the priority. The
higher value in the register indicates a higher weight for the priority. If more than one of the three types of
priority is the same, the final priority will be the one of the three types, whose priority value is greatest.
Queue Priority Mapping
The 2-bit priority has four numbers; however, every port has at most four output queues, so every port
needs a User Priority to Traffic Class Mapping Table to map the priority to QID. A set of Traffic Class
Mapping Tables is provided for each port independently. There is a mechanism to prevent a problem
caused by mapping the traffic to an unused queue. For example, when a port’s queue number is 2, the
queue 2 and queue 3 are not used and mapping the traffic to queue 2 or queue 3 will cause the system to
crash. In the mechanism, traffic mapped to the unused queue will be forced to the highest used queue
(queue 2 in a 3-queue case, queue 1 in a 2-queue case, queue 0 in a 1-queue case). In the example, the
traffic mapped to a port’s queue 2 or queue 3 will be forwarded to queue 1.

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8.4. Lookup Table Function

8.4.1. Function Description
• 2048-entry lookup table (LUT)
• 4-way entry for each entry index
• Supports LRU (Least Recently Used) function for lookup table learning

8.4.2. Address Search, Learning, and Aging

Received packets are forwarded according to the information learned or written into the LUT. When a
packet is received, the RTL8304MB tries to retrieve learned information and assign a forwarding
destination port to the packet.
The 48-bit destination MAC address (DA) of the received packet and the 2-bit FID are used to calculate a
9-bit index value. The hash algorithm uses all 48 bits of the MAC address and 2 bits of the FID. The hash
algorithm is shown below.
Index 0 = MAC4 ^ MAC11 ^ MAC18 ^ MAC25 ^ MAC32
Index1 = MAC3 ^ MAC10 ^ MAC17 ^ MAC24 ^ MAC47
Index2 = MAC2 ^ MAC9 ^ MAC16 ^ MAC39 ^ MAC46
Index3 = MAC1 ^ MAC8 ^ MAC31 ^ MAC38 ^ MAC45
Index4 = FID1 ^ MAC0 ^ MAC23 ^ MAC30 ^ MAC37 ^ MAC44
Index5 = FID0 ^ MAC15 ^ MAC22 ^ MAC29 ^ MAC36 ^ MAC43
Index6 = MAC7 ^ MAC14 ^ MAC21 ^ MAC28 ^ MAC35 ^ MAC42
Index7 = MAC6 ^ MAC13 ^ MAC20 ^ MAC27 ^ MAC34 ^ MAC41
Index8 = MAC5 ^ MAC12 ^ MAC19 ^ MAC26 ^ MAC33 ^ MAC40
As the 9-bit MAC addresses, MAC[13:15] and MAC[0:5], are not stored in the LUT entries, these MAC
address bits should be calculated from the index information via the following method when the hash
algorithm is selected.
MAC0 = Index4 ^ FID1 ^ MAC23 ^ MAC30 ^ MAC37 ^ MAC44
MAC1 = Index3 ^ MAC8 ^ MAC31 ^ MAC38 ^ MAC45
MAC2 = Index2 ^ MAC9 ^ MAC16 ^ MAC39 ^ MAC46
MAC3 = Index1 ^ MAC10 ^ MAC17 ^ MAC24 ^ MAC47
MAC4 = Index0 ^ MAC11 ^ MAC18 ^ MAC25 ^ MAC32
MAC5 = Index8 ^ MAC12 ^ MAC19 ^ MAC26 ^ MAC33 ^ MAC40
MAC13 = Index7 ^ MAC6 ^ MAC20 ^ MAC27 ^ MAC34 ^ MAC41
MAC14 = Index6 ^ MAC7 ^ MAC21 ^ MAC28 ^ MAC35 ^ MAC42
MAC15 = Index5 ^ FID0 ^ MAC22 ^ MAC29 ^ MAC36 ^ MAC43

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The hashed index key is used to locate a matching LUT entry. There are 4 entries sharing one index key
(Table 16). This is called a 4-way hash. It is helpful to minimize address collisions in the address learning
process. The address search engine compares the DA packet with the data in 4 entries, from entry 3 to
entry 0. The final forwarding destination is abstracted from the first matching entry. If the address search
fails to return a matching LUT entry, the packet will be flooded to appropriate ports.
Table 16. L2 Table 4-Way Hash Index Method
Index Entry 0 Entry 1 Entry 2 Entry 3
0x00 MAC Addr 0 MAC Addr 1 MAC Addr 2 MAC Addr 3
0x01 MAC Addr 4 MAC Addr 5 MAC Addr 6 MAC Addr 7
0x02 MAC Addr 8 MAC Addr 9 MAC Addr 10 MAC Addr 11
… … … … …
0x1FE MAC Addr 2040 MAC Addr 2041 MAC Addr 2042 MAC Addr 2043
0x1FF MAC Addr 2044 MAC Addr 2045 MAC Addr2046 MAC Addr 2047

Address learning is the gathering process and storing of information from received packets for the future
purpose of forwarding frames addressed to the receiving port. The information includes the source MAC
address (SA) and the receiving port. As with the hash algorithm, an address search is used in address
learning. The SA of the received packet is used to calculate the entry index. The receiving port
information and the aging timer of the first matching entry will be updated when an address is learned. If
there is no matching entry, the packet’s information will be ‘learned’ into the first empty entry. The SA
will not be learned when all of the 4 entries are occupied. The address learning process can be disabled on
a per-port basis via register setting.
For unicast packet learning & search, and multicast packet search, the RTL8304MB applies the same 4-
way hash algorithm.
Address aging is used to keep the contents of the learned address table updated in a dynamic network
topology. The look-up engine will update the aging timer of an entry whenever the corresponding SA
appears. An entry will be invalid (aged out) if its aging timer is not refreshed by the address learning
process during the aging time period. The aging time of the RTL8304MB is between 200 and 400
seconds. The RTL8304MB also supports a fast aging function that is used to age all dynamic entries
within 1ms.

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8.4.3. Lookup Table Definition

In traditional switch learning, if a MAC address hash collision occurs then the later MAC address in the
collision will not be learned into the lookup table. The LRU function attempts to resolve this problem.
When Enable LRU = 0b1, then the LRU function is enabled. If the Source MAC address of the incoming
packet encounters a hash collision during the learning process and when the 4-way entries are all
occupied, then the switch will learn the address in one of the 4-way entries using the LRU aging timer.
The criteria for selecting the entry to over-write is comparing via the aging timer and choosing the oldest
entry. If the aging timer of the 4 entries are the same, then the entry with the highest Entry_Address[1:0]
value is selected to be over-written.

8.5. Storm Filter Function

The RTL8304MB can effectively control four-types of broadcast storms; those caused by broadcast
packets, multicast packets, unknown multicast packets, and unknown DA unicast packets.
Note: Broadcast packets discussed here are packets whose DA is ff-ff-ff-ff-ff-ff.
Multicast packets include all multicast packets and only unknown multicast packets, which are those
whose DA is a multicast address, but excluding 01-80-C2-00-00-xx.
An unknown DA unicast packet is a packet whose DA is a unicast address and is not found in the lookup
table of the switch.
The RTL8304MB can configure a storm filter rate for these four packet types, and the rate unit can be
configured as packet-based or byte-based via registers. The storm filter rate limits the packet forwarding
rate to less than the rate threshold.

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8.6. Input and Output Drop Function

If some destination ports are blocking, or the buffer is full, the frames to these ports will be dropped.
There are two types of drop:
• Input Drop: Drop the frame directly. Do not forward to any port
• Output Drop: Forward only to non-blocking ports
For the RTL8304MB, the dropping of broadcast, multicast, and unknown DA frames can be controlled
independently.
1 . Broadcast packet from Port.0
2 . Buffer of Port3 is full, others are not full
.

RX : Port0 1 2 3 RX : Port0 1 2 3
Full Full

Input Drop Output Drop

Figure 17. Broadcast Input Drop vs. Output Drop

1 . Multicast packet from Port. 0

2 . Buffer of Port3 is full, Port 1 is not full.

RX : Port0 1 2 3 RX : Port0 1 2 3
Full Full

Input Drop Output Drop

Figure 18. Multicast Input Drop vs. Output Drop

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8.7. LED Function

The RTL8304MB provides flexible LED functions for diagnostics. The LEDs can be configured to
indicate the link information (link, activity, speed, duplex), and collision & loop detection information.
The parallel LED for each port indicates the port’s link information when loop-detection is disabled or no
loop condition occurs. If the loop is detected on a port, the parallel LED will blink.
All LED statuses are represented as active-low or high depending on input strapping.
LED_BLINK_TIME determines the LED blinking period for activity and collision via register (0: 32ms
and 1: 128ms).
Some LED pins are dual function pins: input operation for configuration upon reset, and output operation
for LED after reset. If the pin input is floating upon reset, the pin output is active high after reset.
Otherwise, if the pin input is pulled high upon reset, the pin output is active low after reset.
Figure 19 shows example circuits for LEDs. Typical values for pull-down resistors are 10KΩ.

Figure 19. Floating and Pull-High of LED Pins for LED

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8.8. Energy-Efficient Ethernet (EEE)

The RTL8304MB supports Energy-Efficient Ethernet (EEE) function as defined in IEEE 802.3az. The
EEE function implements the Low Power Idle (LPI) mode at 100Mbps operation to save power during
periods of low link utilization. In Low Power Idle mode, devices on both sides of the link disable portions
of the functionality to lower the power consumption.
At the transmitter side, the RTL8304MB port 0~2 can automatically enter or quit LPI mode based on
their transmission loading. When a port’s EEE function is enabled, the transmission loading is monitored
in real time. If the transmission loading is lower than a preset threshold, this port’s transmission circuit
will enter LPI mode during the idle period. When there are packets to be transmitted, this port wakes up
and quits LPI mode.
There are two types of wake-up:
• Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the
port immediately
• Packet in a low priority queue that reach a preset number. A port in LPI mode can be woken up by low
priority packets when the number of the cumulated low priority packets exceeds the preset threshold
or a delay timer expires
At the receiver side, each embedded PHY of the RTL8304MB will automatically respond to the request
from the link partner to enter or quit the LPI mode.
The EEE ability for 100Base-TX on each side of a link should be exchanged via auto-negotiation. Auto-
negotiation is mandatory when EEE is enabled. The MDIO Manageable Device (MMD), defined in
IEEE 802.3, Clause 45, should also be supported, as the EEE register is located in the MMD of each
PHY.
The RTL8304MB also supports EEE at 10Mbps operation by reducing the transmit amplitude (10Base-
Te). 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of Category 5 or better cable.
The EEE function for each port is enabled by default and can be disabled independently via strapping pin,
registers, or EEPROM configurations.

8.9. Cable Diagnosis

The RTL8304MB physical layer transceivers use DSP technology to implement the Realtek Cable Tester
(RTCT) feature for cable diagnosis. The RTCT feature can detect short, open, or normal in both
differential pair signal runs.

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9. Characteristics
9.1. Electrical Characteristics/Maximum Ratings
WARNING: Maximum ratings are limits beyond which permanent damage may be caused to the device
or which may affect device reliability. All voltages are specified reference to GND unless otherwise
specified.
Table 17. Electrical Characteristics/Maximum Ratings
Parameter Min Max Units
DVDDH, AVDDH, AVDDHPLL Supply Referenced to GND GND-0.3 +3.63 V
DVDDL, AVDDL, AVDDLPLL Supply Referenced to GND GND-0.3 +1.10 V

9.2. Operating Range

Table 18. Operating Range
Parameter Min Max Units
Storage Temperature -55 +150 °C
Ambient Operating Temperature (Ta) 0 +70 °C
3.3V Vcc Supply Voltage Range (DVDDH, AVDDH, AVDDHPLL) 3.13 3.47 V
1.0V Vcc Supply Voltage Range (DVDDL, AVDDL, AVDDLPLL) 0.95 1.05 V

9.3. DC Characteristics
Table 19. DC Characteristics
Parameter SYM Condition Min Typical Max Units
TTL Input High Voltage Vih - 2.0 - - V
TTL Input Low Voltage Vil - - - 0.8 V
TTL Input Current Iin - -10 - 10 µA
TTL Input Capacitance Cin - - 3 - pF
Output High Voltage Voh - 2.25 - - V
Output Low Voltage Vol - - - 0.4 V
Output Three State |IOZ| - - - 10 µA
Leakage Current
Power Supply Current for Icc 10Base-T, idle - 32 - mA
1.0V 10Base-T, Peak continuous 100% utilization - 33 -
100Base-TX, idle - 62 -
100Base-TX, Peak continuous 100% utilization - 62 -
Link down - 32 -
Power Supply Current for Icc 10Base-T, idle - 23 - mA
3.3V 10Base-T, Peak continuous 100% utilization - 60 -
100Base-TX, idle - 68 -
100Base-TX, Peak continuous 100% utilization - 68 -
Link down - 23 -

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Parameter SYM Condition Min Typical Max Units
Total Power Consumption PS 10Base-T, idle - 108 - mW
for All Ports 10Base-T, Peak continuous 100% utilization - 231 -
100Base-TX, idle - 287 -
100Base-TX, Peak continuous 100% utilization - 287 -
Link down - 108 -
Note: All power supply currents are measured under the following conditions:
1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V.
2. Room temperature.
3. The EEE and Green features are disabled.
4. All LEDs are in low-active mode.
5. LDO power is not included.

9.4. Digital Timing Characteristics

9.4.1. RMII Interface Timing
9.4.1.1 RMII Timing
Table 20. RMII Timing
Parameter SYM Description I/O Min Type Max Units
REFCLK Tcyc REFCLK clock cycle time I/O 20+50 20 20-50 ns
ppm ppm ppm
TXD[1:0], TXEN TOS TXD[1:0], TXEN to REFCLK rising O 4 - - ns
Setup Time edge setup time
TXD[1:0], TXEN TOH TXD[1:0], TXEN to REFCLK rising O 2 - - ns
Hold Time edge hold time
RXD[1:0],CRSDV TIS RXD[1:0], CRSDV to REFCLK I 4 - - ns
Setup Time rising edge setup time
RXD[1:0], CRSDV TIH RXD[1:0], CRSDV to REFCLK I 2 - - ns
Hold Time rising edge hold time

9.4.2. LED Timing

Table 21. LED Timing
Parameter SYM Condition Min Typical Max Units
LED On Time tLEDon LED Blinking to Indicate Link Information 32 - 128 ms
LED Off Time tLEDoff LED Blinking to Indicate Link Information 32 - 128 ms

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9.4.3. Reception/Transmission Data Timing of SMI Interface

Figure 20. Reception Data Timing of SMI Interface

Figure 21. Transmission Data Timing of SMI Interface

Table 22. SMI Timing

Parameter SYM Description I/O Min Type Max Units
MDC Tcyc MDC Clock Cycle I 400 - - ns
MDIO Input Setup Time TIS MDIO to MDC Rising Edge Setup Time I 50 - - ns
MDIO Input Hold Time TIH MDIO to MDC Rising Edge Hold Time I 10 - - ns
MDIO Output Delay Time TD MDIO to MDC Rising Edge Output Delay O 2 - 10 ns

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9.4.4. EEPROM Auto-Load Timing

Figure 22. EEPROM Auto-Load Timing

Table 23. EEPROM Auto-Load Timing Characteristics

Symbol Description Min Typical Max Units
t1 SCL High Time - 2.52 - µs
t2 SCL Low Time - 2.52 - µs
t3 START Condition Setup Time - 2.52 - µs
t4 START Condition Hold Time - 2.52 - µs
t5 Data In Hold Time 0 - - ns
t6 Data In Setup Time 100 - - ns
t7 Data Output Hold Time - 1.28 - µs
t8 STOP Condition Setup Time - 2.52 - µs

Single-Chip 4-Port 10/100Mbps Ethernet Switch Controller 41 Track ID: JATR-8275-15 Rev. 1.0
 RTL8304MB
Datasheet

10. Mechanical Dimensions

Single-Chip 4-Port 10/100Mbps Ethernet Switch Controller 42 Track ID: JATR-8275-15 Rev. 1.0
 RTL8304MB
Datasheet

10.1. Mechanical Dimensions Notes

Symbol Dimension in mm Dimension in inch
Min Nom Max Min Nom Max
A 0.75 0.85 1.00 0.030 0.034 0.039
A1 0.00 0.02 0.05 0.000 0.001 0.002
A3 0.20 REF 0.008 REF
b 0.15 0.20 0.25 0.006 0.008 0.010
D/E 6.00BSC 0.236BSC
D2/E2 4.15 4.4 4.65 0.163 0.173 0.183
e 0.40BSC 0.016BSC
L 0.30 0.40 0.50 0.012 0.016 0.020
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.

11. Ordering Information

Table 24. Ordering Information
Part Number Package Status
RTL8304MB-CG 48-Pin QFN in ‘Green’ Package (RoHS Compliant)
Note: See page 5 for package identification.

Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Single-Chip 4-Port 10/100Mbps Ethernet Switch Controller 43 Track ID: JATR-8275-15 Rev. 1.0