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Improved handling of false and multicycle paths in ATPG

Conference Paper · January 2006

DOI: 10.1109/VTS.2006.38 · Source: IEEE Xplore

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 Improved Handling of False and Multicycle Paths in ATPG

Vlado Vorisek Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami

Freescale Semiconductor Mentor Graphics Corporation
[email protected] [email protected]

Abstract 2. Terminology
As electronic design feature sizes continue to Performing STA is a common practice in today’s
shrink and clock speeds continue to rise, more and design flows to ensure that a circuit design is free of
more companies have turned to at-speed test timing violations [6]. The term false path is
techniques to help ensure high test and product commonly used by STA users when verifying the
quality. An important piece of the design flow is timing performance of a design. A false path in a
Static Timing Analysis (STA), which is used to verify circuit is a path that is never activated during
the timing of paths in the design. Part of the STA functional operation [7]. However, a scan-in
process is to specify false and multicycle path operation can load in non-functional states, which
exceptions to relax the timing for these paths for may sensitize these paths during scan-based at-speed
synthesis and layout purposes. This paper explains test.
the importance of using these timing path exceptions Before running timing analysis the user loads
during Automatic Test Pattern Generation (ATPG) the design into the STA tool, specifies the clocks and
and compares previous methods of handling these timing constraints, and then adds the timing
paths to a new innovative method that provides exceptions. These timing exceptions are used to
higher test and product quality. override the default single-cycle clock constraints
and can be applied to any timing path. In
1. Introduction PrimeTime , a widely used STA tool from
Synopsys, the command to specify false path timing
It is commonly understood that at-speed testing exceptions is set_false_path. This command has a
is a requirement for modern electronic designs. The number of command options including –from, -to,
high clock speeds and small geometry sizes found in and –through. These options are followed by one or
today’s integrated circuits have led to an increase in more design locations such as input & output ports,
speed related defects. Fortunately, effective scan- or internal pin names. By specifying false paths, the
based at-speed test techniques are available in leading user is defining paths that the STA tool should not
ATPG tools [1][2]. The most common at-speed tests evaluate for timing. This is a key step that enables the
to check for manufacturing defects and process design to meet timing closure while doing logic
variations include test patterns created for the synthesis and physical place and route.
transition and path delay fault models. The basic
methodologies of creating at-speed test patterns are
covered in numerous sources [3][4][5]. This paper
focuses on the test issues dealing with false and
multicycle paths while creating at-speed test patterns.
If these paths are not handled correctly during scan-
based at-speed test pattern generation, it can lead to
failing good chips on the tester which reduces the
product yield. Figure 1: Logic circuit example
The paper is organized as follows: Section 2 Figure 1 shows part of a logic circuit. Here are a few
explains terminology and the process of specifying examples of using the set_false_path command to
false and multicycle paths during static timing specify false path timing exceptions.
analysis (STA). Section 3 discusses the traditional
methods of handling timing exceptions in ATPG > set_false_path –from CLK1 –to U5/D
tools. Section 4 describes a new method of > set_false_path –from CLK1 –to CLK2
accounting for false and multicycle paths during > set_false_path –through G5/out
ATPG. A real world test case and the results of using These examples can be used inside a Tool Command
both the new and old methods are shown in Language (Tcl) script and the resulting Tcl script can
Section 5. Section 6 concludes the paper.

Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06)

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 serve as an input to various design and test tools It is important when specifying these timing
including synthesis, timing analysis, place and route, exceptions to be specific and accurate. For example,
and test generation. The arguments of the if the following command is used:
set_false_path command are commonly specified
> set_false_path –from U3
with the design object access functions: 1) get_pins
for accessing an instance pin, 2) get_clocks for the result is illustrated in Figure 3.
accessing a clock, 3) get_ports for accessing a port,
or 4) get_nets for accessing a net etc. The following
example shows the usage of design object access
functions get_clocks and get_pins with the
set_false_path command:
> set_false_path –from [get_clocks {CLK1}] \
–to [get_pins {U5/D}]
An alternate command to specify false path timing
exceptions is set_disable_timing. This command can
be used to improve STA runtime performance.
Multicycle paths are similar to false paths in that
they need to be defined as timing exceptions in the
STA tool. A path is considered to be multicycle if the
combined time delay through the path is greater than
the single cycle clock period. Figure 2 shows an Figure 3: Effect cone
illustration of this.
This diagram shows that if only the –from or source
node is specified, the effects of that propagates out
through the design in an effect cone. This may be
correct and intended, but if not, can lead to incorrect
timing specifications and lower test coverage.
Once the STA process is completed, the
write_sdc command should be used to write out a file
in Synopsys Design Constraints (SDC) format. This
SDC format is a de facto industry standard format
that is used by many design tools. This file contains
all the timing constraint and exception information.
When creating at-speed or near at-speed test
patterns in an ATPG tool, it is very important to
provide the tool with this same timing exception
information that was used by the STA tool. It doesn’t
Figure 2: Multicycle path example make sense to try to test paths at-speed if they are not
designed to operate that way in the first place. Failing
This diagram shows path P1 that starts at flip-flop U1 to account for these timing exceptions while creating
and goes through gates G1, G3, G5, G6, and ends at at-speed test patterns can lead to pattern simulation
flip-flop U5. This path has a total propagation delay mismatches and incorrect fails when the patterns are
that is longer than the clock period for CLK1. To run on the automatic test equipment (ATE) with the
specify this timing exception in STA, use the silicon. Hence to get accurate results, the timing
set_multicycle_path command which has similar – exception information should be read into the ATPG
from, -to, and –through switches. For this example, it tool before creating at-speed test patterns. With this
would look like this: information, the tool can do some analysis and
determine the correct expected results for each test
> set_multicycle_path –from U1 –to U5
pattern. This will produce accurate test coverage
Or to be more explicit in the definition of the numbers and eliminates simulation mismatches when
multicycle path, the through gates could also be the completed at-speed test patterns are simulated
specified in the timing exception. with timing in a functional simulator.

Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06)

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 3. Traditional Methods along with the test patterns. It eliminates the tedious
manual steps of generating cell constraints and
Most existing methods of handling timing pattern masks. The correctness of the generated at-
exception paths in the ATPG tools while creating at- speed patterns is guaranteed such that they will not
speed patterns have relied on the addition of some fail on the tester. The automated methodology is
type of constraint or to apply pattern masks. The comprised of the following procedural steps:
common approach has been to analyze the paths so
that appropriate cell constraints, such as forcing to an 4.1 Entering the Timing Exception Paths
X value, could be specified for source and/or sink The timing exception paths are read into the
cell locations on the false and multicycle paths [8]. ATPG tool from one or more SDC files. False path
While using cell constraints can be effective in information is extracted from the SDC commands
ATPG for some situations [9], there are a number of set_false_path and set_disable_timing. Multicycle
drawbacks to using this method for handling timing path information is extracted from the SDC command
exceptions. First, the process of determining the set_multicycle_path. The tool also automatically
correct locations at which to place the cell constraints handles the SDC commands set_case_analysis,
is a manual and tedious process. Second, it is overly create_generated_clock, create_clock, and
pessimistic, so test and product quality suffers. When set_hierarchy_separator.
an X constraint is added to a capture scan cell, all the Alternatively, if a SDC file is not available for
faults on the paths that could be observed there are the design, the timing path exceptions can be entered
now unobservable. This is illustrated in Figure 4. with the ATPG tool commands add false path and
add multicycle path.
4.2 Marking the Path Cone
SC3
SC1 After reading in the timing exception paths, these
X paths are marked inside the circuit and used during
at-speed pattern generation. Here the complete set of
SC2 gates belonging to a timing exception path is
identified. This involves multiple forward and
backward traversals of the path cone defining the
timing exception paths.
Consider the circuit shown in Figure 2. Let P1 be
Figure 4: Cell constraint example a timing exception path from U1/Q to U5/D. The
timing exception path P1 consists of a single section
In this example, if a cell constraint was added to SC3
with source node U1/Q and sink node U5/D. The
for the false path from scan cell SC1 to SC3, all the
gates U1, G1, G3, G5 and G6 belong to both the
paths that could use SC3 as their observation point
forward cone of source node U1/Q and the backward
will lose fault coverage.
cone of sink node U5/D. Hence these gates define the
This drawback leads to a third potential problem.
complete timing exception path from U1/Q to U5/D.
With design size and test pattern count growth, most
Consider the circuit shown in Figure 5. For this
companies are using or evaluating test compression
example, the timing exception path is from Reg_A[4]
solutions. While the Xs in test patterns affect all test
to Reg_B[2] through the node G. This path has two
compression techniques, the large numbers of Xs
sections.
introduced by the cell constraints method have a very
0
negative impact on compression results.
1
Finally, for some complicated timing exception
paths, generating a complete set of constraints and 2 0

masks is difficult and error prone. This results in at- 3 G 1

speed test patterns that may fail on the ATE. 4 2
Source 5 3 Sink
4. The New Method 6
Through Node Reg_B
7
To overcome the pessimism and other drawbacks
of the existing methodologies, a patent pending Reg_A
method was developed to handle false and multicycle Figure 5: Path cone example
paths more effectively during at-speed pattern
generation [10]. The new method removes the Section 1 has source node of Reg_A[4] and sink node
pessimism by considering complete path information as G. Section 2 has source node as G and sink node

Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06)

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 as Reg_B[2]. Cone tracing is performed on each the false path P1 had an at-speed transition at its
section separately. Section 1 consists of gates which input at a time frame less than t. Even though there is
are part of both the forward cone of source node no current at-speed transition at the input of the false
Reg_A[4] and the backward cone of sink node G. path P1, sensitization check is performed for this path
The gates belonging to both the forward cone of at the current time frame t. This is done because the
source node as G and the backward cone of sink node delay along a false path is unknown. If the
as Reg_B[2] form section 2. All the gates belonging sensitization condition of the false path P1 is
to section 1 and section 2 define the complete timing satisfied, the affected end points are assigned the
exception path and in Figure 5 they are shown in the unknown logic value at the current time frame and
cross-marked regions between the cones. the effect of these unknown states is propagated
forward by performing a conventional logic
4.3 Checking Path Sensitization simulation. Slow events like scan load/unload
The logic values at the start points of a timing operations, slow clock events, etc. clear the past
exception path are examined. If an at-speed transition transitions for future consideration.
is found at a start point, the original logic value is For multicycle paths with propagation delay d,
stored and logic value X (representing unknown logic any previous at-speed transitions at the inputs in time
value) is injected. The effects of the injected Xs are frames less than t and greater than (t – d) are
propagated forward through the gates that define the considered for sensitization check. The sensitized
complete timing exception path by performing event multicycle paths are handled according to the same
driven logic simulation. During the event driven rules as just explained for false paths.
simulation the original logic value at a gate is stored To illustrate the above method, consider the
if logic value X is propagated through this gate. At circuit with logic states for a given test pattern shown
the end of the simulation the end points of the timing in Figure 6. The test pattern has four time frames t1,
exception path are examined and the end points with t2, t3 and t4. Logic states at U1/Q are 0, 1, 1 and 1 in
logic value X are stored in a data structure called an time frames t1, t2, t3 and t4 respectively. Logic states
X-mask list. If all the end points have logic value X, at U5/D are 1, 0, 0 and 1 in time frames t1, t2, t3 and t4
the timing exception path is fully sensitized. If logic respectively.
value X is found at a subset of the end points, the
timing exception path is partially sensitized. If none
of the end points have logic value X, the timing
exception path is not sensitized. Once the
sensitization check is done, the original state of the
circuit is restored.
4.4 Identifying the Unknown States
During the generation of each at-speed test
pattern the effects of the timing exception paths are
considered. There are multiple time frames in a given
at-speed test pattern. The unknown states due to
sensitization of these timing exception paths are
identified for each of these time frames. As described
in the procedural step 4.3, the sensitization checks of
the timing exception paths are performed and the X- Figure 6: Circuit states without false path
mask list is populated for each time frame. After
populating the X-mask list, the original circuit state is Suppose there is a false path P1 from U1/Q to
restored. The logic value X is then injected at the U5/D and the effect of this false path needs to be
circuit nodes belonging to the X-mask list and the considered for this test pattern. At time frame t2, there
effect of these unknown states is propagated forward is a rising transition (0−>1) at U1/Q and the false
by performing logic simulation. path sensitization check for P1 is carried out. The
false path P1 is found to be sensitized and U5/D is
4.5 Sustaining the Effect of Past assigned to logic value X in time frame t2 and the
Transitions effect is propagated forward. At time frame t3, there
Sustaining the effect of past transitions at the is no transition at U1/Q. However there was a past
input of the timing exception paths needs to be rising transition (0−>1) at U1/Q in time frame t2 and
considered for each time frame in a given at-speed the false path sensitization check for P1 is carried out
test pattern. Suppose the current time frame is t and in time frame t3. The false path P1 is found to be

Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06)

0-7695-2514-8/06 $20.00 © 2006 IEEE
 sensitized and U5/D is assigned to logic value X in 5. Test Case and Experimental Results
time frame t3 and the effect is propagated forward. At
time frame t4, there is no transition at U1/Q but there The new methodology for efficiently handling
was a past rising transition (0−>1) in time frame false and multicycle paths was used and extensively
tested on a number of different size and style industry
t2. The false path sensitization check for P1 is carried
designs with good results. Here are the details of a
out in time frame t4 and P1 is found to be not
case study with one of these designs.
sensitized. Therefore the original logic state 1 is
The design is a Freescale Semiconductor
retained at U5/D in time frame t4. Figure 7 shows the
MPC5200B device with these characteristics:
logic states considering the effect of false path P1
1) AC scan mode support for transition delay scan
during the four time frames.
patterns. 2) PLL based internally generated AC scan
clocks and broadside clock waveforms are
configurable through JTAG interface. 3) 52 internal
clock domains. 4) Maximum clock transitions at
528MHz. 5) 950k simulation gates (ATPG). 6) 43k
scan cells in 95 scan chains. 7) 2.8M targeted faults.
8) 78 complex false and multicycle path definitions
with wildcards defining approximately 10k paths.
More information about the actual AC scan mode of
this device and some details about the ATPG flow
used were published in [11].
The initial transition delay ATPG was run only
once without any cell constraints or timing exception
definitions. The 30k size was a limit of the
production test time and memory budget for this test
pattern set. Binary patterns were saved for further
fault simulation. The test coverage for this pattern set
Figure 7: Circuit states with false path
was 81.03% with 24M masks (Xs) in the total pattern
These new methods can handle sensitization of set. It is important to note that this test coverage
timing exception paths due to glitches. Consider a number is meaningless because the patterns don’t
timing exception path through an AND gate G. The account for the timing exceptions in the design and
gate G has output Z and inputs A and B. If the input these patterns wouldn’t be used on the tester.
A has a rising transition (0−>1) and the input B has a The stored patterns were then fault simulated
falling transition (1−>0), then the output Z can have a with all the necessary cell constraints to handle
potential glitch (0−>1−>0). In this case, while existing false and multicycle paths as described in
checking path sensitization, the logic value X is Section 3 of this paper. Table 1 presents the results
injected at both inputs A and B, and the gate G is from this flow. As you can see, the test coverage
simulated. This will result in logic value X at the
output Z and the path will be inferred as sensitized Table 1: Test case results
due to potential glitches. Similarly, it can handle the
situation when the input A has a falling transition
Pattern Count
Test Coverage

Total Masks
Definition

(1−>0) and the input B has a rising transition (0−>1).

Count

(%)

The methods presented here can be applied to

any fault model for generating at-speed test patterns.
By applying these methods, the tester ready at-speed
test patterns can be generated in the presence of
timing exception paths. The correctness of test Initial ATPG - 81.03 30k 24M
responses is guaranteed while minimally impacting
Cell
Faultsim. with

the test coverage. For a given design and a complete 4084 73.33 30k 147M
set of design timing exceptions, this automated constraints
solution is far superior to the traditional methods
outlined in Section 3 of this paper. Read SDC 78
78.46 30k 45M
capabilities (10k)

Proceedings of the 24th IEEE VLSI Test Symposium (VTS’06)

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 dropped by 7.7% and the number of masked cells STA engineer at Freescale Semiconductor and Darryl
increased over 6 times when using this methodology Walters, Mark Kassab, Janusz Rajski, and Xijiang
for handling false and multicycle paths. Lin at Mentor Graphics Corporation.
After that, the entire fault simulation flow was
repeated, starting from the same binary pattern set. References:
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directly read in using the Read SDC capabilities of B. Swanson, N. Tamarapalli, “High-frequency, At-
the ATPG tool. This method used the complete path speed Scan Testing”, IEEE Design & Test of
information with the timing exception paths. The Computers, Sept.-Oct. 2003, pp. 17-25.
results from this flow are also presented in Table 1.
[2] M. Beck, O. Barondeau, F. Poehl, X. Lin, R. Press,
Comparing the results from these two flows, it is
“Measures to Improve Delay Fault Testing on Low-
clear that using the timing exceptions provided in the Cost Testers – A Case Study”, Proc. IEEE VLSI Test
SDC file greatly improves the quality of the Symposium, May 2005, pp. 223-228.
generated test patterns. The final pattern set had
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Swanson, G. Aldrich, “Novel techniques for achieving
5.13% higher test coverage compared to the old flow
high at-speed transition fault test coverage for
with pure cell constraints. Motorola’s microprocessors based on PowerPC
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recover all timing critical multicycle-by-2 paths. Symposium, Apr.-May 2002, pp. 3-8.
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Acknowledgements:
We would like to acknowledge these people for
their contributions to this work: Thomas Becker,

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