Paramount

1111
Analog Electronics

Unique Collection of Questions with

Detailed Solutions
 PREFACE

It is our pleasure, that we insist on presenting “Paramount 1111” authored for

Electrical Engineering to all of the aspirants and career seekers. The prime
objective of this book is to respond to tremendous amount of ever growing
demand for error free, flawless and succinct but conceptually empowered
solutions to all the questions.
This book serves to the best supplement for GATE 2023 (EE).
Simultaneously having its salient features the book comprises :
 Step by step solution to all questions.
 Complete analysis of questions through concept wise.
 Solutions are presented in simple and easily understandable language.
The authors do not sense any deficit in believing that this title will in many aspects, be different
from the similar titles within the search of student.
In particular, we wish to thank GATE ACADEMY expert team members for their hard work
and consistency while designing the script.
The final manuscript has been prepared with utmost care. However, going a line that, there
is always room for improvement in anything done, we would welcome and greatly appreciate the
suggestions and corrections for further improvement.

Umesh Dhande
Vice President - Academics GATE & ESE
(UNACADEMY)
 7 Analog Electronics

Questions
Q.1 The comparators (Output = ‘1’ When (D) Output is always bistable on + 8 V
V  V and output  '0' when V  V ), and –10 V
For VS  2sin1000t , the DC component Q.3 The output voltage Vout of the given
of V0 in volt is ________. circuit, for given signal as shown in the
below figure in steady state.
5 V
Vi (t )
VS +
V0 2V
1V –
t
 5V 6 ms 12 ms

Q.2 Consider the schmitt trigger circuit –2V

shown in figure. The following option
is/are correct [MSQ]
+ +
C

Vi (t ) R V0 (t)

– –

(A)

0V

(A) It’s a type of inverting Schmitt 4 V

trigger
(B)
(B) It’s a type of non-inverting Schmitt
trigger 4 V

(C) The hysteresis voltage is approxi- 0V

mately 18 V
 7.2 Paramount 1111 [EE] GATE ACADEMY®
(C) W 
L
2  m2
3
W 
t L
 m1
2
Power dissipation at D1 and D2 are :
(A) 2.1 mW, 0 mW
(D) (B) 0 mW, 2.1 mW
(C) 0 mW, 0 mW
(D) 0.7 mW, 0 mW
Q.6 A Zener diode in the circuit shown in
4 V below figure, has a knee current of 15
Q.4 A voltage (1 2sin t ) is applied to the mA and a maximum allowed power
circuit shown below. The capacitor ‘C’ dissipated 4 W and breakdown voltage
of Zener diode is 15.4 V, otherwise
and diode are considered as ideal, RL is
Zener diode is ideal, the value of the
the resistance of large value.
R 
ratio  L (max)  is ________. (rounded
 RL (min) 
upto two decimal places)
Ri  150 

Ii IZ IL +
The magnitude of average voltage (in
volts) across RL is ________. (in integer Vi  60 V +
– VZ RL VL

only)
–
Q.5 M1 and M 2 in the circuit shown below
Q.7 If unregulated supply change by 1.5 V,
are N - MOSFET operating in saturation
the corresponding change in output
region, forward voltage drop of each
voltage is 86 mV.
diode is 0.7 V, leakage current is
negligible and the Op-Amp is ideal.
5 V 1k

D2
1 mA
D1
–
The incremental resistance of zener
diode is ________  .
+

M1 M2
Q.8 For the circuit shown in the figure
VCC
below, it is given that VCE  . The
2
transistor has   49 and VBE  0.7 V .
GATE ACADEMY® Analog Electronics 7.3

RB (A) 2.11 mA (B) 0.556 mA

For this circuit, the value of is
R (C) 2.67 mA (D) 0.35 mA
________. (rounded opto one decimal
Q.11 The diodes in the circuit shown below
places)
have V  0.7V then output voltage V0
Q.9 For the given circuit, if all the transistors
(in V) is ________. (rounde upto one
are in saturation and channel length
decimal places)
modulation are negligible and threshold
voltage are identical of all transistor the
value of the current ‘ I D 4 ’ (in mA) is
_______. (rounded upto one decimal
places)
I ID4

M3 M4
Q.12 Consider a transistor circuit shown in
I ref
below figure, if value of  is very high
and VBE  0.65V.
M1 M2

W  W  W  W 
      5 ,       10
 L 1  L 3  L 2  L 4
and Iref  2mA
Q.10 In the circuit shown in below figure the
MOSFET parameters are given as The value of the current I (in mA)
nCox  100 A / V2 , VTH  0.5V and flowing through 2kΩ resistance is
  0 . The value of the current flowing ________. (rounde upto one decimal
through the drain is places)
 7.4 Paramount 1111 [EE] GATE ACADEMY®
Q.13 The Op-Amp circuit shown below Trans conductance : gm1 gm2
behaves as a Output resistance :  
VDD

R1

M2

R2
Vout
(A) High pass filter
(B) Band pass filter
Vin M1
(C) Integrator
(D) All pass filter
Q.14 Consider the following circuit shown in
below figure, which one of the following
 gm1  ( R1  R2 )
is a correct statement? (A) AV 
1  gm2  R2
gm1  ( R1  R2 )
(B) AV 
1  gm2  R2
 g m1  ( R1  R2 )
(C) AV 
1  R2
 gm1  ( R1  R2 )
(A) D2 does not conduct for any value (D) AV 
1  gm2
of Vi
Q.16 In the circuit shown in below figure D1
(B) V0  10V , D2 does not conduct for
has 10 times the junction area of D2 .
any value of Vi  10 V
The value of V results is _______ mV.
(C) V0  10V , D2 does not conduct for (Take : VT  25 mV )
any value of Vi  20V
Vi
(D) V0  , D2 does not conduct for
2
any value of Vi  15V
Q.15 Consider the give MOSFET amplifier
circuit shown in figure below. Small
signal voltage gain is given by.
Given :
MOSFET : M1 M2
GATE ACADEMY® Analog Electronics 7.5
Q.17 Given figure (a) shows the Q.19 In the circuit shown below, I is a dc
characteristics of Zener diode as current and vs is a sinusoidal signal.
regulator and figure (b) is the voltage
Capacitors C1 and C 2 are very large:
regulator circuit using the Zener diode of
the same characteristics. The value of their function is to couple the signal to
and from the diode but block the dc
VL  VL(max) VL(min) in volts is
current from flowing into the signal
IZ
0.12 V source or the load (not shown). Use the
0
diode small-signal model. Let
5 mA Rs  1 k . The value of I for which V0
become half of Vs _______ A (Take
: VT  25 mV )
35 mA

Fig. (a)

Fig. (b) Q.20 Consider the network shown below

(A) 0.24 V (B) 0.36 V figure having a ideal diode ‘D’.
(C) 0.12 V (D) 0.48 V D
Q.18 Consider diode circuit shown below. All
the diodes are identical in all respects
Vi RB 5 V0
accept for junction area of D1 , D2 and
D3 are A1 , A2 and A3 respectively
Ii n R Given : Vi  10sgn[sin t ] Volts . The
ID1
ID2
ID 3 value of ' RB ' in ohm’s such that average
Vin D1 D2 D3
output voltage 'V0 ' is 4 volts, is ______.
Q.21 In the following circuit of BJT, a resistor
The expression of I D2 is
of value ‘5k’ is connected across base
Iin Iin and collector junction. The current
(A) (B)
A1 A1
1 
A3 A2
1  common emtetr gain () of transistor is
A2 A3 A2 A1
V0
Iin Iin 100. Then the value of voltage gain
(C) (D) Vi
A2 A2 A1 A3
1  1  is _______. (given VT  25 mV )
A3 A1 A2 A2
 7.6 Paramount 1111 [EE] GATE ACADEMY®
VCC

0.5 mA
5 k
V0
Cin
30 k
Vi
Cin

0.25 k 

For VI  2.5V the output V0 is ______.

(correct upto two decimal places)
Q.22 An Op-Amp slew Rate  0.5 V/μsec
Q.25 Consider the circuit shown below, if
has a gain of 20 dB. If this amplifier has both the MOS transistor are identical
to faithfully amplify signal at 20 kHz,
W 
without introducing any slew Rate with nCox  30 A/V2 ,   2
 L MT1 , MT2
induced distortion, then the input signal
and thersold voltage of both MOS
level must not exceed ______ mV.
transistor VT  1V . The value of
Q.23 Consider the circuit shown in figure
having ideal diodes. I 0 (in A) is _______. (correct upto
two decimal places)

From the transfer characteristics of the

given circuit, following data is obtained,
Vin V0 Q.26 The Op-Amp circuit along with its input
voltage 'Vi ' is shown below. If the
– 2.5 V V1
output gets saturated at time t  150sec,
+ 1.5 V V2
the value of capacitor ‘C’ (in mF) is
The value of V1  V2 (in V) is _______. ________. (correct upto two decimal
Q.24 NMOS and PMOS transistors in the places)
circuit shown are matched with
W  W 
nCox     pCox    1 mA/V2
 L n  L p
V0
Vt  1 V & I D  mA
10
GATE ACADEMY® Analog Electronics 7.7

Q.27 The value of V0 for the given Op-Amp Q.30 A diode circuit and waveform of its
circuit is ________. applied input are shown below,
1k

15 V
1k
2V
V0

15 V

1k
2k

(A) 6 V (B) 8 V
(C) 10 V (D) 15 V
Q.28 Consider the oscillator circuit shown in
figure below, if the Op-Amp is ideal,
If diode D is ideal, then the sum of
then the value of ratio ( R2 /R1 ) is
maximum and minimum output voltages
_______. (correct upto two decimal
in steady state is _______ V. (correct
places)
upto two decimal places)
Q.31 The transistor in the circuit shown
below, is specified to have  in the
range 50 to 100. What is value of RB
that results in saturation with an
overdrive factor of at least 10?
+ 10 V

1 k
Q.29 In the circuit shown below, the diode
RB
used is an ideal diode. The average value
+5 V
of current I (in amperes) delivered to the
network ‘N’ is _______. (correct upto
two decimal places)
 7.8 Paramount 1111 [EE] GATE ACADEMY®
(A) 22 k (B) 11 k value and 10 m sec time period. If
(C) 2.2 k (D) 1.1 k Vb  2.5 V , the average value (in volts)
Q.32 Consider voltage regulator circuit shown of output voltage V0 (t ) is _______.
below (rounded upto two decimal places)
+ R +

V s (t ) Vs (t )
Vb
– –
Zener used has the breakdown voltage, Q.35 In the circuit shown below the zener
Vz  5V , rz  0 kΩ and it is known that diode has a breakdown voltage of 15
ratio of power rating to the minimum Volts. The value of current I (in mA) at
power dissipation across Zener diode is t  1sec will be _______ (Rounded off
1.4. to 2 decimal places).
If RL is varied from 10kΩ to ' Rmax ' 1k

kΩ, then the value of Rmax to maintain I

the voltage regulation is 20[1  e t ] +

– D 1k
(A) 15kΩ (B) 20 kΩ
(C) 100kΩ (D) 50 kΩ
Q.36 Consider the Op-Amp circuit shown
Q.33 In the circuit shown below, the diode is
below with open-loop gain is 10
ideal and all the capacitors are initially
otherwise Op-Amp is ideal.
uncharged. A voltage Vin (t ) is applied as
10
input to the circuit for t  0 . The voltage
Vin (t ) is a periodic square wave of time 10 
2V
10
period 2 sec and having amplitude of 4 10 
AOL  10 V0
volts peak to peak. The value of voltage 2V I0
Vc (t ) (in volts) at t  1.99sec is 10
10 
_______. (correct upto two decimal
places)
1V

The value of current I 0 (in mA)

_______. (in integer only)
Q.37 The Op-Amp shown in the circuit below
is an ideal Op-Amp and is having a slew
Q.34 In the clipping circuit shown below, the 1
rate of V/sec . The input signal Vi
diode is ideal and Vs (t ) is a triangular 6
wave with 10 V peak value, zero average varies by 0.4 Volts in 12 sec . If the
GATE ACADEMY® Analog Electronics 7.9

value of open loop gain ( AOL ) is 10 and 3 V

the value of resistor R1  5  , then the

12 k
value of feedback resistor RF ,

I D1 D2
–

– 15 V 6 k
(A) 35  (B) 40 
(C) 45  (D) 50 
Q.38 The effect of current shunt feedback in 3 V
an amplifier (A) The value of output voltage
(A) Increases the input and output
V  1V
impedances
(B) Increases the input impedance and (B) The value of output voltage V  3V
decreases the output impedance
(C) The value of current through
(C) Decreases the input impedance and
increases the output impedance I D1  0A
(D) Decreases the input output (D) The value of current through
impedances
I D2  0.33A
Q.39 The transistor shown in circuit below
has very high value of . The zener Q.41 A Zener diode specified to have
diode has a breakdown voltage of 3 VZ  6.8 V at the test current
Volts. If the value of VBE  0.7 Volts,
I Z  5 mA incremental (dynamic)
then the collector current IC (in mA) is
resistance rZ  20  and knee current
________.
I Z  0.2 mA, is connected in the circuit
shown below. The supply voltage
Vs  10 V, the value of voltage ‘ VL ’ (in
V) for RL  2k is ________.
Vs  10 V

Rs  0.5 k

Q.40 Assuming that the diodes in the circuits VL

of figure are ideal, which of the VZ  6.8 V
RL
following option(s) is/are correct.
[MSQ]
 7.10 Paramount 1111 [EE] GATE ACADEMY®

Q.42 In the circuit shown below, all the transistor are identical, VBE  0.6 V and   90 . The value of
ICN is _______ mA. (correct upto two decimal places)
Assume : N  9

Q.43 Find V0 for the given ideal Op-Amp signal resistances rd 1 and rd 2 . The value
circuit v0
1k of for I  500 A is ________.
vi
15 V
1k V
2V
V0
V
15 V

2k
1k

(A) 6 V (B) – 6 V
(C)  15V (D) 10 V
Q.44 The open-loop low-frequency gain of an Q.46 For the circuit shown in the below figure
amplifier is AOL  106 and the Op-Amp has a differential gain AV  10
bandwidth of operation is 8 Hz. If the then, the value of Vout is
bandwidth of the system is extended to
Vin +
250 kHz by applying feedback, then the AV Vout
maximum allowed gain that the –
amplifier can have is ______ (dB). 1k
Q.45 In the capacitor-coupled attenuator
circuit shown in figure, I is a dc current
that varies from 0 mA to 1 mA, and C1
1k 1mA
and C 2 are large coupling capacitors.
For very small input signals, so that the
diodes can be represented by their small-
GATE ACADEMY® Analog Electronics 7.11

5 12 V
(A) Vout  (2Vin  1)
6 5 sec
2
(B) Vout  Vin Vi
0V
5
7 Fig. (a)
(C) Vout  (3Vin  8) 8k
5
6 D
(D) Vout  Vin  2
8 Vi 30 k 1000 pF V0
Q.47 Consider the Schmitt trigger circuit
shown below,
+15 V
20 Fig. (b)
Vin
Vout (A) V0

5 5.18 V
– 15 V

R t (μsec)
0 5
(B) V0
5.18 V
If the Hysteresis width is 26 V, then
value of resistance R (in  ) is
_______. (correct upto one decimal
t (μsec)
place) 0 5
Q.48 Consider the circuit shown in figure. If (C) V0
the closed loop gain of the circuit is 0.75 5.18 V
then the open loop gain AOL will be
______.
t (μsec)
0 5
(D) V0

2.18 V
t (μsec)
Q.49 Vi is a pulse of 12 V & duration 5μs as 0 5
Q.50 For the transistor given in the circuit
shown in the figure (a) is applied to the
below VBE  0.6 V ,   120 and
circuit shown in the figure (b). Assume
that the initial voltage on 0 volt is VBC  0 V . Then the value of load
waveform for V0 will be : resistance ‘ RL ’ will be
 7.12 Paramount 1111 [EE] GATE ACADEMY®
15V VCC  12 V

+ 8kΩ R1 50 k RC 5 k
5.6V
VC
+

V0
20 kΩ R2 10 k
RL
RE 1 k
V s (t )

(A) 12.43 k (B) 13.43k

(A) 1.2 + 0.76 sinωt V
(C) 4.69k (D) 8.8k
(B) 1.2 – 0.76 sinωt V
Q.51 In the circuit of figure shown below, an
(C) 6 – 3.74 sinωt V
input signal Vs (t )  1.0sin t V is
(D) 6 + 3.74 sinωt V
coupled to the BJT that has   100
and VBE  0.7V. Assume VT  0.025V,
the voltage measured between collector
terminal and ground, is
Q.52 Consider CE amplifier shown in below figure. Assume   50 and r  2kΩ .

V0
The value of mid-band voltage gain is _______. (rounded opto one decimal places)
Vs
Q.53 Consider the Wien bridge oscillator shown in figure below. To produce sustained oscillation, the
R
value of 2 must be equal to ________ (rounded off upto 2 decimal places)
R1
GATE ACADEMY® Analog Electronics 7.13

4k 5 F Q.55 The current I shown in figure, in mA, is

close to
2k
+
V0
– 15V
10 F 2k 1 k
–
R2
I
+ +
10 V
–
R1 15 V

(A) 8.33 (B) 10

Q.54 In the high pass filter shown in the (C) 9.99 (D) 15
figure, for a cut-off frequency of 1.5
kHz, the value of C (in F ) is _______.

Q.56 Consider the circuit shown in below figure, the cut-in voltage of each diode are 0.7 V, otherwise
all diode are ideal. The plot of I D2 versus VI over the range 0  VI  12 V , for VB  9 V.
12 V

I  100 mA
D1 D2
VI
I D2
VB  9 V

(A) I D2 (mA) (B) I D2 (mA)

100 100

VI (V) VI (V)
9V
 7.14 Paramount 1111 [EE] GATE ACADEMY®
(C) I D2 (mA) (D) I D2 (mA)

100
100

VI (V) VI (V)
–9V 4V

Q.57 Consider the circuit shown in below figure, cut-in voltage of diode is V  0.7V, otherwise diode
is ideal. The plot of output voltage V0 versus I over the range 0  I  2 mA of the circuit is

I R1  1k V0
+
1V
–
–

(A) V0 (V) (B) V0 (V)

1.7 1.7

I (mA) I (mA)
0 1.7 0 0.7

(C) V0 (V) (D) V0 (V)

0.7 1

I (mA) I (mA)
0 1.7 0 1

Q.58 Consider the ideal Op-Amp circuit (A) The value of capacitor voltage at 4
shown below for t  0 [MSQ] sec is 5.187 V.
(B) Current through 4  resistor is fixed
to 1 ampear.
(C) The value of capacitor voltage at 4
sec is 2 V.
(D) The value of capacitor voltage at
steady state is 6 V.
If the capacitor is initially uncharged,
then which of the following option(s) Q.59 Consider a RC phase shift oscillator as
is/are correct. shown in below figure.
GATE ACADEMY® Analog Electronics 7.15

The minimum value of R f (in k ) the circuit below to generate oscillation is ________.
(rounded upto two decmal places)
V 
Q.60 As shown in figure, with ideal Op-Amp. The overall system gain approximately  0  :
 Vs 
10 k
R

1k ± 10%
Vs –
R
–
+ V0
+

(A) 10  10% (B) 10 10% (C) 10 1% (D) 5 2%

Q.61 Consider the circuit shown in below figure. (both diodes D1 and D2 are ideal)

The transfer characteristics of the circuit is,

(A) (B)
 7.16 Paramount 1111 [EE] GATE ACADEMY®
(C) (D)

Q.62 Consider the circuit shown in below figure, assume diode is ideal ( V  0 ). The output waveform

of the circuit is

vi

25 +
D1 D2
T + 10 k 20 k
0 t
T Vi V0
– + +
2 2.5 V 10 V
– 25 – – –

(A) v0 (B) v0
25 25

10 10
0 t 0 t
T T T T
2 2

(C) v0 (D) v0
25 25

0 t 0 t
T T T T
2 2

Q.63 Consider the circuit shown in below figure, the cut-in voltage of diode V  0.7 V, breakdown

voltage of Zener diode VZ1  2.3 V and VZ 2  5.6 V are respectively, otherwise all diode are

ideal. The transfer characteristic of the circuit is when 10 V  Vi  10 V.

GATE ACADEMY® Analog Electronics 7.17
0.5 k
Vi V0

D1 D2

VZ 1 VZ 2

1 k 2k

V0 V0
(A) (B)

0.66 0.66
3 3

– 6.3 – 5.7
Vi Vi
3 2.5

– 6.3 – 6.3

0.8 0.8
V0 V0
(C) (D)

0.8 0.8
3 3

– 6.3 6.3
Vi Vi
3 –3

– 6.3 – 6.3

0.66 0.66

Q.64 For the given circuit configuration both of the zener diode operates in break down region and
used operational amplifier is ideal in nature.The output voltage V0 (in volts) is ______.
10 k 
V0

2 k 5 k
+15V
V0
5V +

5V
 7.18 Paramount 1111 [EE] GATE ACADEMY®

Q.65 In the figure shown below the diode and Op-Amps are ideal. For an input Vin  sin t output
voltage Vout is

(A) Full wave rectified with a peak value 1V .

(B) Full wave rectified with a peak value 1V .
(C) Half wave rectifier with a peak value 1V .
(D) Half wave rectifier with a peak value 1V .
Q.66 A cascaded connection of three current amplifiers A1 , A2 and A3 , whose gains are 50, 5 and 16
respectively, along with practical current source are shown in figure. If input and output
resistances of each stage is 40 respectively, then magnitude of I 0 (in ampere) is________.
(correct upto two decimal places)

Q.67 The circuit shown below consists of an initially uncharged capacitor. The diodes used in the
circuit are ideal diodes and the zener diode has a breakdown voltage of 12 V. The value of
capacitor voltage Vc (t ) (in V) at t  1.4sec is _______.

Q.68 In the circuit shown in below figure, all diodes are ideal, the plot of I1 versus input voltage (Vi ),
when Vi varies from 10 V  Vi  10 V is
VZ = 3 V
10 k
Vi V0
I1
D 10 k
GATE ACADEMY® Analog Electronics 7.19
I1 (mA)

0.65
0.23
(A) – 10 –5
Vi (V)
3 5 10

–5

– 10

I1 (mA)

0.35
(B) 0.1
– 10 – 5
Vi (V)
3 5 10
– 0.5
–1

I1 (mA)

0.7
(C) 0.4
– 10 – 5
Vi (V)
3 5 10
– 0.5
–1

I1 (mA)

0.8
(D) 0.3
– 10 – 5
Vi (V)
3 4 10
– 0.5
–1
 7.20 Paramount 1111 [EE] GATE ACADEMY®

Q.69 Consider the circuit shown below consisting of matched transistors with   100 & VBE  0.7 V
and an ideal Op-Amp. The value of V0 (in V) is ______.
8V

1 k
5 k 2 k +15 V

V0
10 V
+ 
Q1 Q2 2 k –15 V

18 k
6k

Q.70 The small signal model of a MOSFET shown in figure I is equivalently transformed into another
model shown in figure II. The notations have usual meaning. The value of  is
D
G ig  0 id
id D
+
gmV gs

Vgs gmV gs G ig  0

+
– V gs 
S –

S
Fig.I Fig.II
(A) gm1 (B) 2gm1 (C) 2 gm (D) gm
Q.71 The straight line approximated frequency magnitude response of an amplifier circuit shown in
figure I, is shown in figure II

Fig.I Fig.II
The transistor has gm  5mA/V. Ignore channel length modulation effects. Then, in close
approximation
(A) G  10, f1  10, f 2  100 (B) G  31.3, f1  10, f 2  100
(C) G  10, f1  62.8, f 2  628 (D) G  31.3, f1  62.8, f 2  628
GATE ACADEMY® Analog Electronics 7.21
Q.72 An ideal Op-Amp is used in an inverting amplifier configuration as shown below. Note that
VPOS  VNEG in the circuit.
R2  10 k

15 V
R1  1 k
Vin –

Ii Vout
+

R3  10 k
10V

The range of Vin in which the amplifier exhibits the linear operation, is
(A) 1V  Vin  1.5V (B) 1.5V  Vin  1V
(C) 1V  Vin  1V (D) 1.5V  Vin  1.5V
Q.73 Assume linear operation of Op-Amp in the circuit shown below. The circuit stays in steady state
with the switch S closed. When switch S is opened at t  0 , the voltage across capacitor, Vc (t)
for t  0 will be

(A) 4  6e6.25t (B) 6  4e6.25t (C) 4 (1  e3.125t ) (D) 6 (1  e3.125t )

Q.74 Which of the following option(s) is/are correct for given below circuit [MSQ]
27 k

12 V
15 k
 27 k

 
v0


0.033  F 51 k
 7.22 Paramount 1111 [EE] GATE ACADEMY®
(A) it is a type of as astable multivibrator
(B) it is a type of as monostable multivibrator
(C) Output frequency is zero hertz
(D) In steady state output voltage rest at zero volt
Q.75 The voltage transfer characteristic for the circuit shown below, is

15 V

(A) V0 (B)
V0
1 1
1 Vi 1 Vi
5 V 5 V

(C) V0 (D) V0

1 1
5 V 5 V
1 Vi 1 V
5 V
i
1 1 VL
1 1

Answers Analog Electronics

1. – 1.66 2. A, C, D 3. D 4. –2 5. B
6. 7.51 7. 4.98 8. 397.5 9. 8 10. B
11. 4.3 12. 1.35 13. A 14. C 15. A
16. 78.75 17. C 18. D 19. 25 20. 20
21. 83.26 22. 397.88 23. – 0.5 24. 1.04 25. 7.5
26. 2.5 27. D 28. 2.5 29. 1.326 30. 40
31. C 32. D 33. 1.209 34. – 1.14 35. 6.32
36. 20 37. C 38. C 39. 2 40. A, C, D
41. 6.762 42. 3.78 43. B 44. 30.10 45. 0.5
46. A 47. 32.5 48. 3 49. B 50. A
51. C 52. 51.6 53. 4 54. 0.0707 55. A
56. A 57. A 58. A, B, D 59. 2 60. B
61. B 62. A 63. A 64. –5 65. A
66. 0.8 67. 9.85 68. B 69. 15 70. A
71. B 72. B 73. B 74. B, C, D 75. A
GATE ACADEMY® Analog Electronics 7.23

Explanations Analog Electronics

1. – 1.66 2. (A), (C), (D)

Given circuit is shown below figure, Given :

5 V

VS +
V0
1V –

 5V

If Vs  1V; output voltage V0  5V

If Vs  1V; output voltage V0   5V
Vs (volts)

2
1
 2 t (rad)
1. As input applied on inverting terminal
1 2
it’s a type inverting Schmitt trigger.
V0 (volts)
2. As Op-Amp is saturated hence output is
5 always bistable on + 8 V and –10 V.
Vsat  8V
 t (rad)
0 5 13
6 6 6 Vsat  10V
–5
Vin V
Vx  1k  in
2k 2
At   1 ,
V V
2sin 1  1 Vx  0 1k  0
2k 2
 If Vx  Vx then V0  Vsat and Vin  VUTP
1 
6
 5 VUTP Vsat
And 2    1     
6 6 2 2
The average value of output waveform is, VUTP  8 V
1 2
V0Avg   V0 (t )dt If Vx  Vx then V0  Vsat and Vin  VLTP
2 0
VLTP Vsat
4 8 
5  5 2 2
 6 6
2 VLTP  10V
 2  4 VH  VUTP  VLTP  8  (10)  18 V
  5    5 
 6  6 Hence, the correct options are (A), (C) and (D).
10 20
   1.66V 3. (D)
6 6
Hence, the correct answer is – 1.66 V. Given circuit is shown below figure,
 7.24 Paramount 1111 [EE] GATE ACADEMY®
Vi (t ) V0 (t)

2V
t
t
6 ms 12 ms
–4V
–2V
Hence, the correct option is (D).
4. –2
+ +
C
: Method 1 :
Vi (t ) R V0 (t) Question is based on concept of negative
clamper circuit.
– –
Given : Vin  (1  2sin t )
T
Positive half cycle : 0  t 
2
Diode ON shown in below figure,
Vc (t )
+ –
+ +
C

Vi (t ) R V0 (t)

– –
VC (max) across capacitor  Vin(max)  3V
V0 (t )  0 V
Output of a negative clamper is given by,
Vc (t )  2 V
V0  Vin  VC  (1  2sin t )  3
T
Negative half cycle :  t  T  2sin t  2
2
Diode OFF shown in below figure,
Vc (t )
+ –
+ +
C

Vi (t ) R V0 (t)

– –

Applying KVL in the above circuit,

Vin (t )  Vc (t )  V0 (t )  0V
Average value of V0  0  2   2 V
V0 (t )  Vc (t )  Vin (t )
[Average of sin t  0 ]
V0 (t )   2  ( 2)   4V Hence, the correct answer is – 2 V.
GATE ACADEMY® Analog Electronics 7.25

: Method 2 : Hence, VC2  2 V and V02  0 V

By using Superposition Theorem : T 3T
(b) For t  ;
4 4

(i) Consider only DC input, Vi  1V

From figure, VD  Vi  VC  Vi  2
Since, Vi  2
Therefore, VD   ve
Hence, diode is OFF.
From above figure,
VC1  1 V and V01  0 V
(V01 )avg  0 Volt
(ii) Consider only AC input,
Vi  2sin t V
By applying KVL in above figure,
V02  2  Vi  0
V02  Vi  2
V02  2sin t  2

As Vi (max)  2V
Vi (min)  2V
T
(a) For 0  t  ;
4
The average value of V02 is,
(V02 )avg   2 V
The overall output voltage is,
(V0 )avg  (V01 )avg  (V02 )avg  0  2
Diode is ON and the capacitor is (V0 )avg  2 V
charged to maximum value. Hence, the correct answer is – 2 V.
 7.26 Paramount 1111 [EE] GATE ACADEMY®

5. (B) Maximum power dissipated across the Zener

diode is,
Given circuit is shown below figure,
PZ (max)  VZ IZ (max)
5 V 1k
PZ (max)
D2 I Z (max) 
1 mA VZ
D1
– 4
I Z (max)   0.25974 A
+ 15.4
M1 M2 I Z (max)  259.74 mA
Applying KVL, in the above circuit,
Vin  Ii Ri  Vz  0
Vin  Vz
Iin 
From current mirror circuit, Ri
(W /L)2 60 15.4
I M2   I ref Iin   297.33 mA
(W /L)1 150
Iin  I z (min)  I L(max) …(i)
IM2  31mA  3mA
Iin  I z (max)  I L(min) …(ii)
I D2  3I D1  31  3mA
From equation (i),
Diode D2 -ON and Diode D1 -OFF I L(max)  Iin  I z (min)
The power dissipated by the diode D1 and D2 I L(max)  297.33 15
are respectively,
I L(max)  282.33 mA
PD1  I D1 VD1  0  0.7  0mW
From equation (ii),
3
PD2  I D2 VD2  310  0.7  2.1mW I L(min)  Iin  I z (max)
Hence, the correct option is (B). I L(min)  297.33  259.74
6. 7.51 I L(min)  37.59 mA
Circuit shown in below figure, The value of maximum load resistance,
Ri  150  V 15.4
RL(max)  Z 
Ii IL +
I L(min) 37.59 103
IZ
RL(max)  409.68 
Vi  60 V +– VZ RL VL
The value of minimum load resistance,
V 15.4
– RL (min)  Z 
I L (max) 282.33 103
VZ  15.4 V RL(min)  54.55 
IZ (min)  15 mA RL(max) 409.68
The ratio of, 
PZ (max)  4 W RL(min) 54.55
GATE ACADEMY® Analog Electronics 7.27

RL(max)  82  rz 
 7.51 1.5  0.086  
RL(min)  rz 
Hence, the correct answer is 7.51. 17.44 rz  82  rz
7. 4.98 16.441 rz  82
Given : Unregulated supply change by 1.5 V 82
rz 
16.441
rz  4.98 
Hence, the incremental resistance of Zener
diode is 4.98  .
: Method 2 :
When both input and output voltage are variable
: Method 1 : then dynamic Zener diode resistance is given
Apply KVL in the input circuit, by,
VS  82I  I  rz  Vz V  r
V0  in z
Let VS  VS1 , I  I1 RS  rz
1.5  rz
VS1  82I1  I1  rz  Vz …(i) 86 103 
82  rz
Let VS  VS 2 , I  I 2
rz  4.98 
VS2  82I2  I2  rz Vz …(ii) Hence, the incremental resistance of Zener
Apply KVL across output, diode is 4.98  .
V0  I  rz  Vz 8. 397.5
Let V0  V01 , I  I1 Given : VCC  12V
V01  I1  rz Vz …(iii) VCC
VCE   6V ,   49 and VBE  0.7 V
Let V0  V02 , I  I 2 2

V02  I2  rz Vz …(iv)

Subtract (iii) from (iv),
V02 V01  (I2  I1 ) rz
Given, V02 V01  0.086V
0.086
Hence,  I 2  I1 …(v)
rz
Subtract (i) from (ii),
VS2 VS1  82(I2  I1 )  rz (I2  I1 )
82  0.086 rz  0.086 VCE  VCE ( sat ) : Transistor operate in active
VS2  VS1  
rz rz regions.
 7.28 Paramount 1111 [EE] GATE ACADEMY®
Applying KVL through C-E, W 
 
12  ( IC  I B )8R  6  ( IC  I B ) R  0   L 2
I D2
I D1  W 
9 R( IC  I B )  6  
 L 1
R( IC  I B )  0.667 10  I D1
I D2   2I D1  2  2  4 mA
R(1  ) I B  0.667 ( IC  I B ) …(i) 5
Applying KVL through B-E I D3  I D2
12  8R( IC  I B )  I B RB  0.7 W 
I D3  L 3
 R( I C  I B )  0 
I D4  W 
11.3  9R( IC  I B )  I B RB  
 L 4
11.3  9R(1  ) I B  I B RB …(ii) 10  4
I D4   8 mA
From equation (i), (ii), 5
11.3  9  0.667  I B RB Hence, the correct answer is 8 mA.
10. (B)
I B RB  5.297 …(iii)
VD D  1.8 V
From equation (iii) and (i),
I B RB 5.297
 RD 1k
R(1  ) I B 0.667
RB 5.297(1 ) 20k
  2.3 50
R 0.667 IG  0 A W  5
M1   
RB   L  0.18
 397.5 VG S 
R
RS 200 
R
Hence, the value of B  397.5
R
9. 8
Applying KVL in the above circuit,
W  W  VDD  RD I D  VGS  I D RS  0
Given :       5
 L 1  L 3 1.8  1 I D  VGS  0.2 I D  0
W  W  VGS  1.8  1.2 I D …(i)
      10
 L 2  L 4
1 W 
All the transistors are operating in the saturation I D  nCox   (VGS  VTH )2 …(ii)
2 L
region,
1
1 W  I D  100 103
I D  nCox   (VGS  Vth )2 2
2 L
500
W  (1.8 1.2I D  0.5)2
ID  18
L 25
[ VGS and other parameters are constant] I D  (1.3 1.2 I D )2
18
GATE ACADEMY® Analog Electronics 7.29

0.72 I D  (1.3 1.2 I D )2

0.72 I D  1.69 1.44 I D2  3.12 I D
1.44 I D2  3.84 I D 1.69  0
(2.11 mA not possible

I D  this makes VGS  0)
0.556 mA

V0  4.3V
So, I D  0.556 mA
Applying KCL at node V0 ,
Hence, the correct option is (B).
I  I1  I 2
11. 4.3
10  4.3 4.3  0.7
Given : V  0.7V for each diode,   I2
9.5 k 0.5 k
1st we assume D1 and D2 forward biased and 0.6m  7.2m  I 2
D3 is reverse biased equivalent circuit is shown I 2   6.6mA
in the below figure So, I 2 is opposite what we assumed before.
Applying KVL in loop,
 5  0.7  VD 2  5  0
VD 2   0.7 V
VD 2  0.7 V
So, diode D2 remain in reverse biased our
assumption is true.
V0  0.7  5  5.7 V Hence, V0  4.3V
10  5.7 Hence, the correct answer is 4.3 V.
I  0.4526mA
9.5 12. 1.35
From KCL at Node V0 ,
Given : VBE  0.65 V
I  I1  I 2
As  is very high, I B is negligible.
10  5.7 5.7  0.7
  I2
9.5 0.5
 I 2   9.5474mA
i.e. in diode D2 current I 2 flows from n to p,
which is not possible so, our assumption is
wrong.
Now we assume diode D1 and D3 is forward
biased and D2 is reverse biased
 7.30 Paramount 1111 [EE] GATE ACADEMY®
By using voltage divider rule,  1 
10  2  SC1  R
VB   2V  V0 ( s)  V ( s)
2 35  1  1  1 s
 SC SC  R
For transistor Q1 ,  1 2  SC
VB  VBE 2  0.65 1.35 V0 (s)  C1  s 
I E1     1
1k 1k 1k Vs (s)  C2  
 s  1 
I E1  1.35mA  RC 
V0 (s)  C1  s 
Since, base current is zero, T ( s)   1
Vs (s)  C2  
 s  1 
I  I E1  1.35 mA
 RC 
Hence, the correct answer is 1.35 mA.
T (s  0)  0
13. (A)
C1
T (s  )  1 
Consider circuit in transform domain, C2
This circuit passes high frequency signal and
stops low frequency signal, so it is a high pass
filter.
Hence, the correct option is (A).
14. (C)

Applying KCL at non inverting terminal

VNI (s)  VS (s) VNI (s)
 0
1 R
CS
R
VNI (s)  V ( s)
1 s
R Assume Vi  0V then D1 is ON, and consider
SC
Applying KCL at inverting terminal D2 is reverse biased
VI (s) VI (s)  V0 (s) 10 1
 0 V0  Vi  Vi
1 1 10  10 2
SC1 SC2
 1 
 SC1 
VI (s)   V0 (s)
 1  1 
 SC SC 
 1 2 

For an ideal Op-Amp voltage at both the

terminal are same Diode D2 is remain in reverse biased until
VI (s)  VNI (s) V0  10V
GATE ACADEMY® Analog Electronics 7.31

1 Vgs1  Vin  0  Vin

Vi  10
2   R V  Vout
Vi  20V gm2  1 out   R  R  gm1 Vgs1
 R1  R2  1 2
Hence diode D2 get forward biased when
 1  gm2 .R2 
Vi  20 V.  gm1 Vin  Vout  
 R1  R2 
V
Voltage gain AV  out
Vin
 g m1   R1  R2 
AV 
1  g m2  R2
Hence, the correct option is (A).
V0  10V 16. 78.75
Hence, the correct option is (C).
15. (A) I1 10 mA
Small signal equivalent circuit is given by, VD2
+
7 mA VD1
D1
R1 + –
+ VD2 D2
I Vgs2 – +
lg  0
Vg 2 – 0V V
M2
I 2  3 mA
–
I g m2 Vgs2
R2
Vout
gm1 Vgs1
I D1  3 mA  Q1 : FB

Vin M1
I D2  10 m  3 m  7 mA  Q2 : FB
+
Vgs1 I 0  (Junction Area)
–
D1 has 10 times the junction area of D2 .
A1  10 A2
By using voltage divider rule
R1 where, I 0  Reverse saturation current.
Vg2  Vout
R1  R2 I01  A1 and I02  A2
R1 Vout I 01 A1 10 A2
Vsg2  Vs2  Vg2  0     10
R1  R2 I 02 A2 A2
R1 Vout
Vsg2   I01  10I02
R1  R2
By using KVL, V  VD2 VD1
Apply KCL + Ohm’s Law at node A.
V I 
gm2 Vsg2  out  gm1 Vgs1 VD  VT ln  D 
R1  R2  I0 
 7.32 Paramount 1111 [EE] GATE ACADEMY®
Here, multidiode circuit   1. VL (min)  10  5(103 )  4
 ID   10.02 Volts
VD2  VT ln  2 
 I0  VL  VL (max)  VL (min)
 2
 ID  VL  10.14  10.02  0.12 Volts
VD1  VT ln  1 
 I0 
 1 Hence, the correct option is (C).
V  VD2 VD1 18. (D)
 ID   ID  Given circuit consists diodes D1 , D2 and D3
V  VT ln  2   VT ln  1 
 I0   I0 
 2  1 connected in parallel and identical.
 I D I0   VD1  VD2  VD3
V  VT ln  2  1 
 I0 I D  We know, from diode equation.
 2 1 

7 m  I D  I S eV0 / VT
V  25 m ln  10   78.75 mV
3m  I 
 VD  VT ln  D  …(i)
Hence, the value of V results is 78.75 mV.  IS 
17. (C) Saturation current I S in a pn-junction diode is
Given diode characteristics is shown in below given by,
figure, AqDp pno AqDn np0
IZ IS  
0.12 V Lp Ln
0
 I S  A & VD1  VD2  VD3
5 mA
 ID   ID 
So, VT ln  1   VT ln  2 
 IS   IS 
 1  2
35 mA ID IS A
 I D1  2  I S1 & 1  1
From the characteristics of Zener diode, we can I S2 I S2 A2
see that is practical Zener diode A
VZ VZ
Then, I D1  I D2  1  …(ii)
+ – rZ  A2 
 +–
Similarly,
VZ 0.12
rZ   103  4  ID IS A
I Z (35  5) I D3  2  I S3 & 3  3
I S2 I S2 A2
 VL  VZ  I Z rZ
A 
Also from characteristic figure (a) till 5 mA I D3  I D2  3  …(iii)
Zener diode is Reverse biased but is not in  A2 
breakdown. Now by KCL, Iin  I D1  I D2  I D3
So, I Z (min)  5 mA and IZ (max)  35 mA Substituting values from equation (ii) and (iii),
VL (max)  10  35(103 )  4 A A 
Iin  I D2  1   I D2  I D2  3 
 10.14 Volts  A2   A2 
GATE ACADEMY® Analog Electronics 7.33

A A  v0 1

Iin  I D2  1  1  3 
 A2 A2  vs 2
Iin 1 r
I D2   d
A1 A3 2 rd  Rs
1 
A2 A2 rd  Rs  2r2
Hence, the correct option is (D).
rd  Rs
19. 25
VT
 Rs
DC equivalent circuit is given by, I
V
I T
Rs
25 mV
I
1k
I  25 A
Hence, the correct answer is 25 A.
20. 20
Current, I DDC  I Given : Input voltage Vi  10sgn(sin t )
VT Vi  10; sin t  0
rd 
I DDC
Vi  10; sin t  0
As  is not given take   1
The input voltage waveform can be drawn as,
VT V
rd   T
I DDC I
AC equivalent circuit is given by

rd
V0   vs
Rs  rd
It is given that v0 become one-half of vs
 7.34 Paramount 1111 [EE] GATE ACADEMY®
The given diode circuit is, RB  5  25
D
RB  20 
Hence, the correct answer is 20 .
Vi RB 5 V0
21. 83.26
First we will perform ‘DC’ analysis of the
Now, during positive half cycle from circuit. So during ‘DC’ analysis all the capacitor
0  t  1sec . will behave as open circuit.
Diode ‘D’ is ON and RB is shorted
S.C.
V0

10 5

Therefore, V0  10 Volts
During negative half cycle, Vi  10 V . Hence,
diode ‘D’ OFF

I E  IC  I B  0.5 mA
IE
IB   0.0049 mA  4.9 A
 1
IC  I B  0.49 mA
10  5 50 IC
 V0   Now, gm   19.6 mA/V
5  RB 5  RB VT
Vavg (output) VT
r   5.102 k
 T  IB
V0 (positive half cycle)  2  The equivalent AC model of the circuit is
 
 T
 V0 (negative half cycle)  
 2
T
50
10 1  1
5  RB
4
2
50
8  10 
RB  5 Applying KCL at node A
50
2 V0  Vi V
 gmV  0  0 …(i)
RB  5 5 30
GATE ACADEMY® Analog Electronics 7.35
Apply KCL at node P, 23. – 0.5
VP V
  gmV  0 The given circuit can be redrawn as,
0.25 r
Vi  V  V 
   gmV  …(ii)
0.25  r 
 1 
Vi  0.25   19.6 103 V  V
 5.102 10 
3

Vi  0.25103 (0.196 19.6)V  V

Vi  V
Put this in equation (i) we get,
1 1   1
V0     Vi  gm    0
 5 30   5
V0 0.233  Vi (19.6  0.2)  0
State of
V0 (0.233)  Vi 19.4  0 Input Output
diode
V0
Voltage gain   83.26 Vin D1  RB Vin
Vi 2V   1V V0 
2 D2  RB 2
V0
 83.26 4V  Vin  2V
Vi
Vin D1  FB V0  1 V
 1V
V0 2 D2  RB
Hence, the value of voltage gain is 83.26.
Vi Vin  2V
22. 397.88 Vin D1  RB V0  2 V
 2V
Given : S.R.  0.5 V/μsec , Gain  20 dB 2 D2  FB
Vin  4V
20log ACL  20 dB
Transfer characteristics,
ACL (close loop gain)  10
ACL  10
Faithfully amplifying signal from 10 to 20 kHz
So, f m  20 kHz
S.R.
Vm 
2 f m  ACL
0.5 106 5 As slope of transfer characteristics during
Vm  
2 20 10 10 4
3
1
 4  Vin  2 V is
Vm  397.88 mV 2
Hence, the correct answer is 397.88 mV. Vin  2.5Volt
 7.36 Paramount 1111 [EE] GATE ACADEMY®
2.5 VSG  V0  2.5
 V0  V1   1.25V & similarly,
2 For PMOS to be in ON state, VSG  Vt .
V2  0.75 V
V0  2.5  1
Hence, the value of V1  V2 is – 0.5 V.
V0  3.5V  NOT possible as NMOS has
24. 1.04
already in saturation. So PMOS is OFF.
W
nCox
ID  L (2.5  V 1)2
0
2
1
I D  (1.5  V0 )2 …(ii)
2
V
and given I D  0 mA …(iii)
10
For NMOS, VD  2.5 V From equation (ii) and (iii),
V0 1
and VG  2.5 V  (1.5  V0 )2
10 2
As VD  VG  VI  2.5V V0 1
 ((1.5)2  V02  2(1.5)V0 )
So, VDS  VGS 10 2
 VDS  VGS  Vt V0 1
 (2.25  V02  3V0 )
10 2
(As Vt is positive for NMOS)
V0  5(2.25 V02  3V0 )
VD  2.5V
 5V02 16V0 11.25  0

VG  2.5 V
V01  2.156 and V02  1.043
As V0  1.5 , V01 is neglected.
VS  V0
So, NMOS is in saturation, So, V0  1.043V
VGS  2.5  V0 Hence, the correct answer is 1.04 V.
VD  2.5V  Key Point
The condition for NMOS for saturation, NMOS : Linear, VGS  Vt and VDS  VGS  Vt
VDS  VGS  Vt and VGS  Vt Saturation, VGS  Vt and VDS  VGS  Vt
2.5  V0  1 PMOS : Linear, VSG  Vt and VSD  VSG  Vt
V0  1.5V …(i)
Saturation, VSD  Vt and VSD  VSG  Vtp
Now, for PMOS,
VS  V0 Important to note when MOSFET is in
saturation it has already satisfied the first
condition of linearity. If condition for linearity
VG  VI  2.5 V
fails then MOSFET is OFF and in cut-off mode
VD   2.5 V and can be treated as open circuit.
GATE ACADEMY® Analog Electronics 7.37

25. 7.5 By taking MT2 ,

1 W 
I 0  nCox   [V0  1]2
2  L MT2
2
1 1
I 0  30  2  
2 2
30
I0   7.5 A
4
For MT1 , VDS  3  V0 Hence, the value of I 0 is 7.5 A.

VDS  VGS  VT  VGS  VDS  26. 2.5

MT1 is in saturation. (drain is connected to gate)

For MT2 , VDS  V0

VDS  VGS  VT
VGS  V0
MT2 is saturation. (drain is connected to gate)
Current I 0 is same in both transistor,

1 W 
nCox   [3  V0 1]2
2  L MT1
1 W 
 nCox   [V0 1]2
2  L MT2 The above given circuit is integrator using Op-
Amp,
(2 V0 )2  (V0 1)2
1 t
 2  V0  (V0  1) V0   
RC 0
Vi (t )  Vc (0 )

Take positive sign, Vc (0 )  0 V

 2  V0  V0 1 ( Capacitor is initially relaxed)
3 1 t
RC 0
So, V0  V V0   Vi (t ) dt
2
Now, take a negative sign, 1
Vi (t )  t Volt
2  V0  V0  1 2
(equation does not satisfy) As output get saturated at time t  150sec
1 150 1
150C 0 2
3 15 
Finally, V0  V t dt
2
 7.38 Paramount 1111 [EE] GATE ACADEMY®
1 1 28. 2.5
15   150 150
150C 4
150 150
C   2.5 mF
60 60
Hence, the value of capacitor ‘C’ is 2.5 mF.
27. (D)
In the given Op-Amp circuit, both positive and
negative feedback are presents. So, we need to
check which feedback is dominating.
Steps to indentity overall feedback.
Step 1 : Null all the external sources i.e.
The above given circuit is Wien bridge
Vin  0 V (SC) and Iin  0 A (OC)
oscillator for Wien bridge oscillator frequency
Step 2 : Disconnect the output. and gain ( R2 / R1 ) is given by,
Step 3 : Assume small positive output i.e.
1
V0  V . f  …(i)
2 R3 R4C1C2
Step 4 : Find V  and V  at non-inverting
R2 R3 C2
terminal and inverting terminal respectively. and   …(ii)
R1 R4 C1
Step 5 : If V   V  (Positive feedback) and
R2 20k 4μF
V   V  (Negative feedback).  
1k
R1 40k 2μF
R2 1
1k 
15 V   2  2.5
V R1 2
V0  V
V R 
Hence, the value of ratio  2  is 2.5.
15 V  R1 

V
1k V 29. 1.326
2k
Given circuit is as shown below,

2 2
V  V  V and
2 1 3
1 V
V  V 
11 2
Here, V   V  . Hence, positive feedback.
Dominating negative feedback and Vout will be
Given, the diode used is an ideal diode. The
 15 V and virtual ground concept will not be
average current to be delivered to network ‘N’
applicable.
can be obtained by calculating Thevenin’s
So, V0  15 V equivalent across AB using the circuit shown
Hence the correct answer is (D). below
GATE ACADEMY® Analog Electronics 7.39

Applying KVL,
The network in above figure is a balanced
bridge. So, the network becomes as shown Vin  Vc  5  0
below Vc  Vin  5  20  5  25V
Capacitor gets charged by – 25 V during
negative half cycle.
During the positive half cycle, Vin  10 V
Diode is OFF,

12  3
Rth  12 || 3   2.4 
12  3
 The given circuit changes to,

Capacitor try to discharge through 1 M

resistor, so time constant
RC  0.1106 106
RC  0.1 sec
Vavg Vm 1 10 From figure, frequency of input f  1000 Hz ,
I avg    
2.4   2.4 2.4  so time period T  10 3 sec and negative half
 1.326A T
cycle remains for  0.5 103 sec
Hence, the correct answer is 1.326 A. 2
30. 40 T
As RC 
2
Given circuit is a biased clamper circuit.
So discharging of capacitor will not take place.
During negative cycle, Vin  20V, diode D is
By KVL,
forward biased, so output is connected across 5
Vin  Vc  V0  0
V.
V0  5V (Minimum voltage) V0  Vc  Vin  (25)  (10)  25 10

Equivalent circuit is shown in below figure, V0  35V (Maximum)

 7.40 Paramount 1111 [EE] GATE ACADEMY®

32. (D)

Given circuit is shown below,

V0(max) V0(min)  5  35  40V

20  5
Hence, the correct answer is 40 V. Is   1.5mA
10kΩ
31. (C)
Pz (max)
Given : VGEsat  0.2V and VBEsat  0.7V Given that,  1.4
pz (min)
Transistor is in saturation (given),
+ 10 V Vz I zmax
 1.4
I Csat Vz I zmin

1 k I zmax  1.4 I zmin …(i)

Is  I z  IL
RB IB +
+5 V
+
VCEsat  0.2 V I s  I zmin  I Lmax
0.7 V – –
I s  I zmax  I Lmin
Vz 5
I L(max)    0.5mA
VCC  VCE RL(min) 10kΩ
IC 
RC I s  I zmin  I Lmax
10  0.2
ICsat   9.8 mA 1.5  0.5  I zmin
1
5  0.7 I zmin  1mA
RB 
I Bmin
I zmax  1.4 1mA  1.4mA

Overdrive factor, 10  active [From equation (i)]
 forced
min 50 I s  I zmax  I Lmin
 forced   5
10 10 1.5  1.4  I Lmin
IC 9.8 m
I Bmin  set   1.96 mA I Lmin  1.5 1.4  0.1mA
 forced 5
5  0.7 4.3 Now, ( RL )max 
Vz

5
kΩ  50k
RB    2.2 k
I Bmin 1.96 m ( I L )min 0.1
Hence, the correct option is (C). Hence, the correct option is (D).
GATE ACADEMY® Analog Electronics 7.41

33. 1.209 (ii) Circuit at t  0 is shown in figure,

2V 2
(i) Given circuit is shown in figure below

2 V +– 2F 1F Vc ( t)

2 F capacitor comes across the voltage

The waveform for Vin (t ) can be drawn source, so it can be neglected as voltage
as shown below across it is fixed at 2 V.
For 0  t  1 sec ,
  ReqC  2 sec
VC (0 )  VC (0 )  0
VC ()  2V
t t
VC (t )  2  (0  2)e 2  2[1  e 2 ]
V0 ' (t )  2 u (t)
At t  1 sec,
2 1
VC (1 )  2(1  e 2 )  0.786  VC (1 )

0
t(sec) For 1 sec  t  2sec ,
The combination of input voltage
source, diode and 2F capacitor forms a
positive peak detector circuit
 V0 '(t )  2Volts ; t  0
The circuit can be redrawn as shown
below, Transform network for t  1 sec is shown
below,

The above circuit is a source R.C circuit

where u(t ) is the unit step signal
t

 Vc (t )  2(1  e ) V, t  0 2
Applying KVL,
At t  2sec , 2 0.786 1 1
2  2 I ( s)    I ( s)   I ( s)  0
 1 s s s 2s
Vc (t )  2(1  e 2 )  2 1  
 e  4s  3  2  0.786
I ( s)  
 1.264Volts  2s  s
 7.42 Paramount 1111 [EE] GATE ACADEMY®
2.428 Hence, V0 (t )  Vs (t )
I ( s) 
 3
4 s  
 4
0.786 2.428 1
V ( s)   
s  3 s
4 s  
 4
(s  0.75)  0.786  0.606
V ( s) 
s  s  0.75
A B
 
s ( s  0.75)
0.786  0.75  0.606
A  1.594 A1
0.75
0.606
B   0.808
 0.75
1.594 0.808
Vc (s)  
s ( s  0.75) 1
T T
 0.75t ' Average value of Vout  V0 (t )  dt
Vc (t )  1.594  0.808e (where, t '  t 1 )
Therefore, Vc (1.99sec)  1.594  0.808e0.750.99 Area of V0 (t ) over a fundamental Time

 1.209 V Fundamental Time
Hence, the correct answer is 1.209 V. 2.5
Slope  4 
34. – 1.14 t1
Open circuit test t1  0.625 msec
t2  5  0.625  4.375 msec
Area of positive half cycle
1
Ap   5 m 10  25 m
2
Area of negative half cycle
1
Vp  Vs (t ) and VN  Vb AN   5 m  (10)  25 m
2
D : FB; VD  Vp VN  0V Area of output in positive half cycle.
Vs (t )  Vb  0V AX  Ap  A1
Vs (t )  Vb 1
AX  25 m   t2  t1   10  2.5
Diode act as a short circuit. 2
Hence, V0 (t )  Vb  2.5 V 1
AX  25 m   3.75  7.5 m
D : RB : VD  0V 2
Vs (t )  VB  Diode act as open circuit AX  10.9375 m
GATE ACADEMY® Analog Electronics 7.43

Total Area  AX  AN The Zener diode never goes into breakdown

Total Area  10.9375 m  (25m) region.
 14.0625 m I
Vi V
 i
Total Area 1 k  1 k 2 k
Average Value of Vout 
Fundamental Time 20(1  e t )
I mA  10  (1  e t ) mA
14.0625 m 2

10 m  I at t  1 sec  10(1  e1 )  6.32 mA
Voutavg  1.40625 V 1.41 V
Hence, the correct answer is 6.32 mA.
Hence, the correct answer is – 1.41 V.
36. 20
35. 6.32
Concept :
The Zener diode in the given circuit is in reverse
bias condition. Assume that it is not in
breakdown.
1 k V

Vi 1 k

1k Vi
Using voltage division rule, V  Vi  
2k 2
Where, Vi  20 [1 et ]
The waveform of Vi can be drawn as shown
below,
Vi
V1R2  V2 R1
Vx 
20 V R1  R2

t
0
For Zener diode to go into breakdown region.
V  15 V
(2 10)  (110) 20 10 3
Vi V1    V
 15V 10  10 20 2
2
Vi  30 V (2 10)  (10 V0 ) V
V2   1 0
10  10 2
So, Vi must be greater than 30 V for the Zener
V01  A0V Vid
diode to go into breakdown region which is not
at all possible because maximum value of Vi is 3 V 
V01  10  (V1  V2 )  10    1  0 
20 V. 2 2
 7.44 Paramount 1111 [EE] GATE ACADEMY®

 1  V0 
V01  10     5  5V0
 2 
V01  5V0  5 …(i)
Apply KCL + Ohm’s Law node A
V2  V0 V01  V0 V0  0
 
10 10 10
By KCL at inverting terminal,
V2  V01  3 V0
Vx  0 Vx  V0
V0  0
1  V01  3 V0 5 Rf
2
5
5
V0  V01  1 …(ii) Vx  (Vx  V0 )  0
2 Rf
From equation (i), Given : AOL  10
V01  5  5V0 V0
 10
5
V0  5  5 V0  1 Vi  Vx
2 V0  10Vi  10Vx
15V0
6 V0
2 5
12 4 Vi
V0    0.8 V
15 5 10Vi  V0 5  10Vi  V0 
   V0   0
4 10 R f  10 
V01  5  5   1 V
5 5
V0  V0 1  0.8 0.2 10Vi  V0  (10Vi  V0  10V0 )  0
I0  1    20 mA Rf
10 10 10
50 5
The value of current I 0 is 20 mA. 10Vi  Vi  V0  (11V0 )
Rf Rf
37. (C) 50 5
10   5  11 5
Let ACL be the closed loop gain of Op-Amp. Rf Rf

Slew rate, S.R 

dV0 275  50
5
dt Rf
Where 'V0 ' is the output voltage but.
V0  ACL Vi
d dVi
S.R  [ ACL Vi ]  ACL 
dt dt
1 0.4
106  ACL  106
6 12
12 2 225
ACL   5 Rf   45 
6  0.4 0.4 5
Now, AOL  10 Hence, the correct option is (C).
GATE ACADEMY® Analog Electronics 7.45

38. (C) 5V
IC
Current shunt feedback is also called as current
amplifier and it represents current sampling and 2k
shunt mixing. Due to this, it decreases input and
increases output impedances. 3V
Hence, the correct option is (C). IC
KVL
39. 2 3k
Given circuit is as shown below,
– 5V
By KVL,
3  0.7  IC  3K  5  0
IC  3K  7.3
IC  2.433 mA
Now by KVL,
 5  IC  2  VCB  3  0
Also given that  is very high, VCB  2  2.43 2  2.86 V
 So transistor is in saturation as no information is
IC given below,

IB VCE (sat)  0 V
IB  0 A 5  IC  2K  0  IC  3K  5  0
I E  IC 10
IC   2 mA
Assume that the zener diode is not in breakdown 5K
or not connected in circuit. So, the circuit Hence, the correct answer is 2 mA.
becomes as shown below 40. (A), (C), (D)
Assume both the diodes D1 & D2 operates in
FB.

2K
Vx  10   4 Volts
5K
As Vx  3 Volts that is breakdown voltage of
zener diode  zener diode is in breakdown. So,
the circuit becomes as shown below
 7.46 Paramount 1111 [EE] GATE ACADEMY®
30 1 41. 6.762
I1   mA
12K 4
Given : VZ  6.8V at I Z  5 mA & rZ  20 
I1  0.25 mA
N + N +
0  (3)
I D2  IZ
6K VZ
VZ  0
VZ
I D2  0.5 mA BD

I D1  I1  I D2 IZ rZ
– –
I D1  0.25 m  0.5 mA P P

I D1   0.25 mA VZ  VZ0  I2  r2

D1 D2 6.8  VZ0  5 m  20
Assumption :
FB FB VZ0  6.7V (Break Down Voltage)
Take : VD1  0, VD2  0
Now, RL  2kΩ do open circuit test to check
Find : I D1  1.25 mA  0, I D2  0.5mA
conducting state of zener diode.
  VS 10 V
D1  RB D2  FB
RS 0.5 k
Hence, our assumption is wrong.
Now, take D1  RB & D2 : FB VL
+ N
3V RL  2 k
VZ
– P

12 k
2k
0V ID VZ  10  8 V
P
2
2k  0.5k
+
VD D1 N (VZ  8 V)  (VZ0  6.7)
1
ID V
I – N 1

6k Hence, zener Diode operates in BD region.

Equivalent circuit is given by
3 V 10 V

I D1  0 A  I RS 0.5 k
3  (3)
I D2  VL
A
VL
18K
+
1 RL 2k
VZ
I D2  mA 6.7 V
–
0

3
rZ 20 
V  3  I D2 .12K  1V
Hence, the correct options are (A), (C) and (D).
GATE ACADEMY® Analog Electronics 7.47
KCL + Ohm’s law at node-A 710  105 VL
10  VL VL  6.7 VL  0 710
  VL  V  6.762 V
500 20 2000 105
40  4VL  100VL  670  VL Hence, the correct answer is 6.762 V.

42. 3.78
Given : VB  0.6
9  0.6 8.4
I 2k    4.2 mA
2 2

IC
I 2 k  I c  I B  NI B  I C  ( N  1)

   N  1
I2k  Ic  
  
Given circuit is a current mirror,
IC  IC1  IC2  ......  ICN
  
I C  I CN    I 2k
   N  1
I 2k
I CN 
 N 1 
1  
  
 90 
IC    4.2  3.78 mA
 90  9  1 
Hence, the correct answer is 3.78 mA.
Steps to indentity overall feedback.
43. (B)
Step 1 : Null all the external sources i.e.
In the given Op-Amp circuit, both positive and
Vin  0V (SC) and Iin  0 A (OC)
negative feedback are presents. So, we need to
check which feedback is dominating. Step 2 : Disconnect the output.
 7.48 Paramount 1111 [EE] GATE ACADEMY®
Step 3 : Assume small positive output i.e. 106  8  ACL  250kHz
V0  V . ACL  32
 
Step 4 : Find V and V at non-inverting
ACL dB  20log32  30.10dB
terminal and inverting terminal respectively.
Hence, the maximum allowed gain that the
Step 5 : If V   V  (Positive feedback) and
amplifier can have is 30.10 dB.
V   V  (Negative feedback).
1k 45. 0.5

15 V DC equivalent circuit is given by,

1k V
V0  V
V
15 V

V
2k V
1k

1
V   V
3
1
V   V I D1  0.5mA
2
Here, V  V  (Negative feedback)

I D2  1 mA  I D1  1 mA  0.5 mA
Virtual ground concept is applicable.
I D2  0.5 mA
1
Now, V   V   V0 VT 25 mV
3 rd1    50 
I D1 0.5 mA
Apply KCL + Ohm’s law at V  ,
1 1 VT 25 mV
2  V0 V V rd 2    50 
3 3 0 0 I D2 0.5 mA
1k 1k Small signal equivalent circuit is given by,
2 V
2  V0  V0   0
3 3
V0   6 V
Hence, the correct option is (B).
44. 30.10

Given : Open loop gain = 106

Bandwidth = 8 Hz
Closed loop Amplifier bandwidth = 250kHz
We know that,
Gain bandwidth product (GBW) = Constant rd2 50
V0   v1   v1
 (GBW)openloop = (GBW)closedloop rd1  rd 2 50  50
GATE ACADEMY® Analog Electronics 7.49
v0 47. 32.5
 0.5
v1
Hence, the correct answer is 0.5.
46. (A)
Vin
+
Vout
–
1 k

R
1 k 1 mA
V2  Vin and V1   Vout
R5
R
Vid  V1  V2  Vout  Vin
Source Transformation
R5
(1) Vout  15 V and take Vid  0
V1  V2
R
Vin1  .Vout
R5
R 15R
Vin1   (15V) 
R5 R5
(2) Vout  15 V and take Vid  0
Vout  AV Vid
V1  V2
Vout  AV  (V1  V2 )
R
Vin 2  Vout
V1  Vin R5
1 1 R 15R
V2  Vout   (1) Vin 2  (15 V) 
11 1 1 R5 R5
V 1 Here, Vin1  Vin 2
V2  out 
2 2 Vin  VUTP and Vin 2  VLTP
 V 1
Hysteresis width  VUTP  VLTP
Vout  10  Vin  out  
 2 2
15R 15R
Vout  5  (2Vin  Vout  1) 26  
R5 R5
6Vout  10Vin  5 15R 15R 30R
26   
5Vin 5 R5 R5 R5
Vout  
3 6 26R 130  30R
5 4R  130
Vout   (2Vin  1)
6 R  32.5 
Hence, the correct option is (A). Hence, the value of resistance R is 1.66 .
 7.50 Paramount 1111 [EE] GATE ACADEMY®

48. 3 V0 (t )

AOL
Given : Closed loop gain, Af   0.75
1 AOL 5.18
Given circuit is a voltage follower with   1 .
AOL
 0.75
1  AOL 0 5
t

AOL  0.75  0.75 AOL Hence, the correct opiton is (B).

50. (A)
0.25 AOL  0.75
Let’s check operating condition of BJT. Let’s
0.75
 AOL  3 assume it operates in cut-off region
0.25 15 V
15 V
+
Hence, the open loop gain of the given circuit is
+ N 0V 8 k
3. –
5.6 V– BD
49. (B) P
15 V + VB Cut-off
V1
12 V + P
V2 – Vx
N E
– V0
5 sec
20 K RL
0V
Vi
Fig. (a)
8k V2  15  5.6  9.4
D V1  15 V
Vid  V1  V2  15  9.4  5.6 V  0
Vi 30 k 1000 pF V0
Vx  0

BJT : ON
Fig. (b)
At 0  t  5 ,

Active region (CE : 1800 )
V (0)  0 15 V
30 12
V0 ()   9.473 IC 8 k
30  8 + N 9.4
5.6 V– BD –
V0 (t )  9.473  9.473et /  P +
VB C IC
+ Vx
30  8
  RC  103 1000 1012 9.4
– VB +
0.7 V –
I E  0.7 mA
38 Positive V0
  6.315  sec 20 k
feedback
RL
 510 6 /6.31510 6
V0 (t )  9.473(1  e )
V0 (t )  9.473(1 e0.791 )
V0 (t )  9.473  0.546  5.18 V Non-Inverting OP-Amp
00 Phase Shift 0
CE
180 Phase Shift
GATE ACADEMY® Analog Electronics 7.51
Overall negative feedback  VGC is KVL,
applicable. Vth  I B  Rth  0.7  I B (  1)  RE  0
15  9.4 Vth  0.7 2  0.7
IC  IB  
8K Rth  RE (  1) 50
 1(100  1)
IC  0.7 mA 6
VB  9.4 V  Vx IB 
1.3
 11.89 A
VE  8.7 V  V0 109.33
IC   I B  1.189mA
V0
RL   12.43 k VCDC  VCC  IC RC  6.05V
IE
Hence, the correct option is (A). 2. AC analysis :
51. (C)
1. DC analysis :

50 5
Vth  Vs  Vs
60 6
50 10 50
Rth   k
10 10 50  10 6
Vth  12  12  2V
10  50 60
50 10 50
Rth  R1 R2   k
50  10 6

Rth

50
k
6
Vth

Vth  ib  Rth  ie  re  ie  RE  0
ie  (  1)  ib
Vth  ib [ Rth  (  1)re  (  1) RE ]
 7.52 Paramount 1111 [EE] GATE ACADEMY®
5 Internal voltage gain of CE amplifier is given
Vs  ib [ Rth  (  1)  (re  RE )]
6 by,
6 V
Vs   ib [ Rth  (  1)  (re  RE )] Av  0   gm RL' [CE without RE ]
5 Vs
Vc   ib  Rc 
Where, gm   25 mA/V
Vc  RC r
 RL'  5 ||10  3.33 k
Vs 6  [ R  (  1)  (r  R )]
5 th e E
AV   25  3.33   83.25
 Rc .5 V V V V
Vc  Vs AVS  0  0  i  AV  i …(i)
6[ Rth  (  1)  (re  RE )] Vs Vi Vs Vs
VT VT From figure, Ri '  11.5 || 41.1|| r
re  
I EDC (  1)  I BDC Ri '  8.98 || 2  1.636 k
25m
re   20.82 
(100  1) 11.89 
100  5k  5  (1.0sin t )
Vc 
 50 
6  k  (100  1)  (20.82  1000)  Vi 1.636
6    0.62 …(ii)
Vs 1  1.636
500  5 103 (1.0sin t )
Vc  From equation (i) and (ii)
6(111.44k )
AVS   83.25  0.62   51.6
Vc   3.7391sin t (V )
V0
Vc  3.74sin t (V ) Mid-band voltage gain =  51.6
Vs
Vctotal  Vc  vc V0
Hence, the value of mid-band voltage gain
Vctotal  6.05  3.74sin t Vs
Hence, the correct option is (C). is 51.6.
52. 51.6 53. 4

Given :   50, r  2 k Redraw the given circuit,

R2
V0
AC Analysis : All the capacitors are short
circuited.
R1
AC equivalent circuit of CE amplifier is shown –
Vf V0
below, +

Vf V0
CA RA
ZA
CB RB
ZB
GATE ACADEMY® Analog Electronics 7.53

RA  4 kΩ , RB  2 kΩ , CA  5μF and R2 1  SCA RA  SCB RB  S 2 RA RBCACB


CB  10μF. R1 SCA RB
1 1  SCA RA R2 SCA RA SCB RB
 
Here, Z A  RA   R1 SCA RB SCA RB
SCA SCA
1 S 2 RA RBCACB 1
RB   
1 SCB RB SCA RB SCA RB
Z B  RB ||  
SCB R  1 1  SCB RB R2 RA CB 1
B
SCB    SRACB 
R1 RB CA SRBCA
To produce sustained oscillation loop gain must Put S  j ,
be equal to unity.
A  1 R2 RA CB  1 
i.e.    j  RA  CB  
R1 RB CA  RBCA 
V0 Vf
where, A  and   Compare real part both the side,
Vf V0
R2 RA CB
Here, apply KCL + Ohm’s law at inverting  
node. R1 RB CA
0  V f V f  V0 R2 4k 10 
    22  4
R1 R2 R1 2k 5 
R2
V0 R
 A  1 2 4
Vf R1 R1

Use voltage divider rule at node, Hence, the correct answer is 4.

ZB 54. 0.0707
Vf  V0
Z A  ZB Given : fcut off  1.5kHz
V ZB
 f  Circuit is shown below,
V0 Z A  Z B
A  1
1
A

R2 Z A  Z B
1 
R1 ZB
R2 Z
1  1 A
R1 ZB
R2 Z A

R1 ZB Cutoff frequency for above circuit is,
R2 1  SCA RA 1  SCB RB 1
  fcutoff 
R1 SCA RB 2 RC
 7.54 Paramount 1111 [EE] GATE ACADEMY®
1
C
2 R fcutoff
100 mA
1
C  0.0707 F
21.5 103 1.5 103 VI
– +
Hence, the value of capacitor is C  0.0707 F . 0.7 I D2

+
55. (A) VB  9 V
–
Let output V0  15 (Saturated)
V   10 V   15
 0
1 2 I D2  0 mA
 
2V  20 V 15  0 I D2 (mA)
3V   5
5
V 
3
5 Vin (V)
10  0 9
I 3  8.33mA
Case 2 :
1
Hence, the correct option is (A). Input voltage VI  9 V diode D1 -OFF, D2 -ON
12 V
56. (A)

Given : Circuit shown in below figure,

12 V 100 mA

+ –
VI
I  100 mA O.C. I D2 0.7 V
D1 D2 +
VI VB  9 V
I D2 –
+
VB  9 V
–
I D2  100 mA
I D2 (mA)
Diode cut in voltage, Vv  0.7
100
Input voltage 0  VI  12 V
Case 1 : Vin (V)
0 9
If input voltage VI  9 V , diode D1 -ON ,
Hence, from case 1, and case the plot can be
D2 -OFF draw,
GATE ACADEMY® Analog Electronics 7.55
I D2 (mA)
+
O.C.
100
I R1  1k V0
+
1V
VI (V) –
0 9 –
Hence, the correct option is (A). V0  IR1
57. (A) Case 2 :
Given : Circuit shown in below figure, When input current I  1.7 mA , diode is ON

I1 ID + +
+
+ 0.7 V
0.7 –
I R1  1k V0 I R1  1k V0
– +
+ 1V
1V –
– – –

Cut in voltage of diode V  0.7 V V0  1.7 V

Input current I; 0  I  2 mA Hence, from case 1 and case 2, the plot is draw
shown below,
Let diode is ON;
V0 (V)
I1 ID +
+ 1.7
0.7
I R1  1k – V0
+ R1
1
– I (mA)
– 0 1.7
1.7 Hence, the correct option is (A).
I1   1.7 mA
1 KΩ 58. (A), (B), (D)
Applying KCL at node A, Given circuit is as shown below for t  0 .
ID  I  I 1
If diode is ON, then I D  0; flow from P –
terminal to n – terminal of diode,
ID  0
I  I1  0
I  I1
 4
I  1.7 mA V0  1    2V  6Volts
 2
If input current I  1.7 mA , then diode is ON (Output of non-inverting ideal Op-Amp)
otherwise diode is OFF. Capacitor start charging through V0 and 2 
Case 1 : resistor with time constant
When, input current I  1.7 mA , diode is OFF.   RC  2 1  2 sec
 7.56 Paramount 1111 [EE] GATE ACADEMY®

Given : Vc (0 )  0 V, (2  sCR)(sCR 1) 1Vf  V0 sCR

Vc (0 )  Vc (0 )  0 V Vf sCR
  2 2 2
(From the property of the capacitor) V0 s C R  3sCR  1
Vc ()  6 V jRC
( j) 
t 1  R C 2  3 jRC
2 2

Vc (t )  Vc ()  Vc (0 )  Vc () e 

1 1

t At ω  or f  ,
Vc (t )  6(1  e ) V , t  0
2 RC 2πRC

At t  4sec ,  j  j 1
β  
4
 RC  3 j 3

Vc (t  4 sec)  6(1  e 2 ) V Condition for oscillation :
 5.187Volts Aβ  1

 Rf
Vc (t  )  6(1  e ) V  6Volts
2
A  1
R1
2
I 1 A (Non-inverting configuration)
2
Hence, the correct options are (A), (B) and (D).  Rf  1
1     1
59. 2  R1  3
Rf  2k
Rfmin  2k
Hence, the correct answer is 2 k .
60. (B)

V0 T
 T  100%
Vs T
Applying KCL at node V1 ,
 10 
V V V T     10
(V1 V0 ) sC  1  1 f  0  1 
R R
T
(2  sCR)V1  Vf  V0 sCR …(i) 100% R T
T R   10k 
SR 
T
     
R
Applying KCL at node Vf , 100% T R T R  R 
R
V f  V1
V f sC  0 T R 1
R 100%   10  2 10%
T T R
Vf (sCR 1)  V1
R R 1
Put value of V1 in equation (i),  10k  2 10%  10 %
10k R
(2  sCR)(1 sCR)Vf  Vf V0sCR Hence, the correct option is (B).
GATE ACADEMY® Analog Electronics 7.57

61. (B)

Case 1 : When Vin  0, [Inverting terminal > Non inverting terminal.]

So, V01  Vsat

Hence, D1  ON, D2  OFF

Current through R is 0 A in 1st stage. Hence, VA  0

Second stage is a non-inverting amplifier. Since, VA  0

Hence, V0  0

Case 2 : When Vin  0, [Inverting terminal < Non inverting terminal]

So that, V01   Vsat

Hence, D1  OFF, D2  ON

 R 
From above figure, VA    Vin  Vin
 R
 R
and V0  1   VA  (2)(Vin )   2Vin
 R
The transfer characteristics is shown below,
 7.58 Paramount 1111 [EE] GATE ACADEMY®

Hence, the correct option is (B).

62. (A)

Given circuit shown in below figure,

Vi (V)
D1 D2

25 +

T/2 T + 10 k 20 k
t(sec) Vi V0
– + +
2.5 V 10 V
– 25 – –
–

T
Case 1 : During positive half cycle, 0  t  ; both diode D1 and D2 ON, (Given V  0 V )
2

S.C. S.C. +
+ 10 k 20 k
Vi V0
– + +
2.5 V 10 V
– –
–

Applying KVL, in the above circuit.

Vi  V0  0
V0  Vi
V0 (V)

25

t(sec)
0 T/2
T
Case 2 : During negative half cycle, t T
2
GATE ACADEMY® Analog Electronics 7.59

Both diode D1 and D2 are OFF,

O.C. O.C. 0 A 0A
+
0A
+
+ 10 k
Vi 20 k 0V
V0
– + –
2.5 V +
– 10 V
– –

Applying KVL, in the above circuit.

10  0  V0  0
V0  10 V
V0 (V)

25

10

t(sec)
0 T/2 T
Hence, from case 1 and case 2, the output wave form can be drawn as shown below,
V0 (V)

25

10
t(sec)
0 T/2 T
Hence, the correct option is (A).
63. (A)
Given : Circuit shown in below figure, and cut-in voltage of diode is V  0.7 V
Break down voltage of Zener diode VZ1  2.3 V and VZ2  5.6 V
Input voltage 10 V  Vi  10 V
0.5 k
Vin V0
–
+
0.7 D1 D2 0.7
+
–
–
+
2.3 VZ1 VZ2 5.6
+
–

1 k 2 k
 7.60 Paramount 1111 [EE] GATE ACADEMY®

Case 1 : 6.3  Vin  3;

D1 and D2 are reversed biased and Zener diode Z1 and Z2 are also reversed biased
0.5 k 0 A 0A 0A
Vin V0
+ 0 V–
0A 0A

O.C. O.C.

O.C. O.C.

1 k 2 k

V0  Vin
Case 2 : Vin  3;
Diode D1 -ON and Zener diode Z1 is breakdown diode D2 -OFF and Zener diode Z 2 is also OFF shown
in below figure.
I 0.5 k 0A 0A
Vin V0
I 0A
+
0.7 O.C.
–

+
2.3 O.C.
–

1 k 2 k

Applying KVL, in the above circuit,

Vin  0.5 KI  0.7  2.3  1 KI  0
V 3
I  in
1.5 K
Output voltage,
V0  Vin  0.5103 I
(V  3)
V0  Vin  0.5 103 in 3
1.5 10
V0  0.666 Vin  1
GATE ACADEMY® Analog Electronics 7.61
Case 3 :
For Vin  6.3 V
Diode D1  OFF and Zener diode is also revers biased diode D2  ON and Zener diode is breakdown,
shown in below figure,
I 0.5 k I
Vin V0
0A I
–
O.C. + 0.7

–
O.C. + 5.6

1 k 2 k

Applying KVL, in the above circuit,

Vin  0.5 KI  6.3  2 KI  0
Vin  6.3
I
2.5 K
(Vin  6.3)
V0  Vin  0.5 K
2.5 K
V0  0.8 Vin  1.26
The transfer characteristic of given circuit is shown below,
V0 (V)

0.66
3
1
– 6.3
Vin (V)
3
– 1.26

– 6.3

0.8

Hence, the correct option is (A).

 7.62 Paramount 1111 [EE] GATE ACADEMY®

64. –5
Let’s assume zener diodes operates in breakdown region.
10 k 
V0

2 k I 5 k
+15V
Iz VN
+ V0
5V +

VP

5V +

Vp  5V By virtual ground concept.

Vp  VN  5V
Vx  5  5  10V
15  Vx 15 10 5
Current, I     2.5mA
2 2 2
Apply KVL + Ohm’s law at node VN
Vx  VN VN  V0

5 10
10  5 5  V0

5 10
10  5  V0
V0  5V
Applying KCL + Ohm’s Law at node Vx
Vx  VN
I  Iz 
5
15  Vx 10  5
 Iz 
2 5
15 10 5
 Iz 
2 5
I z  2.5  1mA
I z  1.5mA >0
Zener Diode operates in break down region.
Hence, our assumption is correct and output voltage V0   5V .
GATE ACADEMY® Analog Electronics 7.63

65. (A)

Given : Diode and are Op-Amps are ideal and Vin  sin t
For positive half cycle Diode D OFF,

V0  Vin
V0  sin t
For negative half cycle D ON,

R
For A1 , V '  Vin  Vin [Inverting amplifier]
R
For A2 , V0  V '
V0   sin t
Peak value (Vm )  1V

Hence, the correct option is (A).

 7.64 Paramount 1111 [EE] GATE ACADEMY®

66. 0.8

Given figure is shown below,

Current amplifier block can be represented in two-port network form as follows,

So, circuit can be modelled as,

By using current division,

20  40
I1   10 mA
40  40
Ri  R0  40  (for all amplifier)
Using current division rule,
 40 
I 2   A1I1   
 40  40 
1
I 2  50 10   250 mA
2
40
I3   A2 I 2   625 mA
40  40
 40 
I 4  I 0   A3 I3   
 40  460 
40
I 4  I0  16  625  mA  800 mA
500
So, I0  0.8 A
Hence, the correct answer is 0.8 A.
GATE ACADEMY® Analog Electronics 7.65

67. 9.85
Given circuit is shown below,

Since the capacitor is initially unchanged, the zener diode will not be in breakdown initially. So, the
circuit looks as shown below,

Figure represents a positive peak detector circuit. So voltage across the capacitor will be the peak value
of 10sint


 At t  sec or 1.57sec , Vc (t )  10 V
2
 At t  1.4sec , let us assume Zener diode is OFF.
So, Vc (t )  10sin t  10sin1.4  9.85 V
Here, Vz  12 V so zener never come in breakdown.
 Vc (t ) t 1.4 sec  9.85 V
Hence, the correct answer is 9.85 V.
68. (B)
O.C test :
–
10 k + VZ 0V
Vi V0
VN VP2 VN1 –
Ii 2

VD +
+
VP1 0 V 10 k
–
0V
0V
 7.66 Paramount 1111 [EE] GATE ACADEMY®
VZ  VP2 VN2  0 Vi
VZ  Vi , VD  VP1 VN1  0 V
So, during positive half cycle i.e. for 0  Vi  10  zener diode may enter into breakdown  Given
VZ0  3 V
(1) 0  Vi  3 V , DZ : OFF and D  OFF
Hence, current I  0 A
(2) 3  Vi  10 V , D2 : BD and D : RB
Ii
Vi – V0
10 k +
3V
OC
10 k

Vi  3
I
10K  10K
Vi  3 V  I  0A
10  3
Vi  10 V  I   0.35 mA
20K
During negative half cycle. i.e. 10  Vi  0 V zener
0Vdiode operates in FB & PN junction diode also
operates in FB.
Ii SC
Vi V0
10 k D2
SC
10 k

Vi
I  Vi  0 V  I  0
10K
Vi  10 V  I  1 mA
I (mA)

0.35
10
V (volts)
3 10

1
Hence, the correct option is (B).
GATE ACADEMY® Analog Electronics 7.67

69. 15
8V

1 k
5 k I0 I C' 2 k 0A +15 V
Vx 
IC IC V0
10 V
+ 2IB 
Q1 Q2 2 k –15 V
IB
1
IB 2
18 k
6k

I B1  I B2  I B , I0  IC  2I B
I
IB  C

10  0.7
I0   1.86 mA
5
2I
I 0  IC  C

  
Ic  I0    1.823 mA
  2 
Ic  Ic '
Vx  8  11.823  6.176 V
 Rf   18 
Op-Amp, V0  1   Vx  1  6  6.176
 R   
V0  24.7 V
Here, V0  Vsat (Op-Amp is in saturation)
Hence, V0  Vsat
V0  15 V
Hence, the value of V0 is 15 V.
70. (A)

Fig.I Fig. II
 7.68 Paramount 1111 [EE] GATE ACADEMY®
Vgs  ()  ( gmVgs )
1
  gm1
gm
Hence, the correct option is (A).
71. (B)

For f  f 2 , both the capacitors C1 & C2 act as short circuit & gain G is constant. The equivalent circuit
is given by

The given above circuit is a common source amplifier without Rs .

4.7 106 4.7 1000

Vg  V  Vi
100 10  4.7 10
3 6 i
100  4.7 1000
 Vg  0.98Vi
V0  gm Vgs  (RC RL )
Vgs  Vg Vs  0.97 Vi  0  0.98 Vi
V0   gm  ( RC RL )  0.97 Vi
V0
 5  (15 15)  0.98
Vi
V0
 5  7.5  0.98  36.75
Vi
V0
Now,  20log10 36.75  31.3 dB
Vi dB

Now, we have to find f1 & f 2 due to C1  3.3 nF & C2  53 nF

GATE ACADEMY® Analog Electronics 7.69

(1) Due to C1 , Ceq  3.3 nF

Req  R1  RG  100 103  4.7 106  4.8 M
1 1
f1  
2Ceq Req 2 3.3 109  4.8 106
f1  10 Hz
(2) Due to C 2 , Ceq  53 nF & Req  RC  RL
1 1
f2  
2Ceq Req 2 53 109  30 103
f2  100 Hz
Hence, the correct option is (B).
72. (B)
R2  10 k

15 V
R1  1 k
Vin –

Ii Vout
+

R3  10 k
10V

For linear operation : 10 V  Vout  15 V

R 10
Vout   F .Vin   .Vin  10.Vin
R1 1
10 V  10.Vin  15 V
1 V  Vin  1.5 V
1.5 V  Vin  1 V
Hence, the correct option is (B).
 7.70 Paramount 1111 [EE] GATE ACADEMY®

73. (B)
When switch S is open,

0  2 2  V0

20 k 40 k
V0  6 V
VC ()  6 V
When switch S is closed,

Time constant = RC
VN  2 V
V0  VN  2 V
VC (t )  VC ()  VC (0)  VC ()  et / 
  RC
1
  40K  4 F  sec
6.25
1
t /
VC (t )  6  (2  6)  e 6.25

VC (t )  6  4.e6.25t (V)
Hence, the correct option is (B).
74. (B), (C), (D)

Assuming t  0  Op-Amp is at +12 V and capacitor is zero volt, hence appropriate graph will be
GATE ACADEMY® Analog Electronics 7.71
Vc  V
4.28 V
t

V0 (t) 12 V

t
Because input voltage are +12 V and zero volt
Hence, the correct options are (B), (C) & (D).
75. (A)
Open circuit test to find Vid  V1  V2

V1

V2

15  R  3R Vi 3 15
V2   Vi 
R  3R 4 4
V1  0 V  V2  0
3 15 3V 15
Vid  V1  V2  0  Vi    i 
4 4 4 4
Case 1 : Vid  0, Op-Amp output Vx  0  D1 : ON and D2 : OFF
Vid  0
3Vi 15
  0
4 4
Vi   5

OC

SC
 7.72 Paramount 1111 [EE] GATE ACADEMY®
Use KCL and Ohm’s law at node A,
15  0 Vi  0 0  V0
 
3R R R
5  Vi  V0
V0  Vi  5
Vi   5 V
V0  Vi  5
Case 2 : Vid  0, Vx  0  D1 : OFF and D2 : ON
Vid  0  Vi   5 V

SC

OC

Vi   5V  V0  0 V
Transister characteristic,
V0
1
1 Vi
5 V

Hence, the correct option is (A).

