Paramount

1111
Digital Electronics

Unique Collection of Questions with

Detailed Solutions
 PREFACE

It is our pleasure, that we insist on presenting “Paramount 1111” authored for

Electrical Engineering to all of the aspirants and career seekers. The prime
objective of this book is to respond to tremendous amount of ever growing
demand for error free, flawless and succinct but conceptually empowered
solutions to all the questions.
This book serves to the best supplement for GATE 2023 (EE).
Simultaneously having its salient features the book comprises :
 Step by step solution to all questions.
 Complete analysis of questions through concept wise.
 Solutions are presented in simple and easily understandable language.
The authors do not sense any deficit in believing that this title will in many aspects, be different
from the similar titles within the search of student.
In particular, we wish to thank GATE ACADEMY expert team members for their hard work
and consistency while designing the script.
The final manuscript has been prepared with utmost care. However, going a line that, there
is always room for improvement in anything done, we would welcome and greatly appreciate the
suggestions and corrections for further improvement.

Umesh Dhande
Vice President - Academics GATE & ESE
(UNACADEMY)
 8 Digital Electronics

Questions
Q.1 Given Boolean function F  A  B C  D in SOP form is [MSQ]
(A) M (1,3,5,7,9,10,13,15) (B)  m(0,2,5,7,13,8,9,15)
(C) M (1,2,4,7,8,11,13,14) (D)  m(0,3,5,6,9,10,12,15)

Q.2 Consider the following circuit shown in below figure,

The above circuit represents,

(A) Half subtractor (B) Half adder (C) Full Subtractor (D) Full adder
Q.3 If AB  CD  0, which of the following Boolean expression is INCORRECT,

(A) AB  C ( A  D)  AB  BD  BD  ACD

(B) AB  C ( A  D)  B  D  AC

(C) AB  C ( A  D)  B  D  ACD  CD
(D) All are correct
 8.2 Paramount 1111 [EE] GATE ACADEMY®
Q.4 Initially ABC = 000, where X, Y and Z are outputs

0 I0
1
1 I1 4 1 Y1 DA QA X
0 I2 MUX
1
C I3
S1 S 0

A B

C I0
2
C I1 4 1 Y2 DB QB Y
C I2 MUX
2
0 I3
S1 S 0

A B

0 I0
3
1 I1 4 1 Y3 DC QC Z
C I2 MUX
3
0 I3
S1 S 0

A B Clock

The XYZ after 1-clock pulse is

(A) 011 (B) 010 (C) 100 (D) 101
Q.5 Which of the following identities for Ex-OR and Ex-NOR functions are true? [MSQ]
(A) A  B  AB  A  B (B) A B AB  A  B

(C) A  ( A  B)  AB (D) A ( A  B)  AB
Q.6 Consider the following statements [MSQ]
A 4 : 16 decoder can be constructed (with enable input). Which of the following statements is/are
correct?
(A) Using four 2 : 4 decoders (each with an enable input) only
(B) Using five 2 : 4 decoders (each with an enable input) only
(C) Using two 3 : 8 decoders (each with an enable input) only
(D) Using two 3 : 8 decoders (each with an enable input) and an inverter
Q.7 Consider the circuit shown in figure, the switches are in position ‘a’ or ‘b’ depending on the
switch input being ‘0’ or ‘1’, B3 is the MSB and B0 is the LSB.
GATE ACADEMY® Digital Electronics 8.3

If digits input is 1100 then output voltage V0 (in V) (rounded upto two decimal places)
Q.8 In a Full Adder, the time taken to produce sum and carry outputs if propagation delays of the
logic gates are as given below : tEX OR  30ns, t AND  tOR  10ns .
(A) 30ns,40ns (B) 40ns,30ns (C) 60ns,50ns (D) 30ns,20ns
Q.9 For the logic circuits shown in figure, the output is equal to [MSQ]

Which of the following statements is/are correct?

(A) ABC (B) A  B  C (C) AB  BC  A  C (D) AB  BC
Q.10 For the output F to be 1 in the logic circuit shown, the input combination should be [MSQ]

(A) A = 1, B = 1, C = 0 (B) A = 1, B = 0, C = 0
(C) A = 0, B = 1, C = 0 (D) A = 0, B = 0, C = 1
Q.11 Consider the function f ( A, B, C, D)  AB  BC  BD  A(B  A). The number of minterms in
the function f ( A, B, C, D) . (in integer)
 8.4 Paramount 1111 [EE] GATE ACADEMY®
Q.12 If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which
one of the following diagrams implements a half-subtractor? [MSQ]
(A) (B)

(C) (D)

Q.13 For the k-map shown below, the number of prime-implicants and essential prime implicants are

(A) 3 and 2 (B) 4 and 2 (C) 4 and 3 (D) 3 and 3

Q.14 The input Vin varies between 0 V and 6 V for the 2-bit flash type analog to digital converter
shown in figure below,
GATE ACADEMY® Digital Electronics 8.5

The Boolean expression for LSB C0 of the output is,

(A) Y2 (Y1 Y0 ) (B) Y0 (Y2 Y1 ) (C) Y1 (Y2 Y0 ) (D) Y2 (Y1  Y0 )
Q.15 A 4-bit successive approximation type analog-to-digital converter has conversion time of
15 sec . For input voltage of 15 V. The conversion time for 8-bit successive approximation
ADC having same parameter and input voltage of 20 volt?
(A) 255 sec (B) 20 sec (C) 30 sec (D) 15 sec
Q.16 Consider a combinational circuit shown in below figure.

The circuit behaves as

(A) Adder
(B) Subtractor
(C) Adder when V  0 and subtractor when V  1
(D) Adder when V  1 and subtractor when V  0
Q.17 The state diagram which expresses the below FSM is

(A) (B)

01
 8.6 Paramount 1111 [EE] GATE ACADEMY®

(C) (D)

Q.18 Consider the digital circuit shown in figure below,

If the function implemented by the circuit is f ( A, B)  A B, then the gated operation

performed by box ‘X’ is,
(A) AND (B) OR (C) NAND (D) NOR
Q.19 For the function f ( A, B, C, D)  m(2,4,6,10,12) d (0,8,9,13) . Which of the following
statements is/are correct? [MSQ]

(A) The minimized expression is f ( A, B, C, D)  ( A  B  C)D

(B) The minimized expression is f ( A, B, C, D)  ( A  B  C)D

(C) The minimum no. of two input NOR gate required to implement f ( A, B, C, D) is 5

(D) The minimum no. of two input NOR gate required to implement f ( A, B, C, D) is 6

Q.20 The four variable function f is given in terms of min terms as :

f ( A, B, C, D)   m(2,3,8,10,11,12,14,15)
Minimum number of 2-input NAND gate required to implement the function, f is _______.
GATE ACADEMY® Digital Electronics 8.7
Q.21 Consider the counter circuit shown in figure, with all the Flip-Flop in reset condition.

If the circuit works as MOD-5 counter, then the logic gate used is
(A) NAND (B) OR (C) NOR (D) EXNOR
Q.22 The initial contents of right-shift register shown below are 01101110. The contents of the shift
register after 3 clock pulses will be

(A) 0010 0110 (B) 0100 1101 (C) 0011 1000 (D) 0101 0100
Q.23 In the following counter assuming initial state Q3 Q2 Q1 Q0  0000 , the state Q3 Q2 Q1 Q0 after
300 clock cycles is

(A) 0000 (B) 1100 (C) 0011 (D) 1010

Q.24 Consider the circuit shown below :
 8.8 Paramount 1111 [EE] GATE ACADEMY®
If Q is taken as the state of the circuit, then the state diagram of the above circuit can be given
as
(A) (B)

(C) (D) None of the above

Q.25 In a 4-bit weighted resistor DAC, the resistor value corresponding to LSB is 20 k . The resistor
value corresponding to MSB will be
(A) 5 k (B) 4.5 k (C) 2.5 k (D) 1.5 k
Q.26 Consider the sequential circuit given below

If all the flip flop are initially cleared the decimal value of count (Q2Q1Q0 ) after 15th clock pulses
is _______.
Q.27 A full adder is implemented with two half adder and one OR gate. The OR gate is used to drive
the final carry function of full adder. In each half adder Tsum  10ns and Tcarry  5ns and
TOR  10 ns . The minimum time (in ns) required to drive final carry of the full adder after
applying input at t  0 (correct upto one decimal place).
Q.28 For the components in the sequential circuit shown below, t pd is the propagation delay, tsetup is
the setup time and thold is the hold time. The maximum clock frequency (rounded off to the
nearest integer), at which the given circuit can operate reliably, in MHz.
t pd  4 ns

t pd  2 ns Flip flop - 2
Flip flop - 1
T Q
D Q t pd  3ns
t pd  4 ns
tsetup  9 ns
tsetup  8 ns
thold  5 ns
thold  2 ns
GATE ACADEMY® Digital Electronics 8.9
Q.29 The mod value of the counter shown in given figure (in integer)

'1' JC Pre QC '1' JB Pre QB '1' JA Pre QA

Clock

'1' KC QC '1' KB QB '1' KA QA

Q.30 Consider the circuit shown in figure, initially all the flip flops are reset [MSQ]

Which of the following statements is/are correct?

(A) If X  1, Y  1, Output Q  1 (B) If X  0, Y  0, Output Q  1
(C) If X  1, Y  1, Output Q  0 (D) If X  0, Y  0, Output Q  0
Q.31 Consider n-bit weighted resistor type DAC shown below,

Input voltage is logic ‘0’ for 0 V and logic ‘1’ for 15 V. The maximum magnitude of output
voltage of ideal Op-Amp is 29.53125 volts, then value of number of bits ‘n’ (in integer).
Q.32 The initial content of the 4-bit right shift, parallel in parallel out shift register is 1010. Input of
shift register is derived from 2  1 MUX.

The number of clock pulses after which the initial pattern of shift register reappears (in integer).
 8.10 Paramount 1111 [EE] GATE ACADEMY®
Q.33 Consider the connection of two 2  4 decoder as shown in below figure,
0 F1 0
2 to 4 1 2 to 4 F
A decoder 1 decoder 1
2 2
B 3 3
1 2
E E

C
The output of the circuit F will be.
(A) 1 (B) C (C) C (D) 0
Q.34 In the following counter assuming initial state Q3 Q2 Q1 Q0  0000, the state Q3 Q2 Q1 Q0 after
612 clock cycles is

(A) 0000 (B) 1100 (C) 0011 (D) 1010

Q.35 The minimum size of MUX required to implement all the function of ( n  1) variables is N : 1.
Assume a MUX of fixed size 8 : 1 is given. The value of N is
(A) 2n (B) 2n1 (C) 2n 2 (D) 2n3
Q.36 Match List-I (Type of N-bit ADC) with List-II (Characteristics) and select the correct answer
using the codes given below the lists :
List-I List-II
(Type of N-bit ADC) (Characteristics)
A. Flash converter 1. Integrating type
B. Successive approximation 2. Fastest converter
C. Counter ramp 3. Maximum conversion time = N-bits
D. Dual slope 4. Uses a DAC in its feedback path.
Codes :
A B C D
(A) 1 4 3 2
(B) 1 3 4 2
(C) 2 4 3 1
(D) 2 3 4 1
Q.37 Three 2  1 MUX is to be used for generating the output F. With the help of following MUX
tree, which one of the following statement correctly describe the choice of the signals to be
connected to the inputs X1 , X 2 , X 3 and X 4 , so that the output is F ( A, B, C)  m(1,2,4,5).
GATE ACADEMY® Digital Electronics 8.11

(A) C ,1,0, C (B) C, C ,1,0 (C) C,1, C ,0 (D) 0,1, C , C

Q.38 If (101)b  ( D2)16  (467)10 . Then the value of radix ‘b’ is
(A) 13 (B) 14 (C) 18 (D) 16
Q.39 A function f ( A, B, C, D)   m (0,1, 2,5,7,9,12,15) is to be implemented using a 8 1 MUX
shown in figure, which uses A, C and D as select lines. The values of input lines I 0 to I 7 as a
functions of B are respectively,

(A) B, B, B, B, B, 1, 0, B (B) B, 1, B, B, B, B, 0, B
(C) B, 1, B, B, B, B, 0, B (D) B, B, B, B, B, 1, 0, B
Q.40 The full scale output of a digital to analog convertor is 20 mA. If the resolution is to be less than
80 A, then the number of bits required and percentage resolutions are respectively,
(A) 7, 0.39 % (B) 8, 0.39 % (C) 8, 0.49 % (D) 7, 0.49 %
Q.41 For the weighted resistor type DAC shown in figure,
 8.12 Paramount 1111 [EE] GATE ACADEMY®
If the resolution is – 0.2 V then the value of resistance R f is
(A) 320  (B) 340  (C) 250  (D) 270 
1
Q.42 For a dual slope ADC type 3 digit DVM the reference voltage is 100 mV, first integration
2
time is set to 300 ms. If for some input voltage, the de-integration time is 370.2 msec, then the
DVM will indicate
(A) 123.4 mV (B) 199.9 mV (C) 100.0 mV (D) 1.414 mV
Q.43 Consider 4  1 MUX shown below, S1 and S0 are select lines, EN is active low enable input
and I 0 , I1 , I 2 , I3 are data input

The expression at Y ( A, B, C) is (Assume ' A ' as MSB)

(A) AB  ABC (B) AC  BC (C) AB  BC (D) AB  AC
Q.44 Reference voltage to a 4 bit dual slope ADC 10 V. Number of clock pulses utilized for
conversion of 6.25 V (in integer).
Q.45 For the following R-2 R ladder type DAC output of ideal Op-Amp in is (R  10k )

(A) 9.9V (B) 4.95V (C) 13V (D) 6.51V

GATE ACADEMY® Digital Electronics 8.13
Q.46 A certain 8-bit DAC has a full-scale output of 2 mA and full-scale error of  0.5% .
What is the range of possible outputs for an input 10001010?
(A) 997 to 1014 A (B) 990 to 1010 A
(C) 1072 A to 1092 A (D) 984 to 1004 A
Common data for Questions 47 and 48
Consider a sequential circuit shown below,

CLK
F

Q.47 The modulus number of given counter (in integer).

Q.48 If initial state of the counter is 100000 (A, B, C, D, E, F) then state after 7 clock cycles is :
(A) 100001 (B) 010001 (C) 001001 (D) 000101
Q.49 An 8-bit DAC produces Vout  0.05V for a digital input of 00000001. The % resolution and Vout
for an input of 00101010 will be. [MSQ]
(A) % resolution = 12.75 (B) % resolution = 0.392
(C) Vout  12.10 V (D) Vout  2.10 V
Q.50 A clock of frequency 4 MHz is applied to a 10 bit counter type ADC having step size of 0.1875
V. The conversion time (in  sec) for the analog input voltage of 6.437 V (rounded upto two
decimal places).
Q.51 A full adder is created using only two-input NAND gates. If the propagation delay of each
NAND gates is 50 ns, then the propagation delay (in nsec) to get the carry-out (in integer).
Q.52 The output ' P ' from the following logic circuit when the clock is a square wave with 50% duty
cycle. (Assume VCC as logic high)

(A) As same as the clock (B) Inversion to the clock

(C) Always zero (D) Always VCC
 8.14 Paramount 1111 [EE] GATE ACADEMY®
Q.53 The minimum number of NAND gates required to implement 4  1 multiplexer (in integer).
Q.54 The gray code number is 1011010. The number of 1’s present in excess-3 code representation
(in integer).
Q.55 Consider the logic circuit shown in figure below,

If A  B, then the expression for output ‘Y’ is,

(A) A  B (B) A  B (C) A  B (D) A  B
Q.56 Figure shows output of integrator of a dual slope integrator type digital voltmeter which has a
reference voltage of 500 volts and the fixed time of 500 counts. If the counter reads 432 in the
downward slope, then the voltage (in V) indicated by the DVM (in integer).

Q.57 Minimum Number of 2-input NAND gates required to implement the function
Y  AC  AD  BC , (in integer).
Q.58 A 2  1 multiplexer illustrated in figure (a) can be implemented using only 2 input NAND gates,
as shown in figure (b). Figure (c) gives the implementation of a function f using an inter
connection of these 2  1 multiplexer. It is assumed that the 2 input NAND gate’s propagation
delay from low to high & high to low are equal to 5 ns. Then the longest propagation delay (in
ns) from any input (d3d2 d1d0 s2 s1s0 ) to the output ( f ) from figure (c) (rounded upto two decimal
places)
GATE ACADEMY® Digital Electronics 8.15

Fig. (c)
Q.59 The circuit is used to produce a square wave. If switching times for multiplexes are 1μs , 2μs ,
2μs and 2μs as shown in figure, then the frequency ( f ) and duty cycle ( D) of V0 are
respectively

(A) f  10kHz , D  0.5 (B) f  100kHz , D  0.5

(C) f  10kHz , D  0.7 (D) f  100kHz , D  0.7
Q.60 Consider the digital circuit shown in figure,

If the clock is having a duty cycle of 50%, then the duty cycle (in %) of output P (correct upto
one decimal place)
Q.61 Consider the following logic circuit shown. Assume that the AND gate has a delay of 10 ns and
the OR gate has a delay of 5 ns.
8.16 Paramount 1111 [EE] GATE ACADEMY®

The timing diagram for V and Z for the circuit is

(A)

(B)

(C)

(D)
GATE ACADEMY® Digital Electronics 8.17
Q.62 The circuit shown in figure has two counters, neglect the propagation delay of circuit element
and wire.

If the input clock frequency of up-counter is 3.6 kHz, frequency of output wave form ' f0 ' (in
Hz) (rounded upto two decimal places)
Q.63 In the following circuit the comparator output is logic ‘1’ if Vi  VDAC and is logic '0' otherwise.
The Q3 Q2 Q1 Q0 are the counter outputs which is connected input of DAC. Initially counter start
from clear states. The steady value of counter in decimal (in integer).

Q.64 Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-
triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to
the same state on some value of “in” is _______.
 8.18 Paramount 1111 [EE] GATE ACADEMY®
Q.65 Consider a Boolean function f (w, x, y, z) such that
f ( w,0,0, z )  1
f (1, x,1, z )  x  z
f ( w,1, y, z )  wz  y
The number of literals in the minimal sum-of-products expression of f is ______.
Q.66 Consider the above logic circuit. [MSQ]
x
y

F
z

Which of the following options is/are true

(A) For y  z , it acts as an EX-NOR gate (B) For x  y, F  yz
(C) For x  z, F  yz (D) For x  y  z, F  1
Q.67 Consider the following sequential circuit : [MSQ]
1
J1 Q1 J2 Q2 J 3 Q3
K1 K2 K 3 Q3

clock
Assume initially Q1Q2Q3  000 , which of the following statement is correct about the circuit
(A) Q1Q2Q3 after 4 clock pulse = 001 (B) It is a MOD  5 counter
(C) It is a mod.6 counter (D) Q1Q2Q3 after 4 clock pulse = 101
Q.68 An X, Y Flipflop is designed using T-Flipflop which of the following can be the Booleam
function for the input of T of the T-Flipflop.
Consider the truth table of X-Y Flipflop as given below.
X Y Q Q
0 0 Toggle
0 1 1 0
1 0 0 1
1 1 Previous
(A) T  X  Y (B) T  XQn  XQn (C) T  XQn  YQn (D) T  X  YQn
GATE ACADEMY® Digital Electronics 8.19
Q.69 What is the output of the Flip-flops shown in teh fig. if the clock frequnency is 10 kHz.

(A) Output is always at 1.

(B) Output is always at 0.
(C) Output is always a signal with 5 kHz frequency.
(D) Output is same a clock signal with 10 kHz frequency.
Q.70 Consider a sequential circuit shown below,

The counter state (Q1Q0 ) follow the sequence

(A) 00, 10, 11, 00 ....................... (B) 00, 01, 10, 11 .......................
(C) 00, 10, 01, 00 ....................... (D) 00, 01, 11, 00 .......................
Q.71 In a 3-bit Counter type A/D converter Resolution is 0.50 V. The digital output of 1.13 volts
analog input is,
(A) 100 (B) 011 (C) 101 (D) 110
Q.72 In a 4-bit weighted resistor type D/A converter the resistor value corresponding LSB is 32 kΩ.
The resister value corresponding to MSB will be;
(A) 32 kΩ (B) 16 kΩ (C) 8 kΩ (D) 4 kΩ
Q.73 The initial content of the 4-bit serial-in-parallel out right below are 0110. After 5 clock pulses
the content of shift register will be,

(A) 010 (B) 0110 (C) 1110 (D) 0101

 8.20 Paramount 1111 [EE] GATE ACADEMY®
Q.74 An AB Flip-flop is constructed from an SR Flip-flop as shown below, the expression for the
next state Q(n 1) is

(A) AB  BQn (B) AB  BQn

(C) Both (A) and (B) (D) ( AB  AQn )
Q.75 For the given karnaugh map, which of the following represents the minimal expression in sum
of product (SOP) form

(A) X Y+Y’ Z (B) W’ X + Y’ Z + X Y

(C) X Z + Y (D) W X’ Y’ + X Y +X Z

Answers Digital Electronics

1. C, D 2. C 3. C 4. B 5. A, B, C, D
6. B, D 7. 5.625 8. D 9. A, B, C, D 10. A, B, C
11. 9 12. A, D 13. D 14. B 15. C
16. C 17. B 18. D 19. B, C 20. 6
21. B 22. B 23. A 24. A 25. C
26. 5 27. 25 28. 62.5 29. 5 30. A, B
31. 6 32. 8 33. C 34. A 35. B
36. D 37. C 38. D 39. C 40. B
41. A 42. A 43. D 44. 26 45. D
46. C 47. 10 48. C 49. B, D 50. 8.75
51. 250 52. B 53. 7 54. 6 55. A
56. 432 57. 6 58. 35 59. B 60. 75
61. B 62. 56.25 63. 8 64. 2 65. 6
66. B, C 67. A, C 68. C 69. C 70. C
71. B 72. D 73. C 74. A 75. D
GATE ACADEMY® Digital Electronics 8.21

Explanations Digital Electronics

1. (C), (D)

Given : F  A  B CD
F  ( A  B) (C  D)
F  ( A  B)(C  D)  ( A  B)(C  D)
 ( AB  AB)(CD  CD)  ( AB  AB)(CD  CD)
 ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
  m(0,3,5,6,9,10,12,15)  M (1,2,4,7,8,11,13,14)
Hence, the correct options are (C) & (D).
2. (C)

Given circuit is shown below,

From the above circuit,

F1  P  Q  R
F2  R( P  Q)  PQ  R( P Q)  PQ  R( PQ  PQ)  PQ
F2  PQR  PQR  PQ  PQR  P(QR  Q)  PQR  P(Q  R)  PQR  PQ  PR
F2  R(PQ  P)  PQ  R(Q  P)  PQ  PQ  QR  PR
(From distributive law, A  AB  A  B )
The function F1 is difference and F2 is borrow of a full subtractor circuit.
Hence, the correct option is (C).
 8.22 Paramount 1111 [EE] GATE ACADEMY®

3. (C)

Given : AB  CD  0,
Checking from the options :
(i) From option (A),
L.H.S  AB  C ( A  D)  0
 AB  C ( A  D)  AB  CD
 AB  AC  CD  AB  CD
 B( A  A)  D(C  C )  AC
 B  D  AC
R.H.S  AB  BD  BD  ACD  0
 AB  BD  BD  ACD  AB  CD
 B( A  A)  BD  BD  ACD  CD
 B(1  D)  BD  ACD  CD  B  BD  ACD  CD
 B  D  ACD  CD [ A  AB  A  B]
 B  D(1  C )  ACD  B  D  DAC
 B  ( D  D)  ( D  AC )
 B  D  AC [ A  AB  A  B]
Hence, L.H.S = R.H.S
Thus, option (A) is correct.
(ii) From option (B) :
L.H.S  AB  C ( A  D)  AB  CD
 AB  AC  CD  AB  CD
 B( A  A)  D(C  C )  AC
 B  D  AC = R.H.S
Thus, option (B) is correct.
(iii) From option (C) :
L.H.S  AB  C ( A  D)  0
 AB  C ( A  D)  AB  CD
 AB  AC  CD  AB  CD
 B( A  A)  D(C  C )  AC
 B  D  AC
And in option (C),
R.H.S  B  D  ACD  CD
Thus, L.H.S is not equal to R.H.S.
Hence, the correct option is (C).
GATE ACADEMY® Digital Electronics 8.23

4. (B)
Given circuit is shown below,
0 I0
1
1 I1 4 1 Y1 DA QA X
0 I2 MUX
1
C I3
S1 S 0

A B

C I0
2
C I1 4 1 Y2 DB QB Y
C I2 MUX
2
0 I3
S1 S 0

A B

0 I0
3
1 I1 4 1 Y3 DC QC Z
C I2 MUX
3
0 I3
S1 S 0

A B Clock
Initially A  0 , B  0 and C  0
(i) For MUX 1,
S1  A, S0  B , I 0  0, I1  1, I 2  0
Y1  S1S0 I0  S1S0 I1  S1S0 I2  S1S0 I3
Y1  AB  0  ABC  AB  0  ABC  ABC  ABC  0  0  0  0  0  0
So, DA  Y1  0
(ii) For MUX 2,
S1  A, S0  B , I0  C, I1  C, I2  C
Y2  S1S0 I0  S1S0 I1  S1S0 I2  S1S0 I3
Y2  ABC  ABC  ABC  AB  0  ABC  ABC  ABC  BC ( A  A)  ABC  BC  ABC
Y2  0  0  0  0  0  1
So, DB  Y2  1
(iii) For MUX 3,
S1  A, S0  B , I0  0, I1  1, I2  C, I3  0
Y3  S1S0 I0  S1S0 I1  S1S0 I2  S1S0 I3
 8.24 Paramount 1111 [EE] GATE ACADEMY®

Y3  AB  0  AB 1 ABC  AB  0  AB  ABC  1 0  0 1 0  0

So, DC  Y3  0
Now, X  QA (t  1)  DA  0
Y  QB (t  1)  DB  1
Z  QC (t  1)  DC  0
Hence, the correct option is (B).
5. (A), (B), (C), (D)
Checking from the options,
(A) A  B  AB  ( A  B)  AB  AB( A  B)
A  B  AB  ( A B)  AB  AB( A  B) {By Demorgan’s law x  y  x  y , x  y  x  y }
A  B  AB  ( AB  AB) AB  ( AB  AB) AB { x  x  1, x  x  0, x 1  x, x 0  0 }
A  B  AB  0  AB  AB( A  B)  AB( A  B)
A  B  AB  AB  AB  0  0  AB
A  B  AB  B  AB
A  B  AB  ( A  B)( B  B ) { x  0  x, x 1  1 }
A  B  AB  ( A  B) (True) …(i)
(B) By property of XOR and XNOR,
x yz  x y z
From equation (i)
A B AB  A  B (True)
(C) A  ( A  B)  A( A  B)  A( A  B)
A  ( A  B)  A  A  A  B  A( A  B)
A  ( A  B)  A  AB  AAB
A  ( A  B)  A(1  B)  AB
A  ( A  B)  A  B {By Demorgan’s law x  y  x  y , x  y  x  y }
A  ( A  B)  AB (True)
(D) A ( A  B)  A( A  B)  A( A  B)
A ( A  B)  AA  AB  AAB
A ( A  B)  0  AB  0
A ( A  B)  AB (True)
Hence, the correct options are (A), (B), (C) & (D).
6. (B), (D)
4 : 16 decoder using only 2 : 4 decoders
GATE ACADEMY® Digital Electronics 8.25

Five 2 : 4 decoder are required

4 : 16 decoder using two 3 : 8 decoders and an inverter

Two 3 : 8 decoder and one inverter is required

Hence, the correct options are (B) and (D).
7. 5.625

Given circuit is shown below,

 8.26 Paramount 1111 [EE] GATE ACADEMY®
Calculation for RTH : Whether switch connect to a or b, indirectly switches is connected to virtual
ground that’s in below figure all 20 k resistor connected to ground.

RTH  [{(20 || 20  10) || 20  10}|| 20  10]|| 20  10 k

Thus, the equivalent circuit diagram of above figure is,
10
I  1 mA
10k
Now, the circuit can be modified as,

From the above circuit, [{(20|| 20 10) || 20 10}|| 20 10]  20K , thus current I  1mA will be divide
equally on both resistors. Similarly [(20|| 20 10) || 20 10]  20K , thus current 0.5 mA will be divide
equally on both resistors and so on.
v1  10k  0.75mA
v1  7.5V
7.5
I1   0.75mA
10k
I 2  (0.1875  0.75) mA  0.5625mA
v0  10k  0.5625 mA
v0  5.625V
Hence, the correct answer is 5.625.
GATE ACADEMY® Digital Electronics 8.27

8. (D)

For full adder sum

S  A  B  Cin

For full adder carry is given by,

C  AB  BCin  Cin A

Note : No limitation given on number of input for any gate. Therefore, we can use 3-input gates.
Hence, the correct option is (D).
9. (A), (B), (C), (D)

X  AB  BC  A  B  B  C  A  B  C
Y  A X C  A A B C C
 8.28 Paramount 1111 [EE] GATE ACADEMY®

Hence, the correct options are (A), (B), (C) and (D).
10. (A), (B), (C)
Given, logic circuit can be modified as,

Output F can be written as

F  ( A  B) ( A B) C
For even number of inputs XOR is equal to complement of XNOR
i.e. A B  A B
and, XNOR is equality detector
So, ( A  B) ( A B)  0
Now, F  0 C
F  0 C  0  C  C
From given condition
F 1 C
C  0 is the required input condition.
Hence, the correct options are (A), (B) and (C).
11. 9

Given : f ( A, B, C, D)  AB  BC  BD  A(B  A)
f ( A, B, C, D)  AB  BC  BD  AB  AA  AB  BC  BD
A B – – – B C – – B – D
1 1 0 0 0 1 0 0 0 1 0 1
1 1 0 1 0 1 0 1 0 1 1 1
1 1 1 0 1 1 0 0 1 1 0 1
1 1 1 1 1 1 0 1 1 1 1 1
 m(12,13,14,15)  m(4,5,12,13)  m(5,7,13,15)
GATE ACADEMY® Digital Electronics 8.29
So, f ( A, B, C, D)   m(4,5,7,12,13,14,15)
f ( A, B, C, D)   m(0,1,2,3,6,8,9,10,11)
Hence, number of minterms  9
Hence, the correct answer is 9.
12. (A), (D)

Choosing from options,

From option (A) :
For upper MUX,
D  SI0  SI1
Here, S  X , I0  Y , I1  Y
D  XY  XY
D  X Y
For lower MUX,
B  SI0  SI1
Here, S  X , I 0  Y , I1  0
B  XY  X 0
B  XY
So, D shows expression of difference and B shows expression of borrow of half-subtractor.
Thus, option (A) is correct.
From option (D) :
For upper MUX,
B  SI0  SI1
Here, S  Y , I0  Y , I1  X
B  YY  YX  XY
For lower MUX,
D  SI0  SI1
Here, S  Y , I0  X , I1  X
D  YX  YX
D  X Y
So, D shows expression of difference of half subtractor and B shows expression of borrow of half-
subtractor.
Thus, option (D) is correct.
Hence, the correct options are (A) & (D).
 8.30 Paramount 1111 [EE] GATE ACADEMY®

13. (D)
Given K-map is shown below,

Prime implicant (PI) : CD, B, AD

Essential prime implicant (EPI) : CD, B, AD
Hence, Number of PI : 3
Number of EPI : 3
Hence, the correct option is (D).
14. (B)

 50  50
Voltage at inverting terminal of op-amp ‘P’ using VDR    6   6  1V
 50  100  100  50  300
Hence, Y0 will be ‘1’ if Vin  1V.
 100  50 
Similarly, voltage at inverting terminal of Q     6  3V
 50  100  100  50 
Hence, Y1 will be ‘1’ if Vin  3V.
 100  100  50 
Voltage at inverting terminal of R     6  5V
 50  100  100  50 
Hence, Y2 will be ‘1’ if Vin  5V.
The digital circuit shown will function as a priority encoder for flash ADC.
Therefore, the truth table can be constructed for 0  Vin  6 V as,

Input range Y2 Y1 Y0 C1 C0
Vin  1V 0 0 0 0 0
1V  Vin  3V 0 0 1 0 1
3V  Vin  5V 0 1 1 1 0
5V  Vin  6 V 1 1 1 1 1
GATE ACADEMY® Digital Electronics 8.31

Expressions for outputs in terms of Y2 , Y1 and Y0 can be written as,

C1  Y2 Y1 Y0  Y2 Y1 Y0  Y1 Y0 (Y2  Y2 )  Y1 Y0
C0  Y2 Y1 Y0  Y2 Y1 Y0  Y0 (Y2 Y1  Y2 Y1 )
C0  Y0 (Y2 Y1 )
Hence, the correct option is (B).
15. (C)
Given : Conversion time is 15 sec , Input voltage, V1  15 V, V2  20 V and n1  4, n2  8
Maximum conversion time of n-bit successive approximation ADC  n  TCLK
15 sec  4  TCLK
15
TCLK  sec
4
15
For 8-bit successive approximation ADC, maximum conversion time  8  TCLK  8  sec  30 sec
4
Note : Maximum conversion time of successive approximation ADC is independent of input voltage.
Hence, the correct option is (C).
16. (C)
If V  0 then B8 , B4 , B2 and B1 will appear at the outputs of XOR gates and circuit will act as adder.
If V  1 then output of XOR gates will be B8 B4 , B2 , B1 then the circuit will act as subtractor.
Hence, the correct option is (C).
 Key Point

If x  0, Y  B (works as buffer)
If x  1, Y  B (works as inverter)

17. (B)
According to the given logic circuit :
X D1 D0 Q1 Q0 Q1 Q0 Y
0 1 1 0 0 1 1 0
1 1 1 0 0 1 1 0
0 1 1 0 1 1 1 0
1 1 1 0 1 1 1 0
0 1 0 1 0 1 0 1
1 1 0 1 0 1 0 0
0 0 0 1 1 0 0 1
1 1 0 1 1 1 0 0
 8.32 Paramount 1111 [EE] GATE ACADEMY®
Hence, the state diagram is,

01

Hence, the correct option is (B).

18. (D)
Given circuit is shown below,

Outputs of 2  4 decoder are given as,

y0  AB 1  AB
y1  AB 1  AB
y2  AB 1  AB
y3  AB 1  AB
Output of MUX-1 is given as,
Y1  S1S0  0  S1S0 1 S1S0  0  S1S0  0
Y1  S1S0
Y1  ( AB)( AB)  ( A  B)( AB)
Y1  0  AB  AB
Output of MUX-2 is given as,
Y2  S1S0  0  S1S0 1 S1S0  0  S1S0  0
Y2  S1S0
Y2  ( AB)( AB)  ( A  B)( AB)
Y2  0  AB  AB
GATE ACADEMY® Digital Electronics 8.33

Given that, f ( A1B)  A B  AB  AB

Checking from option :

(A) AND AB  AB  0  A B
(B) OR AB  AB  A  B  A B
(C) NAND AB  AB  1  A B
(D) NOR AB  AB  ( A  B)( A  B)  AB  AB  A B
Hence, the correct option is (D).
19. (B), (C)
f ( A, B, C, D)  m(2,4,6,10,12) d (0,8,9,13)

f ( A, B, C, D)  C D  B D  A D
f ( A, B, C, D)  D( A  B  C)
f ( A, B, C, D)  ( A  B  C)D
Hence, the option (B) is correct.
f ( A, B, C, D)  ( A  B  C)D
f ( A, B, C, D)  ( A  B  C)  D
f ( A, B, C, D)  ( A  B  C)  D

Number of NOR gates required to implement f ( A, B, C, D) is 5.

Hence, the correct options are (B) and (C).
 8.34 Paramount 1111 [EE] GATE ACADEMY®

20. 6
Given : f ( A, B, C, D)   m(2,3,8,10,11,12,14,15)
K-map for function f ( A, B, C, D) is shown below,

Therefore, f  AC  AD  BC

F  A(C  D)  BC  A(CD)  BC  ACD  BC  ACD  BC

This function can be implemented using following gates :

Hence, minimum number of NAND gate required to realize the given function are ‘6’.
21. (B)
Given, the counter is initially reset i.e., Q2Q1Q0  000
As counter is working as MOD-5, so when state of Q2Q1Q0  (101)2  5 occurs, then the counter must
initiate its count from Q2Q1Q0  000
From the given diagram, when the output of logic gate is “0”, then the counter will go to reset condition.
So, the gate used must produce an output “0” for inputs Q2 and Q0 , for Q2Q1Q0  101 i.e.,
Q2  0 Q0  0

If Q2  0 and Q0  0, then the required logic gate that gives ‘0’ output is the OR gate.
Hence, logic gate = OR gate.
GATE ACADEMY® Digital Electronics 8.35

Q2 Q1 Q0 Number of state
0 0 0 01
0 0 1 02
0 1 0 03
0 1 1 04
1 0 0 05
1 0 1 Reset  000
Hence, the correct option is (B).
22. (B)
Given circuit shows,
Y  X 2  X1
Z  Y  X0

Hence, the correct option is (B).

23. (A)
Given, Initial state Q3 Q2 Q1 Q0  0000
Present State
CLR  Q3Q2 Is CLR activated?
Q3 Q2 Q1 Q0
0 0 0 0 1 No
0 0 0 1 1 No
0 0 1 0 1 No
0 0 1 1 1 No
0 1 0 0 1 No
0 1 0 1 1 No
0 1 1 0 1 No
0 1 1 1 1 No
1 0 0 0 1 No
1 0 0 1 1 No
1 0 1 0 1 No
1 0 1 1 1 No
1 1 0 0 0 Yes
 8.36 Paramount 1111 [EE] GATE ACADEMY®
This is MOD 12 counter.
The given counter is a MOD-12 counter. So, at 300 clock pulse counter will be at 1100 and after 300
clock pulse counter will be at 0000.
Hence, the correct option is (A).
24. (A)
The state table of the given circuit is shown below,
Present State Input Flip-Flop Input Next State
Q x D  xQ Q
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
0/0 0,1/1

1/1
0 1

Hence, the correct option is (A).

25. (C)
We know that,
For n bit DAC
Resistance of LSB  2n1  Resistance of MSB
20 k  2n1  Resistance of MSB
20
Resistance of MSB  [Here, n = 4]
2n1
20 20
 3   2.5 k
2 8
Hence, the correct option is (C).
26. 5
Given : Q2Q1Q0  000
GATE ACADEMY® Digital Electronics 8.37

Q0  LSB
Q2  MSB

Here counter counts only 4 state,

Hence after 15th clock pulses the state will be 1 0 1 and its decimal equivalent ‘5’.
Hence, the correct answer is 5.
27. 25
Given : Tsum  10ns, Tcarry  5ns, TOR  10 ns

Carry  ( A  B)C  AB
Total delay  10ns  5ns 10ns  25ns
Hence, the correct answer is 25.
28. 62.5
Given :
1. For D-flip flop,
t pd  4 ns
t setup  8 ns
2. For T-Flip Flop,
t pd  3 ns
tsetup  9 ns
According to question it is clear that, input of both flip flop depend upon output of both flip flop’s so it
is necessary to observe each flip flop carefully.
 8.38 Paramount 1111 [EE] GATE ACADEMY®
For D-Flip flop :
Maximum time taken by for D – Flip flop to produce output when clock arrived is,
TDFF  max(t pdD , t pdT )  t pdNAND  tsetupD
TD FF  max (4 ns, 3 ns)  4 ns  8 ns
TD FF  4 ns  4 ns  8 ns  16 ns
For T-Flip flop :
Maximum time taken by For T – Flip Flop to produce output when clock arrived is,
TT FF  max (t pdD , t pdT )  t pdEXOR  tsetup T
TT  FF  max (4 ns, 3 ns)  2 ns  9 ns
TT FF  4 ns  2 ns  9 ns  15 ns
For reliable operation of given circuit, the minimum clock time (TCLK ) should be,
(TCLK )min  max (TD-FF , TT -FF )  max (16 ns, 15 ns)
(TCLK )min  16 ns
Thus, maximum clock frequency is,
1 1
( fCLK )max    62.5 MHz
(TCLK )min 16 109
Hence, the correct answer is 62.5 MHz.
29. 5
Given counter is 3 bit down counter
To make Pre  0
QA  1, QB  0, QC  1
It means, QA  0, QB  1, QC  0
It shows, counter will be PRESET at QA , QB , QC  010
Note : As it is a positive edge triggered and Q is used as a clock to the next flip flop so it is a down
counter.
So, 3 bit counter count from
7 6 5 4 3

Thus it’s a mod – 5 counter.

Hence, the correct answer is 5.
30. (A), (B)
X  1, Y  1
D  X 1
Q' 1
Q'  0
GATE ACADEMY® Digital Electronics 8.39

XOR output = Q ' Y  0 1  1

J  Output of XOR = 1
K  Q' 1
Now for J  1, K  1
Q  1 (as reset initially, i.e. Qn1  0 )
X  0,Y  0
D X 0
Q'  0
Q' 1
XOR output  Q '  Y  1 0  1
J  Output of XOR  1
K  Q'  0
Now for J  1, K  0
Q 1
Hence, the correct options are (A) and (B).
31. 6
Given : V0 max  29.53125V
As the given OPAMP is an inverting amplifier, hence
V0 (max)   29.53125V
Maximum output occurs when all inputs are at logic high state,
i.e. b0 b1 b2 ..... bn1  1111.....1
For given weighted resistor DAC,
R R R R R 
V0  VRef   bn1   bn2   bn3  .....  n2  b1  n1  b0 
R 2R 4R 2 R 2 R 
 1 1 1 1 
 29.53125  15 1     .....  n1 
 2 4 8 2 
1 1 1 1
1.96875  1     .....  n1
2 4 8 2
n
1
1  
 N n 1  a N 1 
1.96875     a  1  a 
2
1  n 0 
1
2
n
1 1
1.96875   1   
2  2
n
1
 2   1  0.984375  0.015625
 
 8.40 Paramount 1111 [EE] GATE ACADEMY®
n 6
1 1 1
 2   64   2 
   
Therefore, the number of bits n  6 .
OR
n
1
 2   0.015625
 
Taking log both sides,
n
1
log10    log10 (0.015625)
2
n log10 (0.5)  log10 (0.015625)
log10 (0.015625)
 n 6
log10 (0.5)
Hence, the correct answer is 6.
32. 8

When S0  0 then I 0 is selected and when S0  1 then I1 line is selected.

Input bit in the register is S0 or Q4 .

Hence, the number of clock pulses after which the initial pattern we appear equal to 8.
GATE ACADEMY® Digital Electronics 8.41

33. (C)

Given :

From 2 to 4 decoder-1, truth table is given by,

A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
From the above truth table,
D0  AB , D1  AB
Now, from the circuit, F1  D0  D1  ( AB)  ( AB)  0
From 2 to 4 decoder-1, truth table is given by,
F1 C D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
From the above truth table,
D0  FC
1 , D2  FC
1

Now, F  FC
1  FC
1  C(F1  F1 )
F C
Hence, the correct option is (C).
34. (A)

Given :
Note : As it is a negative edge triggered and Q is used as clock for next flip flop so it is a up counter.
Initial state Q3 Q2 Q1 Q0  0000
 8.42 Paramount 1111 [EE] GATE ACADEMY®

Present State
CLR  Q3  Q2  Q3Q2 Is CLR activated?
Q3 Q2 Q1 Q0
0 0 0 0 1 No
0 0 0 1 1 No
0 0 1 0 1 No
0 0 1 1 1 No
0 1 0 0 1 No
0 1 0 1 1 No
0 1 1 0 1 No
0 1 1 1 1 No
1 0 0 0 1 No
1 0 0 1 1 No
1 0 1 0 1 No
1 0 1 1 1 No
1 1 0 0 0 Yes
This is MOD-12 up counter.
The given counter is a MOD-12 up counter.
So, at 612 clock pulse counter will be at 1100 but after 612 clock pulse counter will show 0000, because
clear signal will be activated.
Hence, the correct option is (A).
35. (B)

MUX of fixed size 8 : 1 can be used to design inverter.

For n variables, if inverter is NOT given, minimum size of MUX required is 2n .
For n variables, if inverter is given, minimum size of MUX required is 2n1.
According to question, number of variables is (n 1).
For ( n  1) variables, here inverter is not given, so minimum size of MUX required is 2n1.
Hence, the correct option is (B).
36. (D)

Flash converter : It has high speed has conversion takes place simultaneously rather than sequentially.
Typical conversion time is less.
Successive approximation : In successive approximation, the maximum conversion time is much less
and is given by N-bits.
Counter ramp : In counter ramp type ADC, D/A converter is used in feedback.
GATE ACADEMY® Digital Electronics 8.43

Fig. Counter ramp type ADC

Dual slope : We use integrator circuit in the circuitry of dual slope A/D converter. Therefore, it is also
called integrating type ADC.
Hence, the correct option is (D).
37. (C)
Given :
MUX 1 MUX 2
BA BA BA BA
I0 I1 I0 I1
C 0 6
C 3 7
X1  C X2 1 X3  C X4  0
Hence, the correct option is (C).
38. (D)
Given : (101)b  (467)10  ( D2)16 …(i)
Converting into equivalent decimal numbers,
(D2)16  (2 160 )  (13161 )  210
(101)b  (1 b0 )  (0  b1)  (1 b2 )  b2 1
From equation (i),
b2 1  467  210  257
b2  256
b  16
Hence, the correct option is (D).
 8.44 Paramount 1111 [EE] GATE ACADEMY®

39. (C)
Given function f  m(0, 1, 2, 5, 7, 9, 12, 15)
B as a data input and A, C, D as select input.

So, to implement,
f ( A, B, C, D)   m (0,1, 2,5,7,9,12,15)
Input lines from I 0 to I 7 must respectively be
B, 1, B, B, B, B, 0, B
Hence, the correct option is (C).
40. (B)
Resolution of a DAC is given as,
Full scale value
Resolution  …(i)
2n 1
Given, F.S. value of output  20mA
Resolution  80 A
From equation (i),
20 103
 80 10 6
2 1
n

20 103
2n  1 
80 10 6
2n  251
n  log2 (251)
n  7.971
 n 8
1 1
% Resolution  100%  8 100%  0.392%
2 1
n
2 1
% Resolution  0.39%
Hence, the correct option is (B).
41. (A)
Given : Reference voltage, VR  10 V
Resolution   0.2V
Resolution  Minimum analog output voltage
 Output corresponding to input at LSB only.
GATE ACADEMY® Digital Electronics 8.45

Connecting only LSB to VR and applying virtual ground concept,

V 0
KCL at V :
10  0 (0  Resolution)

16 K Rf
10 0.2

16 K R f
16 K  0.2 3.2 103
 Rf    320 
10 10
Hence, the correct option is (A).
42. (A)
For a dual slope ADC :
Applied voltage  Integration time  Reference voltage  De-integration time
 Va  ti  VR  td
100 103  370.2 103
Va   123.4 mV
300 103
Hence, the correct option is (A).
43. (D)
Given : MUX is enable only when A  1 i.e. always S1  1

Y  S1 S0 I 2  S1S0 I3
 ABA  ABC  AB  ABC
 A[B  BC]  A[B  B][B  C]  AB  AC
Hence, the correct option is (D).
 8.46 Paramount 1111 [EE] GATE ACADEMY®

44. 26
Given : N  4, Vr  10V, Va  6.25V
Conversion time for Va  Integration time + De-integration time
Integration time  2N Tc  24 Tc  16Tc
De-integration time  nTc
Va N 6.25
Where, n  2  16  10
Vr 10
Total conversion time  16Tc  10Tc  26Tc
 No. of clock pulse utilized  26
Hence, the correct answer is 26.
45. (D)
Given : N  5, b0  1, b1  0, b2  0, b3  1, b4  1
Rf  20 b  21 b1  22 b2  23 b3  24 b4 
V0   Vcc  0 
3R  25 
5R  20 1  21  0  22  0  23 1  24 1
V0  
3R  
5
25 
V0  6.51V
Hence, the correct option is (D).
46. (C)
Given : Number of bit = 8, full scale value = 2 mA, full scale error = 0.5% , Digital input = 10001010
FSV 2mA
Resolution  n   7.84 A
2 1 255
Convert binary number to digital number,
(10001010)2  (1 27 )  (0  26 )  (0  25 )  (0  24 )  (1 23 )  (0  22 )  (1 21)  (0  20 )
 (138)10
Ideal output  138 7.84 A 1082 A
Error  0.5%  F.S. output  0.5% 2mA  10 A
The range of output is, (1082 10)A  1092Ato1072 A
Hence, the correct option is (C).
47. 10
Given :
1. Five bit ring counter.
2. For n-bit ring counter.
Total states  2n
Used state  n
Unused state  2n  n
GATE ACADEMY® Digital Electronics 8.47
Therefore, MOD of ring counter  MOD n , (Here, n  5)
 MOD 5
MOD of JK-FF is 2.
Since, the ring counter and JK-FF are used in cascade so the MOD of the given counter
 MOD(RC)  MOD(JK)
 5 2  10
Thus, it is MOD 10 counter.
Hence, the correct answer is 10.
48. (C)
Given : 5-bit ring counter and JK flip-flop triggered only one edge of E.

Hence, the correct option is (C).

49. (B), (D)
Given :
1. Vout  0.05V for a digital input of 00000001
2. Number of bits N  8
3. Step size  0.05 V
4. Number of steps  2N 1  28 1  255
 8.48 Paramount 1111 [EE] GATE ACADEMY®
Now, full-scale voltage  Step size  Number of steps
 0.05 255  12.75V
1 1
% Resolution  100  100  0.392%
2 1
N
255
Vout for an input of (00101010)2  [0  27  0  26 1 25  0  24 1 23  0  22 1 21  0  20 ] 0.05
 (42)10  0.05  2.10 V
Hence, the correct options are (B) & (D).
50. 8.75

Given : For a counter type ADC

Vin
Number of steps required  [Next integer value, if result contains fraction]
Step size
6.437
  34.33
0.1875
 Number of steps required = 35
1 1
Conversion time, tconversion  35   35   8.75 sec
fCLK 4 106
Hence, the correct answer is 8.75  sec .
51. 250

For full adder carryout and sum expression is given as follows :

Sum(s) = A  B  Cin
Cout = Cin (A  B)  AB

Cout  Cin ( A  B)  AB
Cout = Cin (A  B).AB

So, total delay for carry out will be  50  50  50  50  50  250ns

Hence, the propagation delay to get the carry out is 250 ns.
GATE ACADEMY® Digital Electronics 8.49

52. (B)
Given circuit is shown below,

Hence, the correct option is (B).

53. 7
For 4  1 MUX, the output is given by,

Y  S1S0 I0  S1S0 I1  S1S0 I2  S1S0 I3

Y  S1S0 I 0  S1S0 I1  S1S0 I 2  S1S0 I 3

Y  (S1S0 I 0 )(S1S0 I1 )(S1S0 I 2 )(S1S0 I3 )

 8.50 Paramount 1111 [EE] GATE ACADEMY®
Now, implementation of function Y by using NAND gate is given by,

Number of NAND gate = 7.

Hence, the correct answer is 7.
54. 6
Given gray code is 1011010
First, convert the gray code 1011010 to binary equivalent

Then convert binary to decimal equivalent

(1101100)2  (26 1)  (25 1)  (23 1)  (22 1)  (108)10
Convert to Excess-3 code
(108)10  (0100 00111011) Excess-3 code
 Number of 1’s present = 6
Hence, the correct answer is 6.
55. (A)
Given circuit is shown below,
GATE ACADEMY® Digital Electronics 8.51
Individual output of each gate is shown below,
(As A  B)

(NAND gate works as an invertor if one input is ‘1’)

(As A  B)

 AB
One of A and B will be ‘0’.
Hence, output of gate ‘d’ will be ‘0’.

NOR gate works as an invertor if one input is fixed at ‘0’.

As A  B,

Hence, the correct option is (A).

56. 432
In dual slope integrator type DVM, first the analog voltage, which is to be converted, is integrated for a
fixed time (usually for 2n clock pulses) and then a reference voltage of opposite polarity is integrated
until the integrator output returns to zero.

i.e.,
 8.52 Paramount 1111 [EE] GATE ACADEMY®
Given, T1  500 TCLK
T2  432 TCLK
VR  500 V
T 
 Va   2 VR
 T1 
432TCLK
Va   500V  432V
500TCLK
Hence, the correct answer is 432 V.
57. 6

Given : Y  A(C  D)  BC

Y  A(C  D)  BC

A(C  D)  BC  A(CD)  BC

Hence, minimum number of 2 input NAND gate required to realize, the given function is ‘6’.
Hence, the correct answer is 6.
58. 35
Given :
S S0

S d0
S1
d1
d0 d0
f
S2
d1 d2
f
d1
f
d3
Fig.(a) Fig.(b) Fig.(c)
From the above figure, choosing longest path from S0 to f,
GATE ACADEMY® Digital Electronics 8.53

Hence, total propagation delay = 5 + 10 + 10 + 10 = 35 ns

Hence, the correct answer is 35.
59. (B)

Given : 2  1 MUX with I 0  1 and I1  0 will give output y  A as shown in figure,

1 I0
2 1
y  A.1  A.0  A
MUX

0 I1

A
So, all the MUX in the given circuit are working as NOT gate, in which only first three MUX will decide
the time period as shown below,
 8.54 Paramount 1111 [EE] GATE ACADEMY®
T  10 s
106
f   100 kHz
10
5
D  0.5
10
Hence, the correct option is (B).
60. 75

Given : D0  Q1 and D1  Q0
FF1  + ve edge trigger
FF0  – ve edge trigger

Ton 3T / 2
Duty cycle   100%  75%
Ton  Toff 2T
Hence, the correct answer is 75%.
GATE ACADEMY® Digital Electronics 8.55

61. (B)
Given : AND gate and OR gate, truth table is shown below,

For AND gate, output V will be 1 when W  X  1 and it will be delayed by 10 ns

Hence, the correct option is (B).

62. 56.25
Q3 Q2 Q1 Q0  4 bit asynchronous counter
For every 8th clock pulse ' Q2 ' of 1st counter can change from 1 to 0 i.e. its repeat value after 8th pulse
After change it state from 1 to 0 it trigger 2nd counter. Counter 2nd (Johnson) Q3 is Mod-8 (2n)
3.6 1000 3600
f0   Hz
8 8 64
f0  56.25Hz
Hence, the correct answer is 56.25 Hz.
 8.56 Paramount 1111 [EE] GATE ACADEMY®

63. 8

10
Given : Vi   7.5 k  7.5Volt
(2.5 k  7.5 k )
If Q3 Q2 Q1 Q0  1000
Where VDAC  8Volt which is greater then Vi
VDAC  Vi
So comparator output is ‘0’
Hence, No clock reach to the counter.
Counter can count the sequence up to 1000
Decimal equivalent (Q3 Q2 Q1 Q0  1000) is 8.
Hence, the correct answer is 8.
64. 2

Given : 2-bit sequential circuit is shown below,

Initial states of given circuit is not given in question. So, consider 4-cases
Case 1 : When initial state Q0Q1  00 and input (in) is 0 or 1. So next state (Q0Q1 ) and ‘out’ is

Case 2 : When initial state (Q0Q1 )  01 and input (in) is 0 or 1, so next state (Q0Q1 ) and ‘out’ is,

Case 3 : When initial state (Q0Q1 )  10 and input (in) is 0 to 1, so next state (Q0Q1 ) and ‘out’ is,
GATE ACADEMY® Digital Electronics 8.57

Case 4 : When initial state (Q0Q1 )  11 and input (in) is 0 to 1, so next state (Q0Q1 ) and ‘out’ is,

Combined all four cases to get compact state table as,

So, the question asking about the self-repeating state/self-loop in state-transition diagram, so from state
table it is clear that, only 2-self repeating state can be found.
Thus, number of state that have transition back to same state on some value of “in” is 2.
State diagram can also be sketched from state table as,

(State transition diagram)

Here, x / y  x  Input and y  Output.
Again, state diagram also showing 2-self loop.
Hence, number of state in state diagram that have a transition back to the same state on some values of
‘in’ is 2.
65. 6

Given : Boolean function f (w, x, y, z) such that

f (w,0,0, z)  1
f (1, x,1, z)  x  z
f (w,1, y, z)  wz  y
 8.58 Paramount 1111 [EE] GATE ACADEMY®
Truth table for above expression is,
w x y z f
0 0 0 0 1
0 0 0 1 1
0 0 1 0 x
0 0 1 1 x
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
From the above table SOP function is
f (w, x, y, z)   m (0, 1, 6, 7, 8, 9, 11, 13, 14, 15) + d (2, 3)
SOP K-Map for f (w, x, y, z) :
yz yz yz yz
wx 1 1  

wx 0 0 1 1 yx

wx 0 1 1 1

wz
wx 1 1 1 0
xy

So, minimized function in SOP format is, f  xy  xy  wz

Therefore, the number of literals in the minimal sum of products expression of f is 6.
Hence, the correct answer is 6.
66. (B), (C)
x
x
x yz
y
y
z
x
xyz
y F
z
z
y
xy
x
GATE ACADEMY® Digital Electronics 8.59
From the given circuit we can write,
F  x yz  xyz  xy
F  xz( y  y)  xy
F  xz  xy
Now, for y  z , we get
F  xz  xz
F  xz
 It act as EX-OR gate.
Now, for x  y , we get
F  yz  yy
F  yz ( yy  0)
Now, for x  z , we get
F  zz  zy
F  zy ( zz  0)
Now, for x  y  z , we get
x yza
 F  aa  aa
F 0
Hence, the correct options are (B) and (C).
67. (A), (C)

Initial state of Q1Q2Q3  000

Present state Inputs Next state
J1 K 1 J2 K2 J3 K 3 Q1 Q2 Q3 Initial state (0th clock
Clock
Q1 Q2 Q3 pulse)
1 1 Q1Q3 Q1 Q1Q2 Q1 0 0 0
1 0 0 0 1 1 0 0 0 0 1 0 0
2 1 0 0 1 1 1 1 0 1 0 1 0
3 0 1 0 1 1 0 0 0 0 1 1 0
4 1 1 0 1 1 1 1 1 1 0 0 1
5 0 0 1 1 1 0 0 0 0 1 0 1
6 1 0 1 1 1 0 1 0 1 0 0 0 Same as 0th clock pulse
 Hence, the given counter is MOD-6 counter as the initial state repeat itself after 6th clock pulse
and after 4th clock pulse Q1Q2Q3  001
Hence, the correct options are (A) and (C).
 8.60 Paramount 1111 [EE] GATE ACADEMY®

68. (C)
Truth table for T flip-flop,
T Qn Qn1
0 0 0
0 1 1
1 0 1
1 1 0
So, we can see that when Qn and Qn 1 is same than T  0 and when Qn1  Qn then T  1
XY flip-flop to T-flip-flop :
X Y Qn Qn1 T
0 0 0 1 1
0 0 1 0 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 0
1 1 1 0 1
1 1 0 0 0
1 1 1 1 0
K-Map :
XY XY XY XY
Qn 1 1
Qn 1 1

 T  XQn  YQn
Hence, the correct option is (C).
69. (C)
Given : We have, D-FF
Characteristic equation, Qn1  D

D Qn

CLK Qn

D-FF EXOR-Application,
For odd no. of 1’s it gives 1 otherwise ‘0’.
MOD-2
f 10
 fout  clk   5 kHz
2 2
Hence, the correct option is (C).
GATE ACADEMY® Digital Electronics 8.61

70. (C)
Given :

T0 Q0 T1 Q1

Q0 Q1

CLK

Characteristic equation of T-FF,

Qn1  T  Qn
T0  Q1
T1  Q0  Q1  Q0 Q1  Q0Q1  Q0Q1
State table :
Q1 Q0 T1 (Q0 Q1 ) T0 (Q1 )
0 0 1 0
0 1 0 0
1 0 0 1
1 1 1 1
State diagram :
00 10 01

Hence, the correct option is (C).

71. (B)
Given : Resolution  0.5V
Input voltage  1.13V
Step size = 0.5 V
1.13
Total steps   2.26
0.5
For digital we will take 2.26  3
Digital output = 011
Hence, the correct option is (B).
 8.62 Paramount 1111 [EE] GATE ACADEMY®

72. (D)
Given : 4-bit weighted resistor
LSB  32 k
MSB resistor  2n1 R  32
Where, n  4
 23 R  32 k
R  4 k
Hence, the correct option is (D).
73. (C)
Q3 Q2 Q1 Q0

0 1 1 0
Serial in

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Clk

0 1 1 0 1 0 1 1 1
1 0 1 1 0 1 0 1 2
0 1 0 1 1 0 1 0 3
1 0 1 0 1 1 0 1 4
1 1 0 1 1 1 1 0 5
After 5-clock pulse the content of shift resistor is 1110.
Hence, the correct option is (C).
74. (A)

Given :
A
S Q

B R Q
GATE ACADEMY® Digital Electronics 8.63

A B Qn S R Qn1
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 1 1 
0 1 1 1 1 
1 0 0 1 0 1
1 0 1 1 0 1
1 1 0 0 1 0
1 1 1 0 1 0
Characteristic table :
BQn
A
BQn BQn BQn BQn

A
A

Qn1  AB  BQn
Hence, the correct option is (A).
75. (D)

Given : K-map of above figure

WX
YZ 00 01 11 10
00 0 X 0 X

01 X 1 X 1

11 0 X 1 0

10 0 1 1 X

ZX  YX  YWX
Hence, the correct option is (D).

