VLSI DESIGN FLOW: RTL TO

GDS

Lecture 3
Overview of VLSI Design Flow: I
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Overview of VLSI Design Flow
▪ Design Flows

▪ Abstraction

▪ Pre-RTL Methodologies

▪ Hardware—software partitioning

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VLSI Design Flow: A top-level
perspective

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Chip Designing: Input and Output

How to tackle this problem?

Divide and conquer

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VLSI Design Flow: Divide and Conquer
RTL: Register Transfer Level (Verilog, VHDL)
GDS: Graphical Database System (Layout)

Idea to RTL Flow: takes a high-level

idea/concept of a product and represents the
hardware portion of the implementation in
RTL.
RTL to GDS flow: takes an RTL through various
stages of logical and physical design steps
and finally represents the design as GDS.

GDS to Chip Processes: takes a GDS, prepares

masks for a given GDS and
fabricates/tests/packages chips

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VLSI Design Flow: A top-level
perspective

Abstraction

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Abstraction: Basic Concept
Abstraction: Level of Representation
Abstraction
▪ Hiding lower level details in a
description
Idea to RTL Very high System,
▪ As a design moves through VLSI design flow Behavior
flow:
➢ Details are added RTL to GDS Decreases RTL, Gate,
➢ Abstraction decreases flow subsequently Transistor,
down the flow Layout
GDS to No abstraction, Mask, Integrated
chip actual Circuit.
implementation

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Why to Abstract?
Scope of Turn-around
Considerations for design tasks:
Optimization time
▪ Optimization: Choosing right
combination of design parameters Idea to RTL Flow Very High Low
to obtain desired QoR by trading-
off some of them.

▪ Turn-around Time: Time taken to RTL to GDS flow Decreases Increases

make changes in a design subsequently down subsequently
the flow down the
Impact of Abstraction: flow
▪ At higher level of abstraction large
number of solutions can be GDS to Chip No optimization. Very costly
analyzed in less amount of time. flow Some corrections. re-spin

▪ Result of optimization at the higher

level of abstraction is expected to
be better.
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Abstraction: Illustration
Consider that the functionality is represented in two ways:
A. Logic Formula: 𝐹 = 𝐴 + 𝐵 ′
B. Using a standard cell delivering NOR function placed and connected on the layout.

Which of the above representations:

1. Has greater abstraction?
Ans: A
2. Smaller turn-around time in evaluating different implementations?
Ans: A
3. Greater accuracy in evaluation?
Ans: B

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Pre-RTL Methodologies

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Pre-RTL Methodologies

System-level
Design

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System-level Design: Top View
Evaluation of “idea”:
• Market requirement
• Financial viability
• Technical feasibility

Preparing specifications:
• Features (functionality)
• PPA
• Time to market (TTM)
HW—SW Partitioning:
• Identify components
• Determine which components to
implement in HW/SW

• HW/SW Development (separately)

• System Integration, Validation, Test
• Final Product
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 Pre-RTL Methodologies

Hardware—software
Partitioning

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Hardware—Software Partitioning: Motivation
Motivation: Exploit the merits of both hardware and software by choosing right combination of
hardware and software to implement a given function

Hardware Software
Performance High Low
Cost High Low
Risk due to bug High Low
Customization Low High
Development Time High Low

• Hardware: usually runs as parallel circuits and

can have very good PPA
➢ Can be implemented in full custom IC,
ASIC or FPGA
• Software: usually run sequentially on a
general purpose processor

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Hardware/Software Partitioning: Example
Video Compression
• Algorithm can be divided in two main parts:
1. Computing Discrete Cosine Transform (DCT):
Performed multiple times, bottleneck
2. Frame Handling and other computation

• DCT • Frame Handling and other

➢ Hardware for computing DCT computation
➢ Can be computed using parallel ➢ Software on a general purpose
circuits microprocessor
➢ Several orders of magnitude faster ➢ Provides Flexibility
and more energy efficient
implementation in hardware

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Hardware/Software Partitioning: Methodology(1)
Objective: Finding a minimum set of
functions that need to be implemented in
hardware to achieve the desired
performance
Inputs:
• Given algorithm that is implemented
entirely in software
➢ 𝑆 contains set of functions
implemented in software
• Acceptable performance 𝑃
• Parameter for the algorithm 𝑁: maximum
number of functions to be move to
hardware in each iteration
Output:
• Set of function 𝐻 to be implemented in
hardware (initially 𝐻 is empty)

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Hardware/Software Partitioning: Methodology (2)
Measure performance: 𝐸𝑣𝑎𝑙𝑢𝑎𝑡𝑒(𝐻, 𝑆)
Profiling: Measures frequency or duration of
each function calls [𝑃𝑟𝑜𝑓𝑖𝑙𝑒(𝐻, 𝑆)]
In each iteration:
• Identify 𝑖 − 𝑡ℎ most severe bottleneck
function 𝑓𝑖
➢ Assume that 𝑓𝑖 is implemented in the
hardware
➢ Measure performance and check
whether target performance 𝑃 is met
• Moves maximum of N most critical
bottleneck functions to hardware
Termination criteria:
• Success: Performance target P is met
• Failure: No improvement even after moving
𝑁 functions to hardware
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Hardware/Software Partitioning: Methodology (3)

• Takes a greedy approach

• Very simplistic

Challenges:
• Performance estimation
• Verification: hardware-software co-
simulation

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 References
▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,
2023.

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