VLSI DESIGN FLOW: RTL TO

GDS

Lecture 4
Overview of VLSI Design Flow: II
Sneh Saurabh
Electronics and Communications
Engineering
IIIT Delhi
Lecture Plan
Pre-RTL Methodologies

▪ Functional description to RTL

▪ Reusing RTL

▪ Behavior Synthesis

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 Pre-RTL Methodologies

Functional
Specification to RTL

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Functional Specification

▪ Functional Specification can be made at a

higher level of abstraction

▪ Opens up implementation gap

▪ Need to convert to RTL

➢ Describes data flow from register to
register at various time instants or clock
cycle
➢ Carries timing information

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RTL: General Structure

RTL: Register Transfer Level

▪ Modelling of circuit as flow of data (signal)

between registers

▪ RTL can also be referred to as “data flow”

description

▪ FSM generates control signals

▪ MUX passes the data based on control

signals
▪ Computation is done on the data path

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Functional Specification to RTL

▪ Manual Coding: straight forward

▪ IP Assembly: reusing existing RTL

▪ Behaviour synthesis: automatic method of

generating RTL from high-level language

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 Pre-RTL Methodologies

Reusing RTL

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System-on-chip (SoC) Design Methodology

▪ Reusing RTL is especially popular in SoC (system-on-chip) design methodologies

System-on-chip (SoC)

▪ A complete system built on a single chip

▪ Composed of:
➢ Processors, hardware accelerators, memories, peripherals, analog components, and RF
devices connected using some structured communication links
➢ Embedded software

▪ Merits:
➢ Improves productivity
➢ Lowers cost
➢ Increases features

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Intellectual Properties (IP)

Intellectual Properties (IP) Sharing of Information:

▪ Pre-designed and pre-verified sub- ▪ IPs contain information related to
systems or blocks structure, configurability, and interfaces
of the subsystem
▪ Can be developed internally or
purchased from IP vendors ▪ Challenge: how to package the
information?
Content:

▪ Hardware blocks: processor, memory,

interface, etc.

▪ Software: real-time operating system

(RTOS), device drivers, etc.

▪ Verification IPs (VIPs) eases verification

effort
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Integration of IPs
Integration of IPs (IP Assembly) Configuring IPs
▪ Instantiating various IPs in an SoC and ▪ IPs can have configuration parameters such
making their connections as bus width, power modes, and
communication protocols
▪ IP assembly involves choosing the set of
Method configuration parameters
▪ Metadata: top-level IP models, bus ▪ Challenges: optimality and consistency
interfaces, ports, registers, and the
required configuration
➢ IP-XACT, SystemRDL, XML, or Communication Links
spreadsheet ▪ Ad-hoc bus-based
▪ Generator tools: produce an SoC-level ▪ Structured network on chip (NoC)
RTL with instantiated IPs.
➢ A generator tool can also produce a Verification Challenges
verification environment and low-
level software drivers. ▪ Huge functional space
▪ Software and Hardware

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 Pre-RTL Methodologies

Behaviour Synthesis

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Behavioral Synthesis: What?

Behavioral Synthesis

• Process of converting an
algorithm (not timed) to an
equivalent design in RTL (fully
timed) and satisfy the
specified constraints.

• Behavioral Synthesis is also called High-level Synthesis

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Behavioral Synthesis : Cost Metrics (1)
• An untimed algorithm can be implemented in many different ways
• Different implementations can have different cost metrics

Cost Metrics:
• Area: number of circuit elements
• Latency: number of clock cycles required before results are available
• Maximum clock frequency: worst case combinational delay
• Power dissipation, Throughput, etc.

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Behavioral Synthesis : Maximum Clock Frequency
Consider a synchronous circuit:
• Path: sequence of pins through which a signal can propagate
• Combinational path: a path that does not contain any sequential circuit element such as a
flip-flop
• Sequentially adjacent flip-flops: if the output of one flip-flop is fed as an input to the other
flip-flop through a combinational path

• Clock period should be

greater than the delay of the
critical path (𝑇𝑝 > 𝑑𝑚𝑎𝑥 )
• Maximum clock frequency
𝑓𝑚𝑎𝑥 < 1/𝑑𝑚𝑎𝑥
• Critical Path: the
combinational path that has
the largest delay in the circuit
Synchronous circuit: data launched must be captured by (approximately)
the sequentially adjacent flip-flop in the next clock cycle.

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Behavioral Synthesis: Illustration (1)
• Algorithmic behavior: 𝑌 = 𝑎 + 𝑏 + 𝑐
• Cost metrics: circuit elements used, latency, and maximum delay of combination path.

Resources Resources
• 2 Adders (+) and 1 Register • 2 Adders (+) and 2 Registers
Latency Latency
• 1 clock cycle • 2 clock cycle
Worst Delay Worst Delay
• Delay of 2 Adders • Delay of 1 Adders

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Behavioral Synthesis: Illustration (2)
• Adder is used in the first cycle to
compute (𝑌 = 𝑎 + 𝑏) and is used
in the next cycle to compute
(𝑌 = 𝑐 + 𝑌)

• Inputs to adders are controlled

by multiplexers
• Multiplexers get “𝑠𝑒𝑙𝑒𝑐𝑡” signal
from the control circuitry
Resources
• 1 Adders (+), 2 Register, 2
Multiplexer and 1 Inverter
Latency
• 2 clock cycle
Worst Delay
• Delay of 1 Adder + Multiplexer

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Behavioral Synthesis: Evaluating Trade-offs
Area (𝝁𝒎𝟐 ) Delay (ns)
Let us compute the area, latency and critical path
Inverter 1 1 delay for three implementations.
Multiplexer 6 10
Adder 200 100
Flip-flop 12 0 RTL-1 RTL-2 RTL-3

Area 412 424 237

Latency 1 2 2
cycle cycle cycle

Delay 200 100 110

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Behavioral Synthesis: Untimed to Timed Behavior

Algorithmic behavior: 𝑌 = 𝑎 + 𝑏 + 𝑐 RTL-1 RTL-2 RTL-3

Timed Behavior Area 412 424 237

• Three different “timed” implementation
illustrated Latency 1 cycle 2 cycle 2 cycle
• There can be several other Delay 200 100 110
implementations
• Behavior synthesis tool will choose the
best possible implementation satisfying Which RTL will be generated when:
the constraints • Area is to be minimized?
• Latency is to be minimized?
Trade offs • Clock Frequency is to be maximized?
• Behavior synthesis tool can trade off
one FoM to improve other FoM

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Behavioral Synthesis: Merits and Challenges
Merits: Challenges:
• Automatic exploration of different • Physical design:
possible implementations ➢ Down the flow the QoR may degrade due
➢ More exhaustive than to other metrics such as congestion not
handwritten RTL taken into account
• Reduces design effort • Incremental changes:
• Less chance of introducing errors ➢ Lacks readability and debuggability
compared to handwritten RTL • Verification challenges

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 References
▪ G. D. Micheli. “Synthesis and Optimization of Digital Circuits”. McGraw-Hill Higher Education,
1994.

▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press,

2023.

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