Features

• Compatible with MCS-51® Products

• 32K Bytes of Reprogrammable Flash Memory
• Endurance: 1000 Write/Erase Cycles
• 4V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 512 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
•
•
Eight Interrupt Sources
Programmable Serial Channel
8-bit
•
•
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Microcontroller
• Hardware Watchdog Timer
• Dual Data Pointer with 32K Bytes
• Power-off Flag
Flash
Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read only memory and 512 bytes of RAM. The
AT89C51RC
device is manufactured using Atmel’s high-density nonvolatile memory technology and
is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout.
The on-chip Flash allows the program memory to be user programmed by a conven-
tional nonvolatile memory programmer. A total of 512 bytes of internal RAM are
available in the AT89C51RC. The 256-byte expanded internal RAM is accessed via
MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The other
256-byte RAM segment is accessed the same way as the Atmel AT89-series and
other 8052-compatible products. By combining a versatile 8-bit CPU with Flash on a
monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.

Rev. 1920B–MICRO–11/02

1
Pin Configurations
TQFP

P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.0 (T2)

VCC
P1.4
P1.3
P1.2

NC
44
43
42
41
40
39
38
37
36
35
34
P1.5 1 33 P0.4 (AD4)
P1.6 2 32 P0.5 (AD5)
P1.7 3 31 P0.6 (AD6)
RST 4 30 P0.7 (AD7)
(RXD) P3.0 5 29 EA/VPP
NC 6 28 NC
(TXD) P3.1 7 27 ALE/PROG
(INT0) P3.2 8 26 PSEN
(INT1) P3.3 9 25 P2.7 (A15)
(T0) P3.4 10 24 P2.6 (A14)
(T1) P3.5 11 23 P2.5 (A13)

12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
PDIP
(T2) P1.0 1 40 VCC
(T2EX) P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP
(TXD) P3.1 11 30 ALE/PROG
(INT0) P3.2 12 29 PSEN
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)

PLCC
P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.0 (T2)

VCC
P1.4
P1.3
P1.2

NC
6
5
4
3
2
1
44
43
42
41
40

P1.5 7 39 P0.4 (AD4)

P1.6 8 38 P0.5 (AD5)
P1.7 9 37 P0.6 (AD6)
RST 10 36 P0.7 (AD7)
(RXD) P3.0 11 35 EA/VPP
NC 12 34 NC
(TXD) P3.1 13 33 ALE/PROG
(INT0) P3.2 14 32 PSEN
(INT1) P3.3 15 31 P2.7 (A15)
(T0) P3.4 16 30 P2.6 (A14)
(T1) P3.5 17 29 P2.5 (A13)
18
19
20
21
22
23
24
25
26
27
28
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

2 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC

PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. PORT 0 PORT 2

REGISTER RAM FLASH
LATCH LATCH

PROGRAM
B STACK ADDRESS
ACC POINTER
REGISTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING DUAL
AND INSTRUCTION
EA / VPP CONTROL REGISTER DPTR

RST

PORT 1 PORT 3
LATCH LATCH
WATCH
DOG

OSC
PORT 1 DRIVERS PORT 3 DRIVERS

P1.0 - P1.7 P3.0 - P3.7

3
1920B–MICRO–11/02
Pin Description
VCC Supply voltage.

GND Ground.

Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.

Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)

Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.

Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are exter-
nally being pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C51RC, as
shown in the following table.

4 AT89C51RC
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 AT89C51RC

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

RST Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives High for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In
the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and
may be used for external timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the
bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.

PSEN Program Store Enable is the read strobe to external program memory.
When the AT89C51RC is executing code from external program memory, PSEN is acti-
vated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (V PP ) during Flash
programming.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

5
1920B–MICRO–11/02
Table 1. AT89C51RC SFR Map and Reset Values

0F8H 0FFH

B
0F0H 0F7H
00000000

0E8H 0EFH

ACC
0E0H 0E7H
00000000

0D8H 0DFH

PSW
0D0H 0D7H
00000000

T2CON T2MOD RCAP2L RCAP2H TL2 TH2

0C8H 0CFH
00000000 XXXXXX00 00000000 00000000 00000000 00000000

0C0H 0C7H

IP
0B8H 0BFH
XX000000

P3
0B0H 0B7H
11111111

IE
0A8H 0AFH
0X000000

P2 AUXR1 WDTRST
0A0H 0A7H
11111111 XXXXXXX0 XXXXXXXX

SCON SBUF
98H 9FH
00000000 XXXXXXXX

P1
90H 97H
11111111

TCON TMOD TL0 TL1 TH0 TH1 AUXR

88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000 XXX00X00

P0 SP DP0L DP0H DP1L DP1H PCON

80H 87H
11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000

6 AT89C51RC
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 AT89C51RC

Special Function A map of the on-chip memory area called the Special Function Register (SFR) space is
Registers shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be
implemented on the chip. Read accesses to these addresses will in general return ran-
dom data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in
Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit
auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two pri-
orities can be set for each of the six interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
7 6 5 4 3 2 1 0

Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK
= 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

7
1920B–MICRO–11/02
Table 3a. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00X00B
Not Bit Addressable
– – – WDIDLE DISRTO – EXTRAM DISALE
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
EXTRAM Internal/External RAM access using MOVX @ Ri/@DPTR
EXTRAM Operating Mode
0 Internal ERAM (00H-FFH) access using MOVX @ Ri/@DPTR
1 External data memory access
DISRTO Disable/Enable Reset out
DISRTO Operating Mode
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE Operating Mode
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data
memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address
locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and
DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate
value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON
SFR. POF is set to “1” during power up. It can be set and rest under software control
and is not affected by reset.

8 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Table 3b. AUXR1: Auxiliary Register 1

AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
– – – – – – – DPS
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H

Memory Organization MCS-51 devices have a separate address space for Program and Data Memory. Up to
64K bytes each of external Program and Data Memory can be addressed.

Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89C51RC, if EA is connected to VCC, program fetches to addresses 0000H
through 7FFFH are directed to internal memory and fetches to addresses 8000H
through FFFFH are to external memory.

Data Memory The AT89C51RC has internal data memory that is mapped into four separate segments:
the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes special function regis-
ter (SFR) and 256 bytes expanded RAM (ERAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly
addressable only.
4. The 256-byte expanded RAM (ERAM, 00H-FFH) is indirectly accessed by MOVX
instructions, and with the EXTRAM bit cleared.
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. This means they have the same address, but are
physically separate from the SFR space.
When an instruction accesses an internal location above address 7FH, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction. Instructions that use direct addressing access
SFR space. For example:
MOV 0A0H, # data

9
1920B–MICRO–11/02
 accesses the SFR at location 0S0H (which is P2). Instructions that use indirect address-
ing access the Upper 128 bytes of data RAM. For example:
MOV@R0, # data

where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2
(whose address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes
of data RAM are available as stack space.
The 256 bytes of ERAM can be accessed by indirect addressing, with EXTRAM bit
cleared and MOVX instructions. This part of memory is physically located on-chip, logi-
cally occupying the first 256 bytes of external data memory.

Figure 1. Internal and External Data Memory Address

(with EXTRAM = 0)
FF FF FF FFFF
UPPER SPECIAL EXTERNAL
128 BYTES FUNCTION DATA
INTERNAL REGISTER MEMORY
RAM
ERAM 80 80
256 BYTES

LOWER
128 BYTES
INTERNAL
RAM 0100
00 00 0000

With EXTRAM = 0, the ERAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access
to ERAM will not affect ports P0, P2, P3.6 (WR), and P3.7 (RD). For example, with
EXTRAM = 0,
MOVX@R0, # data

where R0 contains 0A0H, accesses the ERAM at address 0A0H rather than external
memory. An access to external data memory locations higher than FFH (i.e. 0100H to
FFFFH) will be performed with the MOVX DPTR instructions in the same way as in the
standard 80C51, i.e., with P0 and P2 as data/address bus, and P3.6 and P3.7 as write
and read timing signals. Refer to Figure 1.
With EXTRAM = 1, MOVX @ Ri and MOVX@DPTR will be similar to the standard
80C51. MOVX@Ri will provide an 8-bit address multiplexed with data on Port 0 and any
output port pins can be used to output higher-order address bits. This is to provide the
external paging capability. MOVX@DPTR will generate a 16-bit address. Port 2 outputs
the high-order 8 address bits (the contents of DP0H), while Port 0 multiplexes the low-
order 8 address bits (the contents of DP0L) with data. MOVX@Ri and MOVX@DPTR
will generate either read or write signals on P3.6 (WR) and P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the ERAM.

10 AT89C51RC
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 AT89C51RC

Hardware Watchdog The WDT is intended as a recovery method in situations where the CPU may be sub-
Timer jected to software upsets. The WDT consists of a 13-bit counter and the WatchDog
Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To
(One-time Enabled enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST regis-
with Reset-out) ter (SFR location 0A6H). When the WDT is enabled, it will increment every machine
cycle while the oscillator is running. The WDT timeout period is dependent on the exter-
nal clock frequency. There is no way to disable the WDT except through reset (either
hardware reset or WDT overflow reset). When WDT overflows, it will drive an output
RESET HIGH pulse at the RST pin.

Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST
register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by
writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter over-
flows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is
enabled, it will increment every machine cycle while the oscillator is running. This means
the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the
user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The
WDT counter cannot be read or written. When WDT overflows, it will generate an output
RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where
TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the time required to prevent a WDT
reset.

WDT During Power- In Power-down mode the oscillator stops, which means the WDT also stops. While in
down and Idle Power-down mode, the user does not need to service the WDT. There are two methods
of exiting Power-down mode: by a hardware reset or via a level-activated external inter-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it normally does whenever the
AT89C51RC is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service for the interrupt used
to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it
is best to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine
whether the WDT continues to count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the
AT89C51RC while in IDLE mode, the user should always set up a timer that will period-
ically exit IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the
count upon exit from IDLE.

UART The UART in the AT89C51RC operates the same way as the UART in the AT89C51
and AT89C52. For further information, see the December 1997 Microcontroller Data
Book, page 2-48, section titled, “Serial Interface”.

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1920B–MICRO–11/02
Timer 0 and 1 Timer 0 and Timer 1 in the AT89C51RC operate the same way as Timer 0 and Timer 1
in the AT89C51 and AT89C52.

Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.
The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload (up or down counting), and
baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 reg-
ister is incremented every machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator frequency.
Table 3. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)

In the Counter function, the register is incremented in response to a 1-to-0 transition at

its corresponding external input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. The new count value appears in the reg-
ister during S3P1 of the cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 tran-
sition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given
level is sampled at least once before it changes, the level should be held for at least one
full machine cycle.

Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit
can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same
operation, but a 1-to-0 transition at external input T2EX also causes the current value in
TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can
generate an interrupt. The capture mode is illustrated in Figure 2.

Auto-Reload (Up or Timer 2 can be programmed to count up or down when configured in its 16-bit auto-
Down Counter) reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will
default to count up. When DCEN is set, Timer 2 can count up or down, depending on the
value of the T2EX pin.

12 AT89C51RC
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 AT89C51RC

Figure 2. Timer in Capture Mode

OSC ÷12
C/T2 = 0

TH2 TL2 TF2

OVERFLOW
CONTROL
TR2
C/T2 = 1

T2 PIN CAPTURE

RCAP2H RCAP2L
TRANSITION
DETECTOR TIMER 2
INTERRUPT
T2EX PIN EXF2

CONTROL
EXEN2

Figure 3 shows Timer 2 automatically counting up when DCEN=0. In this mode, two
options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer
registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in
Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a
16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external
input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can gen-
erate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this
mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also
causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,
TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2
equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a
17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

13
1920B–MICRO–11/02
Figure 3. Timer 2 Auto Reload Mode (DCEN = 0)

OSC 12
C/T2 = 0
TH2 TL2

CONTR OL OVERFLOW
TR2
C/T2 = 1
RELO AD
T2 PIN TIMER 2
RCAP2H RCAP2L INTERRUPT

TF2
TRANSITION
DETECTOR

T2EX PIN EXF2

CONTROL
EXEN2

Table 4. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
– – – – – – T2OE DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
– Not implemented, reserved for future
T2OE Timer 2 Output Enable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter

14 AT89C51RC
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 AT89C51RC

Figure 4. Timer 2 Auto Reload Mode (DCEN = 1)

(DOWN COUNTING RELOAD VALUE) TOGGLE

0FFH 0FFH EXF2

OSC 12 OVERFLOW
C/T2 = 0

TH2 TL2 TF2

CONTROL
TR2
C/T2 = 1 TIMER 2
INTERRUPT
T2 PIN

RCAP2H RCAP2L
COUNT
(UP COUNTING RELOAD VALUE) DIRECTION
1=UP
0=DO

T2EX PIN

Figure 5. Timer 2 in Baud Rate Generator Mode

TIMER 1 OVERFLOW

÷2
"0" "1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1

OSC ÷2
C/T2 = 0
"1" "0"
TH2 TL2
RCLK
Rx
CONTROL CLOCK
TR2
÷ 16
C/T2 = 1
"1" "0"
T2 PIN
TCLK
RCAP2H RCAP2L Tx
CLOCK
TRANSITION ÷ 16
DETECTOR

TIMER 2
T2EX PIN EXF2 INTERRUPT

CONTROL
EXEN2

15
1920B–MICRO–11/02
Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON
(Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is
used for the receiver or transmitter and Timer 1 is used for the other function. Setting
RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure
5.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation.

Mdes 1 and 3 Baud Rates = Timer 2 Overflow Rate-

-----------------------------------------------------------
16

The Timer can be configured for either timer or counter operation. In most applications,
it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer
2 when it is used as a baud rate generator. Normally, as a timer, it increments every
machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator frequency). The baud rate formula is
given below.

Modes 1 and 3 Oscillator Frequency

--------------------------------------- = --------------------------------------------------------------------------------------
Baud Rate 32 x [65536-RCAP2H,RCAP2L)]

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 5. This figure is valid only if RCLK
or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2
but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2
is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode,
TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or write may not be accurate.
The RCAP2 registers may be read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The timer should be turned off
(clear TR2) before accessing the Timer 2 or RCAP2 registers.

16 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Figure 6. Timer 2 in Clock-Out Mode

TL2 TH2
OSC 2
(8-BITS) (8-BITS)

TR2

RCAP2L RCAP2H
C/T2 BIT

P1.0
2
(T2)

T2OE (T2MOD.1)

TRANSITION
DETECTOR

P1.1 TIMER 2
(T2EX) EXF2
INTERRUPT

EXEN2

17
1920B–MICRO–11/02
Programmable Clock A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 6.
Out This pin, besides being a regular I/O pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle
clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be
cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the
timer.
The clock-out frequency depends on the oscillator frequency and the reload value of
Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

Oscillator Frequency
Clock-Out Frequency = ------------------------------------------------------------------------------------
-
4 x [65536-(RCAP2H,RCAP2L)]

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is
similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as
a baud-rate generator and a clock generator simultaneously. Note, however, that the
baud-rate and clock-out frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.

Interrupts The AT89C51RC has a total of six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 7.
Each of these interrupt sources can be individually enabled or disabled by setting or
clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA,
which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. User software should
not write 1s to these bit positions, since they may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register
T2CON. Neither of these flags is cleared by hardware when the service routine is vec-
tored to. In fact, the service routine may have to determine whether it was TF2 or EXF2
that generated the interrupt, and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the
timers overflow. The values are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer
overflows.

18 AT89C51RC
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 AT89C51RC

Table 5. Interrupt Enable (IE) Register

(MSB) (LSB)

EA – ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

EA IE.7 Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or
clearing its enable bit.
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to reserved bits, because they may be used in future AT89
products.

Figure 7. Interrupt Sources

0
INT0 IE0
1

TF0

0
INT1 IE1
1

TF1

TI
RI

TF2
EXF2

19
1920B–MICRO–11/02
Oscillator XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that
Characteristics can be configured for use as an on-chip oscillator, as shown in Figure 8. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 9.
There are no requirements on the duty cycle of the external clock signal, since the input
to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.

Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be termi-
nated by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally
resumes program execution from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM
in this event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when idle mode is terminated by a reset, the instruction
following the one that invokes idle mode should not write to a port pin or to external
memory.

Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes
Power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the Power-down mode is terminated. Exit from Power-
down can be initiated either by a hardware reset or by an enabled external interrupt.
Reset redefines the SFRs but does not change the on-chip RAM. The reset should not
be activated before VCC is restored to its normal operating level and must be held active
long enough to allow the oscillator to restart and stabilize.

Figure 8. Oscillator Connections

C2
XTAL2

C1
XTAL1

GND

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

20 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Figure 9. External Clock Drive Configuration

NC XTAL2

EXTERNAL
OSCILLATOR XTAL1
SIGNAL

GND

Table 6. Status of External Pins During Idle and Power-down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

Program Memory The AT89C51RC has three lock bits that can be left unprogrammed (U) or can be pro-
Lock Bits grammed (P) to obtain the additional features listed in the following table.
Table 7. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program
memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on reset,
and further programming of the Flash memory is
disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also
disabled

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched dur-
ing reset. If the device is powered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The latched value of EA must agree
with the current logic level at that pin in order for the device to function properly.

21
1920B–MICRO–11/02
Programming the The AT89C51RC is shipped with the on-chip Flash memory array ready to be pro-
Flash grammed. The programming interface needs a high-voltage (12-volt) program enable
signal and is compatible with conventional third-party Flash or EPROM programmers.
The AT89C51RC code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89C51RC, the address, data,
and control signals should be set up according to the Flash programming mode table
and Figures 10 and 11. To program the AT89C51RC, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The
byte-write cycle is self-timed and typically takes no more than 50 µs. Repeat
steps 1 through 5, changing the address and data for the entire array or until the
end of the object file is reached.
Chip Erase Sequence: Before the AT89C51RC can be reprogrammed, a Chip Erase
operation needs to be performed. To erase the contents of the AT89C51RC, follow this
sequence:
1. Raise VCC to 6.5V.
2. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
3. Power VCC down and up to 6.5V.
4. Pulse ALE/PROG once (duration of 200 ns - 500 ns) and wait for 150 ms.
5. Power VCC down and up.
Data Polling: The AT89C51RC features Data Polling to indicate the end of a write
cycle. During a write cycle, an attempted read of the last byte written will result in the
complement of the written data on P0.7. Once the write cycle has been completed, true
data is valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the
RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to
indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed
code data can be read back via the address and data lines for verification. The status of
the individual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as
a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7
must be pulled to a logic low. The values returned are as follows:
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H
(200H) = 07H indicates 89C51RC

22 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Programming Every code byte in the Flash array can be programmed by using the appropriate combi-
Interface nation of control signals. The write operation cycle is self-timed and once initiated, will
automatically time itself to completion.
Most major worldwide programming vendors offer support for the Atmel microcontroller
series. Please contact your local programming vendor for the appropriate software
revision.
Table 8. Flash Programming Modes
P3.4 P2.5-0 P1.7-0
ALE/ EA/ P0.7-0
Mode VCC RST PSEN PROG VPP P2.6 P2.7 P3.3 P3.6 P3.7 Data Address
(1)
Write Code Data 5V H L 12 V L H H H H DIN A14 A13-8 A7-0

H/12
Read Code Data 5V H L H L L L H H DOUT A14 A13-8 A7-0
V
(2)
Write Lock Bit 1 6.5V H L 12 V H H H H H X X X X

(2)
Write Lock Bit 2 6.5V H L 12 V H H H L L X X X X

(2)
Write Lock Bit 3 6.5V H L 12 V H L H H L X X X X

P0.2,
Read Lock Bits
5V H L H H H H L H L P0.3, X X X
1, 2, 3
P0.4
(3)
Chip Erase 6.5V H L 12V H L H L L X X X X

Read Atmel ID 5V H L H H L L L L L 1EH X XX 0000 00H

Read Device ID 5V H L H H L L L L L 51H X XX 0001 00H

Read Device ID 5V H L H H L L L L L 07H X XX 0010 00H

Notes: 1. Write Code Data requires a 200 ns PROG pulse.
2. Write Lock Bits requires a 100 µs PROG pulse.
3. Chip Erase requires a 200 ns - 500 ns PROG pulse.
4. RDY/BSY signal is output on P3.0 during programming.

23
1920B–MICRO–11/02
 Figure 10. Programming the Flash Memory
4.5V to 5.5V
AT89C51RC
A0 - A7 VCC
ADDR. P1.0 - P1.7
0000H/7FFFH A8 - A13 PGM
P2.0 - P2.5 P0 DATA
A14* P3.4
P2.6
SEE FLASH P2.7 ALE PROG
PROGRAMMING P3.3
MODES TABLE P3.6
P3.7
XTAL2 EA VIH/VPP

3 - 33 MHz
RDY/
P3.0
BSY

XTAL1 RST VIH

GND PSEN

Figure 11. Verifying the Flash Memory

4.5V to 5.5V
AT89C51RC
A0 - A7 VCC
ADDR. P1.0 - P1.7
0000H/7FFFH A8 - A13 PGM DATA
P2.0 - P2.5 P0 (USE 10K
A14* P3.4 PULL-UPS)
P2.6
SEE FLASH P2.7 ALE
PROGRAMMING P3.3
MODES TABLE P3.6
VIH
P3.7

XTAL 2 EA

3 - 33 MHz

XTAL1 RST VIH

GND PSEN

Note: *Programming address line A14 (P3.4) is not the same as the external memory address
line A14 (P2.6).

24 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Flash Programming and Verification Characteristics

TA = 20°C to 30°C, VCC = 4.5V to 5.5V
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 11.5 12.5 V
IPP Programming Supply Current 10 mA
ICC VCC Supply Current 30 mA
1/tCLCL Oscillator Frequency 3 33 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold after PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold after PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold after PROG 10 µs
tGLGH PROG Width 0.2 1 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float after ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 80 µs

25
1920B–MICRO–11/02
Flash Programming and Verification Waveforms
PROGRAMMING VERIFICATION
P1.0 - P1.7
ADDRESS ADDRESS
P2.0 - P2.5
P3.4 tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tGHDX
tAVGL tGHAX
ALE/PROG
tSHGL tGHSL
tGLGH
VPP LOGIC 1
EA/VPP LOGIC 0

tEHSH tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY) BUSY READY
tWC

Lock Bit Programming

Test Conditions
Setup

Lockbit_1, 2 or 3
Data Setup

100 µs
ALE/PROG

VCC = 6.5V VCC = 4.5V to 5.5V

Wait 10 ms to reload
new lock bit status

26 AT89C51RC
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 AT89C51RC

Parallel Chip Erase Mode

Test Conditions
Test Conditions Setup
Setup

200 ns 200 ns

ALE/PROG

DC DC
P3<0> Erase Erase Erase Erase

VCC = 4.5V to 5.5V

VCC = 6.5V
Wait 10 ms before
reprogramming
10 ms

27
1920B–MICRO–11/02
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C Notice*: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
Storage Temperature ..................................... -65°C to +150°C device. This is a stress rating only and functional
operation of the device at these or any other condi-
Voltage on Any Pin tions beyond those indicated in the operational
with Respect to Ground .....................................-1.0V to +7.0V sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
Maximum Operating Voltage ............................................ 6.6V periods may affect device reliability.

DC Output Current...................................................... 15.0 mA

DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage (Except EA) -0.5 0.2 VCC-0.1 V
VIL1 Input Low-voltage (EA) -0.5 0.2 VCC-0.3 V
VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V
Output Low-voltage(1) (Ports
VOL IOL = 1.6 mA 0.45 V
1,2,3)
Output Low-voltage(1)
VOL1 IOL = 3.2 mA 0.45 V
(Port 0, ALE, PSEN)
IOH = -60 µA, VCC = 5V ± 10% 2.4 V
Output High-voltage
VOH IOH = -25 µA 0.75 VCC V
(Ports 1,2,3, ALE, PSEN)
IOH = -10 µA 0.9 VCC V
IOH = -800 µA, VCC = 5V ± 10% 2.4 V
Output High-voltage
VOH1 IOH = -300 µA 0.75 VCC V
(Port 0 in External Bus Mode)
IOH = -80 µA 0.9 VCC V
Logical 0 Input Current (Ports
IIL VIN = 0.45V -50 µA
1,2,3)
Logical 1 to 0 Transition Current
ITL VIN = 2V, VCC = 5V ± 10% -650 µA
(Ports 1,2,3)
Input Leakage Current (Port 0,
ILI 0.45 < VIN < VCC ±10 µA
EA)
RRST Reset Pull-down Resistor 10 30 kW
CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Active Mode, 12 MHz 25 mA
Power Supply Current
ICC Idle Mode, 12 MHz 6.5 mA
(1)
Power-down Mode VCC = 5.5V 100 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

28 AT89C51RC
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 AT89C51RC

AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100
pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator Variable Oscillator
Symbol Parameter Min Max Min Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tLHLL ALE Pulse Width 127 2tCLCL-40 ns
tAVLL Address Valid to ALE Low 43 tCLCL-25 ns
tLLAX Address Hold after ALE Low 48 tCLCL-25 ns
tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns
tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns
tPLPH PSEN Pulse Width 205 3tCLCL-45 ns
tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-60 ns
tPXIX Input Instruction Hold after PSEN 0 0 ns
tPXIZ Input Instruction Float after PSEN 59 tCLCL-25 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 400 6tCLCL-100 ns
tWLWH WR Pulse Width 400 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns
tRHDX Data Hold after RD 0 0 ns
tRHDZ Data Float after RD 97 2tCLCL-28 ns
tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns
tAVDV Address to Valid Data In 585 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 203 4tCLCL-75 ns
tQVWX Data Valid to WR Transition 23 tCLCL-30 ns
tQVWH Data Valid to WR High 433 7tCLCL-130 ns
tWHQX Data Hold after WR 33 tCLCL-25 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 43 123 tCLCL-25 tCLCL+25 ns

29
1920B–MICRO–11/02
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL tLLIV
tLLPL
PSEN tPLIV
tPXAV
tPLAZ
tPXIZ
tLLAX
tPXIX
PORT 0 A0 - A7 INSTR IN A0 - A7

tAVIV

PORT 2 A8 - A15 A8 - A15

External Data Memory Read Cycle

tLHLL
ALE
tWHLH

PSEN
tLLDV
tRLRH
tLLWL

RD tLLAX
tRLDV tRHDZ
tAVLL
tRLAZ
tRHDX

PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN

tAVWL
tAVDV
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

30 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

External Data Memory Write Cycle

tLHLL
ALE
tWHLH

PSEN
tLLWL tWLWH

WR tLLAX
tAVLL tQVWX tWHQX
tQVWH

PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN

tAVWL

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

External Clock Drive Waveforms

tCHCX
tCHCX tCLCH tCHCL
VCC - 0.5V
0.7 VCC

0.2 VCC - 0.1V

0.45V
tCLCX
tCLCL

External Clock Drive

Symbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tCLCL Clock Period 30 ns
tCHCX High Time 12 ns
tCLCX Low Time 12 ns
tCLCH Rise Time 5 ns
tCHCL Fall Time 5 ns

31
1920B–MICRO–11/02
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc Variable Oscillator
Symbol Parameter Min Max Min Max Units
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL - 133 ns
tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL - 80 ns
tXHDX Input Data Hold after Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL - 133 ns

Shift Register Mode Timing Waveforms

INSTRUCTION 0 1 2 3 4 5 6 7 8
ALE
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF 0 1 2 3 4 5 6 7
tXHDX
OUTPUT DATA tXHDV SET TI
CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID

INPUT DATA SET RI

AC Testing Input/Output Waveforms(1)

VCC - 0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V

Note: 1. AC Inputs during testing are driven at VCC - 0.5V

for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.

Float Waveforms(1)
V LOAD+ 0.1V V OL - 0.1V

V LOAD Timing Reference

Points
V LOAD - 0.1V V OL + 0.1V

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.

32 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
24 4.0V to 5.5V AT89C51RC-24AC 44A Commercial
AT89C51RC-24JC 44J (0°C to 70°C)
AT89C51RC-24PC 40P6
AT89C51RC-24AI 44A Industrial
AT89C51RC-24JI 44J (-40°C to 85°C)
AT89C51RC-24PI 40P6
33 4.5V to 5.5V AT89C51RC-33AC 44A Commercial
AT89C51RC-33JC 44J (0°C to 70°C)
AT89C51RC-33PC 40P6

Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

33
1920B–MICRO–11/02
44A – TQFP

PIN 1
B
PIN 1 IDENTIFIER

e E1 E

D1
D

C 0˚~7˚

A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable E1 9.90 10.00 10.10 Note 2
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45
plastic body size dimensions including mold mismatch.
C 0.09 – 0.20
3. Lead coplanarity is 0.10 mm maximum.
L 0.45 – 0.75
e 0.80 TYP

10/5/2001
TITLE DRAWING NO. REV.
2325 Orchard Parkway
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
R San Jose, CA 95131 44A B
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

34 AT89C51RC
1920B–MICRO–11/02
 AT89C51RC

44J – PLCC

1.14(0.045) X 45˚
1.14(0.045) X 45˚ PIN NO. 1
0.318(0.0125)
IDENTIFIER 0.191(0.0075)

E1 E B1 D2/E2
B

e
A2
D1
A1
D
A

0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion. E1 16.510 – 16.662 Note 2
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 14.986 – 16.002
and E1 include mold mismatch and are measured at the extreme
B 0.660 – 0.813
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533
e 1.270 TYP

10/04/01

TITLE DRAWING NO. REV.

2325 Orchard Parkway
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44J B
R San Jose, CA 95131

35
1920B–MICRO–11/02
40P6 – PDIP

D
PIN
1

E1

SEATING PLANE

A1
L
B
B1
e

COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE

eB A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. B1 1.041 – 1.651
2. Dimensions D and E1 do not include mold Flash or Protrusion. L 3.048 – 3.556
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP

09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual 40P6 B
R San Jose, CA 95131 Inline Package (PDIP)

36 AT89C51RC
1920B–MICRO–11/02
 Atmel Headquarters Atmel Operations
Corporate Headquarters Memory RF/Automotive
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e-mail
[email protected]

Web Site
http://www.atmel.com

© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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1920B–MICRO–11/02 xM
This datasheet has been download from:

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