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0% found this document useful (0 votes)
11 views2 pages

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Uploaded by

jose bryan
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Counter is
port(
clk : in std_logic;
clk_out: out std_logic; -- Reloj de entrada
reset: in std_logic;
count_in: in std_logic;
seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
digit: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end Counter;

architecture Behavioral of Counter is

signal clk_1hz: std_logic := '0';


signal count_divider: UNSIGNED(31 downto 0) := (others => '0');

constant CLK_FREQ : integer := 50000000; -- 50 MHz


constant FREQ_5HZ : integer := 10;
constant DIV_5HZ : UNSIGNED(31 downto 0) := to_unsigned(CLK_FREQ / (2 *
FREQ_5HZ) - 1, 32);
signal div_value : UNSIGNED(31 downto 0) := DIV_5HZ;
signal count_in_last : std_logic := '1'; -- Guarda el estado anterior
de count_in
signal active : integer := 0;

type seg_type is array (0 to 15) of STD_LOGIC_VECTOR(6 downto 0);


constant seg_codes : seg_type := (
"0000001", -- 0 0111111
"1111001", -- 1 0000110
"0010010", -- 2 1011011
"0000110", -- 3 1001111
"1001100", -- 4 1100110
"0100100", -- 5 1101101
"0100000", -- 6 1111101
"0001101", -- 7 0000111
"0000000", -- 8 1111111
"0000100", -- 9 1101111
"0001000", -- A 1110111
"1100000", -- b 1111100
"0110001", -- C 0111001
"1000010", -- d 1011110
"0110000", -- E 1111001
"0111000" -- F
);

signal total_counter: integer := 0;


begin
process(clk, reset)
begin
if reset = '1' then
count_divider <= (others => '0');
clk_1hz <= '0';
elsif rising_edge(clk) then
if count_divider >= div_value then
count_divider <= (others => '0');
clk_1hz <= not clk_1hz;
else
count_divider <= count_divider + 1;
end if;
end if;
end process;

process(clk_1hz, reset)
begin
if reset = '1' then
total_counter <= 0;
count_in_last <= '1';
elsif rising_edge(clk_1hz) then
if count_in_last = '1' and count_in = '0' then -- Detección de flanco
de bajada
total_counter <= total_counter + 1;
if total_counter = 15 then
total_counter <= 0;
end if;
end if;
count_in_last <= count_in; -- Actualiza el estado anterior de count_in
end if;
end process;
seg <= seg_codes(total_counter);
digit <= "11111110";

clk_out <= clk_1hz;


end Behavioral;

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