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Application Brief
Driving BLDC Motors with PWM Generation Mode

Introduction
In gate driver applications used by TI’s brushless-
DC (BLDC) DRV8x portfolio, there are a few
control modes that are typically used to toggle the
output gates for MOSFET switching. These control
modes are: 1x, 3x, 6x, and independent pulse-width
modulation (PWM) mode.
However, a new technology in the DRV8x portfolio,
such as the DRV8311, includes PWM Generation
mode. PWM Generation mode allows the user to turn
on and off MOSFET gate outputs by writing to the
devices registers over Texas Instruments SPI (tSPI).
The benefit of this new control mode is that the control
mode allows for the PWM period, frequency, and duty
cycle to be configured over the serial interface.
As a result, the impact with this control mode is that Figure 1. Multi-Motor Control using tSPI
the user can achieve a more compact system with
robust motor control by sending SPI read/write signals For more information regarding using tSPI in multi-
instead of requiring multiple GPIO inputs from the motor systems, see Reduce Wires for Your Next Multi-
MCU. Motor BLDC Design With tSPI Protocol.

tSPI System Design Benefits PWM Generation Mode

One system level benefit of using PWM Generation With PWM Generation mode, the following
mode with the DRV8311P (the tSPI variant of the commutation methods are possible: trapezoidal,
DRV8311), comes with the elimination of the INHx sinusoidal, and field-oriented control (FOC). These
and INLx pins. BLDC DRV8x devices generally methods can be accomplished using SPI to set
require three INHx pins and three INLx pins to control the Phase Driver Outputs to the correct state. For
the gate driver outputs. As a result, if the user wanted example, the DRV8311P allows the user to write to
to drive multiple motors, six times the number of the PWM_STATE register to turn control the behavior
motors GPIO pins from the MCU is required. of both the high- and low-side MOSFETs for each of
the phases.
By using PWM Generation mode over tSPI, four wires
to communicate over SPI as shown in Figure 1 are Additionally, this control mode allows the user
required. Additionally, tSPI allows random access to to configure the duty cycle of the PWM signals
the DRV8311P devices with a general call address with precise granularity. For example, with a PWM
and the ability to perform read/writes in any order. frequency of 20 kHz, a user can achieve a duty cycle
granularity of 0.2% per bit. To achieve this with the
DRV8311P, calculate the following:

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1. Set the PWM period output by configuring

the PWM_PRD_OUT bits to generate a PWM
frequency using Equation 1.
F
PWMPRD = 0.5 × F SYS (1)
PWM

•
PWMPRD = PWM_PRD_OUT value
•
FSYS = internal system clock frequency
(approximately 20 MHz)
• FPWM = PWM frequency
2. Set the duty cycle for each of the phase outputs
by configuring the PWM_DUTY_OUTx bits using
∆value = 0.01 × PWMPRD × ∆per (2)

• Δvalue = PWM_DUTY_OUTx value

• Δper = duty cycle (%) Figure 2. DRV8311P Measured Duty Cycle at
3. To calculate what level of granularity can be 50.0%
achieved, solve for Δper using Equation 2 which
becomes:
∆
∆per = 0.01 ×value
PWMPRD (3)

For this example, PWMPRD is 500 and Δvalue is set

to 250. By solving for Δper using Equation 3, Δper
becomes 50.0%. If Δvalue increases by one (so that
Δvalue = 251), Δper becomes 50.2%. Therefore, the
granularity of the duty cycle at a PWM frequency of 20
kHz must be 0.2%.

DRV8311P Duty Cycle Step Accuracy

To show the level of granularity mentioned in the
previous section, the input duty cycle given to
DRV8311P started at 50.0% and incremented by Figure 3. DRV8311P Measured Duty Cycle at
0.2% until the input duty cycle reached 51.0%. For 50.2%
this test, the high-side (HS) of phase A was PWM’d
and the low-side (LS) of phase B was turned ON, with As Figure 2 and Figure 3 show, the measured duty
the HS and LS for phase C left off. Table 1 shows the cycle increased by 0.2% as expected.
level of granularity that was observed.
DRV8311H Duty Cycle Step Accuracy
Table 1. DRV8311P Duty Cycle Granularity
Measured To compare the level of accuracy observed by the
Input Duty Target Duty Measured
Duty Cycle tSPI variant of the DRV8311 using PWM Generation
Cycle (%) Step (%) Duty Step (%)
(%)
mode, the same test was conducted using the
50.0 49.78 - - DRV8311H (hardware variant). Again, the high-side
50.2 49.98 0.20 0.20 (HS) of phase A (INHA) was PWM’d and the low-side
50.4 50.18 0.20 0.20 (LS) of phase B (INLB) was pulled HIGH, with the HS
50.6 50.38 0.20 0.20 and LS for phase C was both left LOW Table 2 shows
the duty cycle step granularity for the DRV8311H.
50.8 50.58 0.20 0.20
51.0 50.78 0.20 0.20

Figure 2 and Figure 3 are waveforms that were

captured measuring the duty cycle observed at OUTA
that is seen in the first two rows of Table 1.

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Table 2. DRV8311H Duty Cycle Granularity Conclusion

Measured
Input Duty
Duty Cycle
Target Duty Measured As discussed, PWM Generation mode can be
Cycle (%) Step (%) Duty Step (%) a powerful tool to help reduce the number of
(%)
50.0 50.13 - - unnecessary signals in systems, if the user designs
the PCB and operates the system appropriately. As
50.2 50.35 0.20 0.22
shown by the duty cycle step accuracy data, the PWM
50.4 50.56 0.20 0.21
Generation mode is a robust method that is viable for
50.6 50.76 0.20 0.2 motor control.
50.8 50.93 0.20 0.17
References
Figure 4 and Figure 5 are waveforms that were For additional references, see the following:
captured measuring the duty cycle observed at OUTA
that was seen in the first two rows of Table 2. • Texas Instruments, How to spin 4 motors using
Channel 1 (yellow) captures the input PWM signal DRV8311 with just 5 wires demo video, video.
while channel 2 (blue) captures the measured PWM • Texas Instruments, Reduce Wires for Your Next
signal. Multi-Motor BLDC Design With tSPI Protocol,
application note.
• Texas Instruments, Delay and Dead Time in
Integrated MOSFET Drivers, application note.
• Texas Instruments, DRV8311, product page.
• Texas Instruments, DRV8311 Three-Phase PWM
Motor Driver, data sheet.
• Texas Instruments, DRV8311HEVM, product page.
• Texas Instruments, DRV8311HEVM User's Guide,
user's guide.

Figure 4. DRV8311H Measured Duty Cycle at

50.0%

Figure 5. DRV8311H Measured Duty Cycle at

50.2%

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