Introduction to Verilog

- a hardware description language (HDL)

Dr Alister Hamilton

2-1
 Introduction

 With the allowance of more and more components

on a chip, digital systems have continued to grow
in complexity.
 Technology improvements have advanced the
very large scale integration (VLSI) field. Despite
changes in integration ability, the term VLSI
remains popular.
 Early integrated circuits belonged to small-scale
integration (SSI), medium-scale integration
(MSI), or large-scale integration (LSI) groups
depending on the density of integration.

2-2
 Computer-Aided Design (CAD)

 Steps in modern digital system design:

2-3
 CAD (continued)
 Target technologies that are available:

 Most common: field programmable gate arrays (FPGAs) and

application-specific integrated circuits (ASICs).

2-4
 Hardware Description Languages
(HDLs)
 Many different HDLs used for a variety of purposes
 Some suited to low level design (e.g. ABEL)
 Two popular HDLs—VHDL and Verilog.
 Verilog is an HDL used to describe the behavior and/or
structure of digital systems.
 Verilog can describe a digital system at several
different levels—behavioral, data flow, and structural.
 Verilog leads naturally to a top-down design
methodology.
 Also system-level languages (hardware and software)
e.g. SystemC and System Verilog.

2-5
 Verilog: The Module
 Basic unit of hardware
 Freestanding, cannot contain other module definitions.
 A module may be instantiated within another module.
 Basic mechanism for creating design hierarchy

 Basic module layout

 With Verilog keywords in bold.

module module-name (list-of-ports);

local wire/reg declarations
parallel statements
endmodule

2-6
 A Simple Module
module Continuous (output StatOut, input StatIn);

assign StatOut = ~StatIn; // Continuous assignment

endmodule

synthesis

assign statement creates a static binding between expression on left-

and right-hand sides of the = operator. Commonly used to describe
combinational logic. Constantly active, awaiting events on the input
signal(s) to trigger its execution. Here, such events depend on activity
of external sources applied to module inputs.

Bit-wise logical inversion operation (~) 2-7

 wire and reg
 Local storage and/or connections used within the
module.
 Link together logical elements described by so-
called parallel statements.
 Parallel statements execute concurrently in a manner
similar to digital hardware.
 wire: one category of more general Verilog nets,
which have to be driven continuously by either
 continuous assignment
 output of a primitive gate
 module instantiation (ports are wires by default†)

†See [3] p155 for more on this topic.

8
 wire and reg (continued)
 Left-hand side or target of a continuous assignment
must be a wire.
 Unconnected wires are undriven and assigned the high
impedance value z.

 reg: one category of more general Verilog registers

(the other being integer) which imply storage.
 Able to retain a value in-between being updated by a
sequential assignment.
 Used exclusively inside sequential blocks.

 wire and reg may be declared as a 1-bit object or as

a vector.

9
 Verilog AND-OR-INVERT module
// Note – Comments are written in the same
// style as C++ (block comments use /* */)
// Verilog description of a AND-OR-INVERT gate

module AOI (input A, B, C, D, output F);

wire W1, W2;

assign W1 = A & B; A W1
assign W2 = C & D;
B
assign F = ~( W1 | W2); F
C
endmodule W2
D

Alternatively: assign F = ~( (A & B) | (C & D) );

Bit-wise logical AND (&) and logical OR (|)

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 Verilog 4-bit adder
module add4 ( output [3:0] sum,
output c_out,
input [3:0] a, b,
input c_in);

assign #15 {c_out, sum} = a + b + c_in;

endmodule

Module header defines multi-bit ports a, b and sum. Expression [3:0]

is the bit range of the port. The left hand bit, in this case bit 3, is always
assumed the most significant. The {} operator concatenates c_out and
sum producing a 5-bit result. The #15 denotes a delay of 15 time units
between an input changing and the resulting output change. Addition is
unsigned by default.
11
4-bit adder (symbol)

c_in

a
add4 sum
b

c_out

12
 Design Hierarchy
modT
U1 out1
4
w1
in1 X Y
5 modA
K
F modB G out2
U3 E
U2
in2 M N
modC 8 w2

Block diagram of a module containing instances of other modules.

13
 Verilog description for modT

module modT (input [4:0] in1,

input in2,
output [3:0] out1,
output out2);
wire [7:0] w2;
wire w1;

modA U1 (.X(in1), .Y(w1));

modB U2 (.F(w1), .E(w2), .K(out1), .G(out2));
modC U3 (.M(in2), .N(w2));

endmodule

Explicit association:

module-name instance-name (.port-name (net-name), …);

14
 Verilog Full Adder Example
module FA (output S, Cy, input A, B, Ci);

assign S = A^B^Ci;
assign Cy = (A&B) | (A&Ci) | (B&Ci);

endmodule

A FA
B Cy

Ci
S

Dataflow style of description. Other styles are possible, from primitive

MOS switches through to a high level behavioural description. Bit-wise
Exclusive-OR (^). 15
Verilog 4-bit ripple carry adder
module Add4(output [3:0] Sum, output Co,
input [3:0] Ain, Bin, input Cin);

wire [2:0] Cy;

FA fa0 (.S(Sum[0]), .Cy(Cy[0]), .A(Ain[0]),

.B(Bin[0]), .Ci(Cin));

FA fa1 (.S(Sum[1]), .Cy(Cy[1]), .A(Ain[1]),

.B(Bin[1]), .Ci(Cy[0]));

FA fa2 (.S(Sum[2]), .Cy(Cy[2]), .A(Ain[2]),

.B(Bin[2]), .Ci(Cy[1]));

FA fa3 (.S(Sum[3]), .Cy(Co), .A(Ain[3]),

.B(Bin[3]), .Ci(Cy[2]));

endmodule
16
 4-bit ripple carry adder schematic

Bin[0] Ain[0] Bin[1] Ain[1] Bin[2] Ain[2] Bin[3] Ain[3]

fa0 fa1 fa2 fa3

A FA A FA A FA A FA
B Cy B Cy B Cy B Cy
Cin
Ci S Ci S Ci S Ci S
Cy[0] Cy[1] Cy[2]

Sum[0] Sum[1] Sum[2] Sum[3] Co

17
 4-bit adder test bench

mut: module under test

A Add4
Ain S
initial B Sum
block Bin
C_in Co
Cin C_out

‘!=’
error
‘+’ check_sum

18
Test bench for 4-bit adder
‘timescale 1ns/1ns
module Test_Add4 (); // no ports needed

// input stimulus
reg [3:0] A, B;
reg C_in;

//wire for check_sum and error flag

wire [4:0] check_sum;
wire error;

//output responses
wire [3:0] S;
wire C_out;

integer test; continued …

19
Test bench (continued)

initial // only use in test module – runs only once

begin
{A, B, C_in}= 9’b000000000;
#100 // wait for 100 time units
for(test = 0; test < 512; test = test+1)
begin //apply all input values
{A, B, C_in} = test;
#100;
end
$stop // system command stops simulation
end

continued …
20
Test bench (continued)

// instantiate the module under test

Add4 mut (.Sum(S),.Co(C_out),.Ain(A),.Bin(B),

.Cin(C_in));

// add inputs using built in ‘+’ operator

assign check_sum = A + B + C_in;

//compare with mut output

assign error = (check_sum != {C_out, S} );

endmodule

21
 Verilog types
Nets (connections) Registers (storage)
wire
tri
supply0 reg
supply1 integer
wand real
wor time
tri0 realtime
tri1
triand
trireg
trior

Most commonly used types shown in bold text

22
 supply0 and supply1
 Model power supply connections
 Used to tie input ports to logic 0 or logic 1.

module …

supply0 gnd;
supply1 vdd;
nand g1 (y, a, b, vdd); // tie one input of NAND high

endmodule

23
 reg and integer
 reg can be declared as a 1-bit object or as a
vector of any required size
 i.e size not determined by host machine,
 by default an unsigned quantity.
 may be qualified as signed upon declaration e.g.

reg signed [63:0] sig1; // a 64-bit signed register

wire signed [15:0] sig2; // a 16-bit signed wire

 integer usually takes on the default size of the

host machine i.e. 32 or 64 bits
 i.e. size cannot usually be specified,
 stored as a 2’s complement signed number.

2-24
 Verilog type reg and integer:
example

module longcnt (input clock, reset, output reg [15:0] q);

reg[15:0] t; //flip-flop outputs and inputs

//sequential logic
always @ (posedge clock)
begin
if (reset)
q <= 16’b0;
else
q <= q ^ t;
end

Bit-wise logical exclusive-OR, XOR: (^) continued …

2-25
 Verilog example (continued)

always @ (q) //combinational logic

begin: t_block
integer i; //integer used as loop counter
for (i=0; i<16; i = i + 1)
if (i == 0)
t[i] = 1’b1;
else
t[i] = q[i-1] & t[i-1];
end
endmodule

Naming a block (t_block) in this example allows the use of local

declarations of both regs and integers for use within the begin end pair.

This example implements a synchronous binary ascending counter.

26
 Verilog Logic

Logic value Interpretation

0 Logic 0 or false
1 Logic 1 or true
x Unknown (or don’t care)
z High impedance

At the start of simulation, all regs assume the unknown state x, while all
wires assume the undriven state z. x is also used to represent the don’t
care condition in certain circumstances.

27
 2-input AND module simulation
module valuedemo (output y, input a, b);
and g1(y, a, b);
endmodule

0 50 100 150 200 250 300 350 400 450

time (ns)
High impedance – dashed line
Unknown – filled rectangle 28
 Numeric values in Verilog
 Two types of number: sized and unsized.
 Format of sized number:
<size> ’ <base> <number>
 <size>: a decimal number, specifying number
length in binary bits.
 If omitted, number is decimal format. Size implied by the
variable to which the number is being assigned.
 The <base> can be one of the following:
Binary b or B 4’b0101 // 4-bit binary number
Hexadecimal h or H 12’hefd // 12-bit hex number
Decimal (default) d or D 16’d245 // 16-bit decimal no.
Octal o or O 9’o237 // 9-bit octal number
29
 Primitive gates in Verilog
 Basic logic gates
 and, or, xor, not, nand, nor, xnor, buf
 all have one output, but allow any number of inputs
 Optional delays specifying propagation delay or rise-time
and fall-time may be included.

// AND gate with output rise-time of 10 time units and

// fall time of 20 time units
and # (10, 20) g1 (out, in1, in2);

 Three-state gates
 bufif1, bufif0, notif1, notif0
 all have one input, one control signal input and one tri-
state output.

2-30
 Gate-level Verilog example

‘timescale 1 ns /1 ns

module x_or_s (output y, input a, b);

wire t1, t2, t3, t4;

and #10 g1(t3, t1, a);

and #10 g2(t4, t2, b);
not #10 g3(t1, b);
not #10 g4(t2, a);
or #10 g5(y, t3, t4);

endmodule

Note that gate level delays are inertial i.e. input pulses with a duration shorter or
equal to the gate delay don’t produce a response at the gate output.
2-31
 Verilog operators

Operator type Symbol Operation Operands

Arithmetic * Multiply 2
/ Divide 2
+ Add 2
- Subtract 2
% Modulus 2
** Raise to power 2
Logical ! Logical negation 1
&& Logical AND 2
|| Logical OR 2

continued …
32
 Verilog operators (continued)

Operator type Symbol Operation Operands

Relational > Greater than 2
< Less than 2
>= Greater than or equal 2
<= Less than or equal 2
Equality == Equality 2
!= Inequality 2
=== Case equality 2
!== Case inequality 2

continued …
33
 Verilog operators (continued)
Operator type Symbol Operation Operands
Bitwise ~ Bitwise NOT 1
& Bitwise AND 2
! Bitwise OR 2
^ Bitwise exclusive OR 2
^~ or ~^ Bitwise exclusive NOR 2
Reduction & Reduction AND 1
~& Reduction NAND 1
| Reduction OR 1
~| Reduction NOR 1
^ Reduction EXOR 1
^~ or ~^ Reduction EXNOR 1
continued …
34
 Verilog operators (continued)

Operator type Symbol Operation Operands

Shift >> Shift right 2
<< Shift left 2
>>> Shift right signed 2
<<< Shift left signed 2
Concatenation { } Concatenate Any number
Replication {{}} Replicate Any number
Conditional ?: Conditional 3

35
 Verilog and C/C++ Differences
 Verilog provides reduction operators that operate
on all the bits within a single word.
 Additional ‘case’ equality/inequality operators are
used to handle high impedance (z) and unknown
values (x).
 Curly braces ‘{‘ and ‘}’ used in concatenation and
replication operators instead of normal begin …
end block delimiters in Verilog.

36
 Example continuous assignments

wire [7:0] a, b; // 8-bit wire

wire [3:0] c; // 4-bit wire
wire d; // 1-bit wire

assign c = a[3:0] ^ b[3:0]; // example #1

assign d = c[2] & ~ a[6]; // example #2

assign d = ~| a; // example #3

assign c = d ? a[3:0] : a[7:4]; // example #4

Consider each continuous assignment example separately for the given

wire declarations.
2-37
 Corresponding logic circuits

a[7]
a[3:0] c[3:0]
a[3] c[3] a[6]
c[2]
d a[5]
b[3]
a[2] a[4]
c[2] d
a[6]
b[2] a[3]
a[1]
c[1] Example #2 a[2]

a[1]
b[1]
a[0] a[0]
c[0]

b[0] a[3:0] Mux

a[7:0] Example #3
b[3:0] A
c[3:0]
Example #1 Y
a[7:4]
B

Example #4
a[7:0] d

38
Behavioural Description: Sequential
Block
 always block
 Sequential statements that execute repetitively, usually in
response to trigger mechanism
 Acts like a continuous loop that never terminates
 Used to describe any type of digital hardware
 initial block
 Sequential statements that execute from beginning to end
once only
 Commence at start of simulation at t=0
 Used in test benches to provide test input stimuli
 Does not describe synthesisable hardware
 initial and always are parallel blocks
 A module may contain any number of them

39
initial block clock generator
example

localparam PERIOD = 100; // clock period

reg CLK;

initial
begin
CLK = 1’b0;
forever // an endless loop!
#(PERIOD/2) CLK = ~CLK;
end

2-40
 always sequential block format

always @ (event_expression)
begin
// sequential statement 1
// sequential statement 2
…
end

Other forms:
always @ (input1 or input2 or input3) // or separated list
always @ (input1, input2, input3) // comma separated list
always @ (*) // wildcard event expression

always @ (a) // sequential block with a single

y = a * a; // sequential statement
41
 always sequential blocks
 Assignments within sequential blocks
 Only reg-type objects allowed on the left hand side of a
sequential assignment statement
 Event_expression
 Sequential blocks can be triggered into action by changes
in both regs and/or wires
 Allows behavioural and data flow elements to be mixed
freely within an HDL

42
 Include all variables in
always statements

synthesis

Variables declared within an

always statement hold a
temporary value and do not
always imply wires.
Verilog Basic Syntax
Verilog Basic Syntax (Cont.)
Statements in Verilog
 Blocking and non-blocking
sequential assignments
 Blocking assignment
 Uses the = operator
 Target of assignment updated before the next sequential
statement
 Non-blocking assignment
 Uses the <= operator
 Simulator schedules assignment to take place at next
simulation cycle, usually at end of sequential block
 Subsequent statements are not blocked by the
assignment
 All assignments in sequential block scheduled to take
place at same point in time.

47
 RTL described in Verilog HDL

• Netlist: Circuit description from

connectivity point of view in terms
of cells available in the design
library used in the synthesis process
(e.g., intel, umc, tsmc).
• Netlist is usually described in a
Synthesis textual form.
Use of case statement for
combinational logic

synthesis
Consider the following Verilog Model

combinational circuit:
A B C D Y1 Y2

Verilog HDL
description

Synthesis constraints:
Is speed or area
important for this
design?
 FSM modelling with
Verilog-HDL:
Example: A circuit that could be in either a WRITE
state or READ state. If input SlowROM is received
from the ROM memory, then the circuit goes into a
wait state Delay.
The circuit has inputs Read and Write. While in the
READ state read is set to 1, whereas in WRITE state
write=1, otherwise they are set to zero.

State Diagram Verilog HDL Model

 Behavioral and Structural Verilog
 Any circuit or device can be represented in
multiple forms of abstraction.
 Example:

2-52
 Behavioral and Structural Verilog
(continued)
 3 Model views:
 Behavioral:
 Specifies only the behavior at a higher level of abstraction.
 Does not imply any particular structure or technology.
 Structural:
 Specifies more details.
 Components used and the structure of the interconnection
between the components are clearly specified.
 At a low level of abstraction.
 Dataflow (Register Transfer Language [RTL]):
 Data path and control signals are specified.
 System is described in terms of the data transfer between
registers.
 At an intermediate level of abstraction.

2-53
 Synthesis
 Synthesis is a set of transformations between two
model views (e.g. behavioural to structural):

 Architectural synthesis

 Logic synthesis

 Circuit synthesis

2-54
 Overview of Synthesis Levels
[Rabaey]
Architectural Level Logic Level Circuit Level

state
Behavioral View

0 a
(i: 1..16) :: b
sum = sum*z–1 +
2 1
coeff[i]*In*z–1 c x
3 tp

Architecture Logic Circuit

Synthesis Synthesis Synthesis
Structural View

a
4
mem b
fsm x
c a 2
* 1 c
b 2
D
 Architecture Synthesis
 Identifying hardware resources (e.g., execution
units, memories, busses, controllers, etc.)
 Binding the behavioral operations to resources
 Scheduling the execution time of resources

 Define a structural model for the data path

 interconnection of resources
 Define a logic level model for the control unit
 Summary
 Verilog can be used to model combinational logic
and sequential machines.
 Verilog is a hardware description language.
 Verilog statements execute concurrently.
 Statements within a process execute sequentially.
 Verilog signals model actual signals in hardware.
 Variables may be used for internal computation.

2-57