Indian Institute of Information Technology Senapati Manipur
Indian Institute of Information Technology Senapati Manipur
Vdd
IREF = 50 µA
Iout
I1
I2
M1 + M2 M3
V
- GS
5. Design a PMOS current mirror circuit to produce the current I𝑜𝑢𝑡 = I𝑅𝐸𝐹 /2. Consider that the threshold
voltages and W/L ratios are fixed and same for all the transistors.
6. Obtain the expression for the small signal voltage gain for the high gain differential amplifier given in Fig. 2.
Propose a new design to replace the ideal current sources with MOS current source.
�Part C Two questions: Attempt any one question (7 or 8) and will carry 10-mark
7. A differential amplifier is shown in Fig. 3 is having (W/L)1,2,3 = 4, I𝑆𝑆 = 200 𝜇A, R𝐷 = 5 K, Ω, (V)𝐷𝐷 = 1.8
V.
i. Find out the minimum value of common mode input signal voltage V𝑖𝑐𝑚 to operate all the MOS transistors
in saturation region.
1
Vdd
ID1 ID2
VX VY
M3
Vb M4
Vin1 Vin2
M1 M2
P
ISS
Vdd
RD RD
VX VY
ID1 ID2
Vin1 M1 M2 Vin2
P
ISS
Vb
M3
8. A differential amplifier is given in Fig. 4 operated at a bias current (I𝑆𝑆 ) of 270 𝜇A having (W/L)1,2 = 100,
R𝐷 = 5 KΩ, R𝑆𝑆 = 25 KΩ. Find the differential gain, the common mode gain when the drain resistance have
1% mismatch (Hint: R𝐷1 = R𝐷 , R𝐷2 = R𝐷 +ΔR𝐷 ), and CMRR.
Vdd
RD RD
VX VY
ID1 ID2
Vin1+vicm M1 M2 Vin2+vicm
P
RSS ISS