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    Department of Electronics & Communication Engineering: Academic Year: 2023 - 2024 Assignment - 2

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    Department of Electronics & Communication Engineering: Academic Year: 2023 - 2024 Assignment - 2

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    23ecuos117
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    DE(2)

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    Department of Electronics & Communication Engineering: Academic Year: 2023 - 2024 Assignment - 2

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    23ecuos117

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    of 3

    Department of Electronics & Communication Engineering

    (Faculty of Technology, Dharmsinh Desai University, Nadiad)

    Academic Year : 2023 - 2024

    ASSIGNMENT – 2

    Subject : (IC302) Digital Electronics


    Class : B. Tech. Sem.III (EC/IC)

    Due Date :

    Q.1 Select the most appropriate option.

    (1) Which of the following TTL subfamily is having highest power consumption.
    a) 74S b) 74LS c) 74H d) 74L
    (2) Open collector TTL gate can have outputs as
    a) 0 or 1 b) 0 or floating c) 1 or floating d) all of the above
    (3) Figure of merit of a particular gate is 140 pJ and power dissipation is 10 μW. The
    propagation delay of the gate is microseconds.
    a)14 b)180 c) 1 d) 30
    (4) The purpose of a pull-up resistor is to keep a terminal at a level when it
    would normally be at a level.
    a) LOW, float b) HIGH, float c) clock, float d) pulsed, float
    (5) Digital systems many a times are required to have inputs and(/or) outputs dealing with
    analog signals because,
    a) process becomes less complex.
    b) it provides added accuracy.
    c) all signals available in real world are of the analog nature.
    d) none of above.
    (6) The main advantage of TTL with totem-pole output as compared with other TTL types
    are
    a) Fast switching and low power dissipation
    b) Fast switching and low power dissipation
    c) High noise-margin and low cost
    d) none of above.

    Q.2 Answer in Brief.

    (1) “The wired logic connection is not allowed with totem-pole output circuits” Justify
    true/false with reason.
    (2) Define the terms :Noise margin and Fan-in.
    (3) Discuss, Latch v/s Flip flop.

    Q.3 Do as Directed.

    (1) How many gates have to be connected externally to convert a JK flip flop to operate as
    D flip flop? Of which type? Draw NOR SR Latch.
    (2) (I) From options (A), (B), and (C) shown in Fig. 1, identify a Latch, +ve and –ve edge
    triggered flipflops in the following symbols.
    (II) Answer with one word: How many states a flipflop or a latch can represent? What
    does the state of a flipflop or a latch represent?
    (III) NAND SR Latch is considered to have invalid state when applied with input
    combination
    (A) S = R = 0 (B) S = 0, R = 1 (C) S = 1, R = 0 (D) S = R = 1

    (3) What is meant by high impedance state? Show with neat diagram how it is obtained in
    three state TTL NAND gate. What advantage is offered by this state in circuit designs?
    (4) Let all inputs in the open collector TTL gate be in high state of 3V. (connect external
    RL )
    Determine the voltages in the base, collector and emitter of all transistors.
    Calculate the base current of Q3(output transistor-Pull down network).
    Assume that the minimum hFE of all transistors is 5. What is the maximum current that
    can be tolerated in the collector to ensure saturation of Q3?
    What is the minimum value of RL that can be tolerated to ensure saturation Q3.
    (5) Answer followings with reference to the waveforms given in the Fig. 2 and identify.
    (I) The flipflop/latch based on the relationship between inputs I1 and I2 with the
    output.
    (II) The corresponding input pins on the flipflop/latch.
    (III) The type of triggering followed by the flipflop/latch represented by these
    waveforms.
    (IV) The clock cycle number where the race around condition is apparently
    demonstrated. (each clock cycle is numbered above the waveform of the clock signal)
    (V) What will be the final output if the asynchronous clear input is activated
    continuously from the negative half cycle of the clock cycle number 6 onwards with
    inactive preset?
    (VI) What will be the final output if the asynchronous preset input is activated
    continuously from the negative half cycle of the clock cycle number 6 onwards with
    inactive clear?
    Fig. 2

    (6) Compare the gate level circuit of positive edge triggered and negative edge triggered D
    flip flop circuits.

    Faculty Name: Prof. Vasim A. Vohra ([email protected])


    Prof. Manish K Patel
    Prof. D.K.Rabari

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