Advance Microprocessor

Module I
Evolution of microprocessors, 8086 Microprocessor - Architecture and signals,
Memory organisation, Minimum and maximum mode of operation, Minimum
mode Timing Diagram. Comparison of 8086 and 8088.
What is Microprocessor?
A single chip processor is called microprocessor. It is also called Central
Processing Unit (CPU). It is the brain of a computer system. It is also used in
many electronic devices.
Microprocessor is a semiconductor device consisting of electronic logic circuits
manufactured by techniques such as large scale integration (LSI) or very large
scale integration. It is capable of performing computing functions and
making decisions to change the sequence of program execution. A
computer built with a microprocessor is called micro computer.

Examples
Intel 8086, Intel 80286, Pentium II
A microprocessor in which most instructions operate on n-bit data and its
registers are of n-bit size is said to be a n-bit microprocessor.
Evolution of microprocessors

4-bit Microprocessors
The first microprocessor was introduced in 1971 by Intel Corp. It was named Intel
4004 as it was a 4 bit
processor. It was a processor on a single chip. It could perform simple
arithmetic and logic operations such as addition, subtraction, boolean AND and
boolean OR. Intel introduced the enhanced version of 4004, the 4040.
8-bit Microprocessors

The first 8 bit microprocessor which could perform arithmetic and logic operations
on 8 bit words was
introduced in 1973 again by Intel. This was Intel 8008 and was later followed
by an improved version, Intel 8088.
16-bit Microprocessors

The 8-bit processors were followed by 16 bit processors. They are Intel 8086 and
80286.

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 Advance Microprocessor
32-bit Microprocessors
The 32 bit microprocessors were introduced by several companies but the
most popular one is Intel 80386.
Pentium Series
Instead of 80586, Intel came out with a new processor namely Pentium processor.
Its performance is
closer to RISC performance. Pentium was followed by Pentium Pro CPU.
Pentium Pro allows allow multiple CPUs in a single system in order to achieve
multiprocessing. The MMX extension was added to Pentium Pro and the result
was Pentiuum II. The low cost version of Pentium II is celeron.
The Pentium III provided high performance floating point operations for certain
types of computations by using the SIMD extensions to the instruction set. These
new instructions makes the Pentium III faster than high-end RISC CPUs.
Interestingly Pentium IV could not execute code faster than the Pentium III when
running at the same clock frequency. So Pentium IV had to speed up by
executing at a much higher clock frequency.

8086 Microprocessor
8086 Microprocessor is an enhanced version of 8085Microprocessor that was
designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines
and16 data lines that provides up to 1MB storage. It consists of powerful
instruction set, which provides operations like multiplication and division
easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode.
Maximum mode is suitable for system having multiple processors and
Minimum mode is suitable for system having a single processor.

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 Advance Microprocessor
Features of 8086
 The most prominent features of a 8086 microprocessor are as follows –
20
 It has a 20 bit address bus can access upto 2 memory location
 Support upto 64 KB I/O Ports
 Word size is 16 bits
 40 pin dual in line package
 Address ranges from 00000H to FFFFFH
 Memory is addressable- every byte has a separate address
 It has an instruction queue, which is capable of storing six instruction
bytes from the memory resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers,
internal data bus, and 16-bit external data bus resulting in faster
processing.
 It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz
o 8086-2 → 8MHz
o 8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
 Execute stage executes these instructions.
 It has 256 vectored interrupts.
 It consists of 29,000 transistors.
Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor –
8086 Microprocessor is divided into two functional units, i.e., EU (Execution
Unit) and BIU (Bus Interface Unit).

3
BIU (Bus Interface Unit)
BIU takes care of all data and addresses transfers on the buses for the EU like
sending addresses, fetching instructions from the memory, reading data
from the ports and the memory as well as writing data to the ports and the
memory.
EU has no direction connection with System Buses so this is possible with the
BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets upto 6
bytes of next instructions and stores them in the instruction queue. When
EU executes instructions and is ready for its next instruction, then it
simply reads the instruction from this instruction queue resulting in
increased execution speed.
 Fetching the next instruction while the current instruction executes is called
pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It
holds the addresses of instructions and data in memory, which are used by
the processor to access memory locations. It also contains 1 pointer
 register IP, which holds the address of the next instruction to executed by
the EU.
o CS − It stands for Code Segment. It is used for addressing a
memory location in the code segment of the memory, where the
executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the
program and is accessed in the data segment by an offset address or
the content of other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data
and addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment,
which is used by the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the
next instruction to be executed.
BIU contains a separate adder to perform physical address calculation.
EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data
and then decode and execute those instructions. Its function is to control
operations on data using the instruction decoder & ALU. EU has no direct
connection with system buses as shown in the above figure, it performs
operations over data through BIU.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT
operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status
according to the result stored in the accumulator. It has 9 flags and they are
divided into 2 groups − Conditional Flags and Control Flags. Conditional Flags
It represents the result of the last arithmetic or logical instruction executed.
Following is the list of conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 –
D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The
processor uses this flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e.
when the lower order 8-bits of the result contains even number of 1’s,
then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
  Zero flag − This flag is set to 1 when the result of arithmetic or logical
operation is zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of
the operation is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is
exceeded.
Control Flags
Control flags controls the operations of the execution unit. Following is the list of
control flags −
 Trap flag − It is used for single step control and allows the user to
execute one instruction at a time for debugging. If it is set, then the
program can be run in a single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt
enabled condition and set to 0 for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests
when it is set then string bytes are accessed from the higher memory
address to the lower memory address and vice-a- versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH,
and DL. These registers can be used individually to store 8-bit data and can be
used in pairs to store 16bit data. The valid register pairs are AH and AL, BH
and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and
DX respectively.
 AX register − It is also known as accumulator register. It is used to store
operands for arithmetic operations.
 BX register − It is used as a base register. It is used to store the
starting base address of the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store
the loop counter.
 DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to
the memory location, where a word was most recently stored on the stack.

Register Organization
A register is a very small amount of fast memory that is built in the CPU (or
Processor) in order to speed up the operation. Register is very fast and efficient
than the other memories like RAM, ROM, external memory etc,.
The 8086 microprocessor has a total of fourteen registers that are accessible to
the programmer. All these registers are 16-bit in size. The registers of 8086 are
categorized into 5 different groups.

a) General registers
b) Index registers
c) Segment registers
d) Pointer registers
e) Status Register(Flag register)

Figure: Register groups of 8086 micro-processor

General Registers
All general registers of the 8086 microprocessor can be used for arithmetic and
logic operations. These all general registers can be used as either 8-bit or 16-bit
registers. The general registers are:
AX (Accumulator):
AX is used as 16-bit accumulator. The lower 8-bits of AX are designated to use as AL
and higher 8-bits as AH. AL can be used as an 8-bit accumulator for 8-bit operation.
This Accumulator used in arithmetic, logic and data transfer operations. For
manipulation and division operations, one of the numbers must be placed in AX
or AL.
BX (Base Register):
BX is a 16 bit register, but BL indicates the lower 8-bits of BX and BH
indicates the higher 8-bits of BX. The register BX is used as address register to
form physical address in case of certain addressing modes CX (Count
Register):
The register CX is used default counter in case of string and loop instructions. Count
register can also be
used as a counter in string manipulation and shift/rotate instruction.
DX (Data Register):
DX register is a general purpose register which may be used as an implicit
operand or destination in case of a few instructions. Data register can also be
used as a port number in I/O operations.
Segment Register:
The 8086 architecture uses the concept of segmented memory. 8086 can able to
access a memory capacity of up to 1 megabyte. This 1 megabyte of memory is
divided into 16 logical segments. Each segment contains 64 Kbytes of memory.
This memory segmentation concept will discuss later in this document.
There are four segment registers to access this 1 megabyte of memory. The
segment registers of 8086 are:
CS (Code Segment):
Code segment (CS) is a 16-bit register that is used for addressing memory
location in the code segment of the memory (64Kb), where the executable
program is stored. CS register cannot be changed directly. The CS register
is automatically updated during far jump, far call and far return
instructions.
Stack segment (SS)
Stack Segment (SS) is a 16-bit register that used for addressing stack
segment of the memory (64kb) where stack data is stored. SS register can be
changed directly using POP instruction.
Data segment (DS)
Data Segment (DS) is a 16-bit register that points the data segment of the
memory (64kb) where the program data is stored. DS register can be changed
directly using POP and LDS instructions.
Extra segment (ES):
Extra Segment (ES) is a 16-bit register that also points the data segment of
the memory (64kb) where the program data is stored. ES register can be
changed directly using POP and LES instructions.
 Index Registers
The index registers can be used for arithmetic operations but their use is usually
concerned with the memory addressing modes of the 8086 microprocessor
(indexed, base indexed and relative base indexed addressing modes).
The index registers are particularly useful for string manipulation.
SI (Source Index):
SI is a 16-bit register. Source Index Register is used to point the memory locations in
the data segment.
DI (Destination Index):
DI is a 16-bit register. This is destination index register performs the same function as
SI.
Pointer Registers:
8086 microprocessor contains three pointer registers.
SP (Stack Pointer):
Stack Pointer register points the program stack that means SP stores the base
address of the Stack Segment.
BP (Base Pointer):
Base Pointer register also points the same stack segment. Unlike SP, we can use
BP to access data in the other segments also.
IP (Instruction Pointer):
The Instruction Pointer is a register that holds the address of the next
instruction to be fetched from memory. It contains the offset of the next
word of instruction code instead of its actual address Status Register:
The status register also called as flag register. The 8086 flag register contents indicate
the results of computation in the ALU.
Flag register is 16-bit register with only nine bits that are implemented. Six of
these are status flags. The complete bit configuration of 8086 is shown in the
figure.

SF (Sign Flag): This flag represents sign of the result. 0-Result is Positive
1-Result is Negative
ZF (Zero Flag): ZF is set if the result produced by an instruction is zero.
Otherwise, ZF is reset. PF (Parity Flag): This flag is set to 1, if the
lower byte of the result contains even number of 1’s. 0- Odd parity
1- Even parity
CF (Carry Flag)
This flag is set, when there is a carry out of MSB in case of addition or
borrow in case of subtraction. 0- No Carry/ Barrow
1- Carry/ Barrow
TF (Trap Flag): It is used for single step control and allows the user to execute
one instruction at a time for debugging. If it is set, then the program can be run in
a single step mode.
IF (Interrupt Flag):
If this flag is set, the maskable interrupts are recognized by the CPU, otherwise they
are ignored.
DF (Direction Flag):
This is used by string manipulation instructions.
0- The string is processed beginning from the lowest address to the
highest address, i.e., auto incrementing mode.
1- The string is processed from the highest address towards the lowest
address, i.e., auto incrementing mode.
AC (Auxiliary Carry Flag):
This is set when there is a carry from the lowest nibble (i.e, bit three during
addition), or borrow for the lowest nibble (i.e, bit three, during subtraction).
OF(Over flow Flag):
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to accommodate in a destination register.
8086 Pin Diagram
8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline
Package) chip. Here is the pin diagram of 8086 microprocessor −
 Power supply and frequency signals
Vcc- +5V power supply for the operation of internal circuit
GND – ground for internal circuits
 Clock signal
Clock signal is provided through Pin-19. It provides timing to the
processor for operations. Its frequency is different for different versions,
i.e. 5MHz, 8MHz and 10MHz.
 Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order
byte data and AD8- AD15 carries higher order byte data. During the first
clock cycle, it carries 16-bit address and after that it carries 16-bit data.
During T1 state , address are on the lines and data is available on the data
bus during T2, T3,Tw and T4. Tw is a wait state
 Address/status bus(A19/S6,A18/S5,A17/S4,A16/S3)
During T1 state the four address lines for memory operations. During
I/O operations these lines are low. During T2, T3 and T4 states status
information is available on these lines.
S5: The status of the
interrupt flag S6: is always
low

A17/ A16/S Function

S4 3

0 0 Extra segment
access
0 1 Stack segment
access

1 0 Code segment
access
1 1 Data segment
access

 S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to
 indicate the transfer of data using data bus D8-D15. This signal is low
during the first clock cycle, thereafter it is active. S7: not currently used
 Read
It is available at pin 32 and is used to read signal for Read operation.
 Ready
It is available at pin 32. It is an acknowledgement signal from I/O
devices that data is transferred. It is an active high signal. When it is high,
it indicates that the device is ready to transfer data. When it is low, it
indicates wait state.
 RESET
It is available at pin 21 and is used to restart the execution. It causes the
processor to immediately terminate its present activity. This signal is
active high for the first 4 clock cycles to RESET the microprocessor.
 INTR
It is available at pin 18. It is an interrupt request signal, which is sampled
during the last clock cycle of each instruction to determine the availability
of interrupt request.
 NMI
It stands for non-maskable interrupt and is available at pin 17,indicate
interrupt response at the end of current instruction.
 TEST
This signal is like wait state and is available at pin 23. When this signal
is high, then the processor has to wait for IDLE state, else the execution
continues.
 MN/MX
It stands for Minimum/Maximum and is available at pin 33. It indicates
what mode the processor is to operate in; when it is high, it works in the
minimum mode and vice-versa.
 INTA
It is an interrupt acknowledgement signal and id available at pin 24.
When the microprocessor receives this signal, it acknowledges the
interrupt.
 ALE
It stands for address enable latch and is available at pin 25. This signal
indicates the availability of a valid address on the address/data lines.
 DEN
It stands for Data Enable and is available at pin 26. It is used to indicate
the availability of valid data over address/data lines
 DT/R
 It stands for Data Transmit/Receive signal and is available at pin 27.
When it is high, data is transmitted out and when it is low, data is
received by processor
 M/IO
This signal is used to distinguish between memory and I/O operations.
When it is high, it indicates I/O operation and when it is low indicates
the memory operation.
 WR
It stands for write signal and is available at pin 29. It is used to write the
data into the memory or the output device depending on the status of M/IO
signal.
 HLDA
It stands for Hold Acknowledgement signal and is available at pin 30.
This signal acknowledges the HOLD signal.

 HOLD
This signal indicates to the processor that external devices are
requesting to access the address/data buses. It is available at pin 31.
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These
signals provide the status of instruction queue. Their conditions are
shown in the following table −
QS0 QS1 Status
0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2
These are the status signals that provide the status of operation, which is
used by the Bus Controller 8288 to generate memory & I/O control signals.
These are available at pin 26, 27, and 28. Following is the table showing their
status −
S2 S1 S0 Status
0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive
LOCK
It indicates to another system bus master, not to gain control of the system bus
while LOCK is active Low.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the
CPU to release the system bus. When the signal is received by CPU, then it
sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
Memory Segmentation
Segmentat
ion
It is the process in which the main memory of computer is divided into different
segments and each segment has its own base address.
* Segmentation is used to increase the execution speed of computer system so
that processor can able to fetch and execute the data from memory easily and
fastly.
Segmentation in 8086
The size of address bus of 8086 is 20 and is able to address 1 Mbytes
of physical memory. The compete 1 Mbytes memory can be divided
into 16 segments, each of 64 Kbytes size. Only four segments can be
addressed at a time
Types of Segmentation
Overlapping segment
• A segment starts at a particular address and its maximum size can go up to 64
Kbytes. But if another segment starts along this 64 Kbytes location of the first
segment, the two segments are said to be overlapping segment.
• The area of memory from the start of the second segment to the possible
end of the first segment is called as overlapped segment.
Non Overlapped Segment
• A segment starts at a particular address and its maximum size can go up to 64
Kbytes. But if another segment starts before this 64 Kbytes location of the first
segment, the two segments are said to be Non- overlapping segment.
Advantages of segmentation
The main advantages of the segmented memory scheme are as follows: Allows
the memory capacity to be 1 Mbyte although the actual addresses to be handled
are of 16-bit size Allows the placing of code data and stack portions of the
same program in different parts (segments) of memory, for data and code
protection. Permits a program and/ or its data to be put into different areas of
memory each time program is executed, ie, provision for relocation may be done.
Memory Address Generation
• The BIU has a dedicated adder for determining physical memory addresses.
Physical Address (20 Bits) Adder Segment Register (16 bits) 0 0 0 0 Offset
Value (16 bits)
Logical Address is specified as segment: offset
• Physical address is obtained by shifting the segment address 4 bits to the
left and adding the offset address.
 Physical Memory Organization
● The total memory (1mb) of 8086 is arranged in two banks. An
odd bank and an even bank. Both the banks have equal no. of
locations.
● The odd bank contains odd numbered memory Locations. It is known as
upper bank.
● The even bank contains only even numbered memory. Locations.
It is known as lower bank.
● This arrangement is done in order to speed up the operation Every
memory location has two kinds of address – physical and logical.
● A physical address is the 20-bit value that uniquely identifies
each byte location in the Mega byte memory space.
● These may range from 0 to FFFFF Hex.
● All exchanges between the CPU and memory components use this
physical address
● Programs deal with logical, rather than physical, addresses.
● A logical address consists of a segment base value and an offset value.
Byte data with even address is referred on D15  D8 .D7  D0 and byte
data with odd address is transferred on
The processor provides two enable A0 for selecting of either even or odd or
signals, BHE and banks. both the
FIG
A0 Function
BHE
0 0 Whole word
0 1 Upper byte/ odd address
1 0 Lower byte/even address
1 1 none

General Bus Operation

Basically, all the processor bus cycles consist of at least four clock cycles.
These are referred to as T1, T2, T3, T4.
The 8086 has a combined address and data bus commonly referred as a time
multiplexed address and data bus. The main reason behind multiplexing address
and data over the same pins is the maximum utilization of processor pins and it
facilitates the use of 40 pin standard DIP package.
The address is transmitted by the processor during T1.During T2, T3 and T4,
data is transmitted over these lines.Tw is wait state , is introduced between T3
and T4.
 ALE- is emitted during T1 by the processor or bus controller. Used to separate
address or data or status information.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.

Status bits S3 to S7 are multiplexed with higher order address bits and
the BHE signal. Address is valid during T1 while status bits S3 to S7
are valid during T2 through T4.
General Bus Cycle

Minimum Mode 8086 System

The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to
logic 1
In this mode, all the control signals are given out by the microprocessor chip
itself. There is a single microprocessor in the minimum mode system.
The latches are generally buffered output D-type flip-flops, like, 74LS373 or
8282. They are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086.

Transreceivers are the bidirectional buffers they are required to separate the
valid data from the time multiplexed address/data signal.
They are controlled by two signals, namely, DEN and DT/R. The DEN signal
indicates that the valid data is available on the data bus, while DT/R indicates
the direction of data, i.e. from or to the processor.

Usually, EPROMS are used for monitor storage, while RAMs for users program
storage. A system may contain I/O devices for communication with the
processor as well as some special purpose I/O devices. The clock generator
generates the clock from the crystal oscillator for the system.
The timing diagram can be categorized in two parts, the first is the timing
 diagram for read cycle and the second is the timing diagram for write cycle.

Fig shows the read cycle timing diagram. The read cycle begins in T1 with the
assertion of the address latch enable (ALE) signal and also M/IO signal. During
the negative going edge of this signal, the valid address is latched on the local
bus.
The BHE and A0signals address low, high or both bytes. From Tl to T4,
the M/IO signal indicates a memory or I/O operation.
At T2 the address is removed from the local bus and is sent to the output. The
read (RD) control signal is also activated in T2
The read (RD) signal causes the addressed device to enable its data bus drivers.
After RD goes low, the valid data is available on the data bus.
The addressed device will drive the READY line high, when the processor
returns the read signal to high level, the addressed device will again tristate its
bus drivers.
A write cycle also begins with the assertion of ALE and the emission of
the address. The M/IO signal is again asserted to indicate a memory or I/O
operation. In T2 after sending the address in Tl the processor sends the data to be
written to the addressed location.
The data remains on the bus until middle of T4 state. The WR* becomes
active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide
time for floating).
The BHE and A0 signals are used to select the proper byte or bytes of memory
or I/O word to be read or written. The M/IO, RD and WR signals indicate the
types of data transfer as specified in Table

Read cycle timing diagram

 Maximum Mode 8086 System
In the maximum mode, the 8086 is operated by strapping the
MN/MX pin to ground. In this mode, the processor derives the
status signals S2, S1 and S0.
Another chip called bus controller drivers the control signals using this status
information. In the maximum mode, there may be more than one microprocessor
in the system configuration.
The other components in the system are the same as in the minimum mode system.
The general system organization is as shown in the fig
The basic functions of the bus controller chip IC8288, is to derive control
signals like RD and WR (for memory and I/O devices), DEN, DT/R, ALE, etc.
using the information made available by the processor on the status lines.
The bus controller chip has input lines S2, S1 and S0 and CLK. These inputs to
8288 are driven by the CPU. It derives the outputs ALE, DEN, DT/R, MWTC,
AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially

useful for multiprocessor systems. AEN and IOB are generally grounded. CEN
pin is usually tied to +5V.
The significance of the MCE/PDEN output depends upon the status of the IOB
pin. If IOB is grounded, it acts as master cascade enable to control cascaded
8259A; else it acts as peripheral data enable used in the multiple bus
configurations
INTA pin is used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
IORC, IOWC are I/O read command and I/O write command signals
respectively. These signals enable an IO interface to read or write the data from
or to the addressed port.
The MRDC, MWTC are memory read command and memory write command
signals respectively and may be used as memory read and write signals.
All these command signals instruct the memory to accept or send data from or
to the bus. For both of these write command signals, the advanced signals
namely AIOWC and AMWTC are available. They also serve the same purpose,
but are activated one clock cycle earlier than the IOWC and MWTC signals,
respectively.
 Fig Maximum Mode 8086 System
The maximum mode system timing diagrams are also divided in two portions as
read (input) and write (output) timing diagrams. The address/data and
address/status timings are similar to the minimum mode. ALE is asserted in T1,
just like minimum mode. The only difference lies in the status signals used and
the available control and advanced command signals.

Fig. Memory Read Timing in Maximum Mode

Fig. Memory Write Timing in Maximum Mode

 Comparison between 8086 and 8088
8088 Architecture

8088 Pin Diagram

AD7-AD0(Address/Data bus):-These lines constitute address or data time
multiplexed
A15-A8(Address):-These lines provide address bits A8-A15 in the entire bus cycle.
SS0:-A new SS0 is introduced in 8088 instead of BHE pin in 8086.In
minimum mode, the pin ss0 is equivalent to s0 in the maximum mode.In
maximum mode it is always high
IO/M
This pin is similar to M/IO pin of 8086 , but it offers an 8085 compatible,
memory I?O bus interface

Intel 80186

80186 contain a 16-bit data bus. The internal register structure of

the 80186 is virtually identical to the 8086. The only difference
is that the 80186 contain additional reserved interrupt vectors
and some very powerful built in I/O features. The 80186 and
80188 are often called embedded controllers because of their
application as a controller, not as a microprocessor-based
computer.
Features

 The 80186 contains 16 bit data bus.

 The internal register structure of 80186 is virtually identical to the
8086.
 Enhanced 8086-2 CPU.
 Clock Generator.
 2 Independent DMA Channels.
 Programmable Interrupt Controller.
 3 Programmable 16-bit Timers.
 Programmable Memory and Peripheral Chip-Select Logic.
 Available in 10 MHz and 8 MHz Versions.
 Direct Addressing Capability to 1 Mbyte of Memory and 64
Kbyte I/O.

Architecture

Muhammed Riyas A.M, Asst.Professor,Dept. Of E.C.E,MCET Pathanamthitta

 Advanced Microprocessors
In addition to the BIU and EU, the 80186 family contains a
clock generator, a programmable interrupt controller,
programmable timers, a programmable DMA controller and a
programmable chip selection unit. These enhancements greatly
increase the utility of the 80186 and reduce the number of
peripheral components required to implement a system.

Clock Generator. The internal clock generator replaces the

external 8284A clock generator used with the 8086/8088
microprocessors. This reduces the component count in a
system. The internal clock generator has three pin connections:
X1, X2, and CLKOUT. The X1 (CLKIN) and X2 (OSCOUT)
pins are connected to a crystal that resonates at twice the
operating frequency of the microprocessor. The CLKOUT pin
provides a system clock signal that is one half the crystal
frequency. The CLKOUT pin drives other devices in a system
and provides a timing source to additional microprocessors in the
system.

Programmable Interrupt Controller. The programmable

interrupt controller (PIC) arbitrates the internal and external
interrupts and controls up to two external 8259A PICs. When an
external 8259 is attached, the 80186 microprocessors function as
the master and the 8259 functions as the slave. If the PIC is
operated without the external 8259, it has five interrupt inputs:
INT0–INT3 and NMI.

Timers. The timer section contains three fully programmable l6-

bit timers. Timers 0 and 1 generate waveforms for external use
and are driven by either the master clock of the 80186 or by an
external clock. They are also used to count external events. The
third timer, timer 2, is internal and clocked by the master clock.
The output of timer 2 generates an interrupt after a specified
number of clocks and can provide a clock to the other timers.

Programmable DMA Unit. The programmable DMA unit

contains two DMA channels or four DMA channels in some
models. Each channel can transfer data between memory
locations, between memory and I/O, or between I/O devices.

Programmable Chip Selection Unit. The chip selection is a

built-in programmable memory and I/O decoder. It has six output
lines to select memory, seven lines to select I/O on some models,
and 10 lines that select either memory or I/O on the some other
models.

Power Save/Power Down Feature. The power save feature

allows the system clock to be divided by 4, 8, or 16 to reduce
power consumption. The power-saving feature is started by
software and exited by a hardware event such as an interrupt.
The power down feature stops the clock completely. The power
down mode is entered by execution of an HLT instruction and is
exited by any interrupt.

Refresh Control Unit. The refresh control unit generates the

refresh row address at the interval programmed. The refresh
control unit does not multiplex the address for the DRAM—this
is still the responsibility of the system designer. The refresh
address is provided to the memory system at the end of the
programmed refresh interval, along with the control signal. The
memory system must run a refresh cycle during the active time of
the control signal.
Intel 80286

The 80286 is the first member of the family of advanced

microprocessors with memory management and protection abilities.

Features

 The 80286 microprocessor is an advanced version of the

 8086 microprocessor that is designed for multi user and
multitasking environments.
 The 80286 addresses 16 M Byte of physical memory and
1G Bytes of virtual memory by using its memory-
management system.
 The 80286 is basically an 8086 that is optimized to
execute instructions in fewer clocking periods than the
8086.
 Various versions of 80286 are available that runs on 12.5
MHz , 10 MHz and 8 MHz clock frequencies.
 Like the 80186, the 80286 doesn’t incorporate internal
peripherals; instead it contains a memory management unit
(MMU).
 The 80286 operates in both the real and protected modes
 In the real mode, the 80286 addresses a 1MByte
memory address space and is virtually identical to
8086.
 In the protected mode, the 80286 addresses a 16MByte memory
space.
Architecture
The CPU contain four functional blocks
1. Address Unit (AU)
2. Bus Init (BU)
3. Instruction
Unit (IU)
4.Execution
Unit (EU)

Address Unit: The address unit is responsible for calculating the

physical address of instructions and data that the CPU wants to
access. Also the address lines derived by this unit may be used
to address different peripherals. The physical address computed
by the address unit is handed over to the bus unit (BU) of the
CPU.

Bus Unit: Major function of the bus unit is to fetch instruction

bytes from the memory. Instructions are fetched in advance and
stored in a queue to enable faster execution of the instructions.
The bus unit also contains a bus control module that controls the
prefetcher module. These prefetched instructions are arranged in
a 6-byte instructions queue. The 6- byte prefetch queue
forwards the instructions arranged in it to the instruction
unit(IU).

Instruction Unit: The instruction unit(IU) accepts instructions

from the prefetch queue and an instruction decoder decodes them
one by one. The decoded instructions are latched onto a decoded
instruction queue. The output of the decoding circuit drives a
control circuit in the execution unit.

Execution Unit: The execution unit(EU) is responsible for

executing the instructions received from decoded instruction
queue. The decoded instruction queue sends the data part of the
instruction over the data bus. The EU contains the register bank
used for storing the data as scratch pad, or used as special
purpose registers. The ALU, the heart of the EU, carries out all
the arithmetic and logical operations and sends the results over
the data bus or back to the register bank.

Register Organization of 80286

The 80286 CPU contains almost the same set of registers, as in 8086,
namely
1. Eight 16-bit general purpose registers
2. Four 16-bit segment registers
3. Status and control registers
4. Instruction Pointer

The flag register reflects the results of logical and arithmetic

instructions.

D2, D4, D6, D7 and D11 are called as status flag bits. The bits D8
(TF) and D9 (IF) are used for controlling machine operation and
thus they are called control flags. The additional fields available
in 80286 flag registers are :

1. IOPL - I/O Privilege Field (bits D12 and D13)

2. NT - Nested Task flag (bit D14)

3. PE- Protection Enable (bit D16, is set to select the protected

mode of operation. The 80286 could not return to real mode
without a hardware reset)

4.MP - Monitor Processor Extension (bit D17, is set to indicate

that the arithmetic coprocessor is present in the system)

5.EM - Processor Extension Emulator (bit D18, Is set to cause

a type 7 interrupt for each ESC instruction. We often use this
interrupt to emulate, with software, the function of the
coprocessor. Emulation reduces the system cost, but it often
requires at least 100 times longer to execute the emulated
coprocessor instructions.)

6.TS – Task Switch (bit D19, If TS = 1, a numeric coprocessor

instruction causes a type 7 (coprocessor not available) interrupt.)

Machine Status Word (MSW)

The machine status word consists of four flags – PE, MP, EM and
TS of the four lower order bits D19 to D16 of the upper word of
the flag register. The LMSW and SMSW instructions are
available in the instruction set of 80286 to write and read the
MSW in real address mode.

Real Address Mode

• Act as a fast 8086

• Instruction set is upwardly compatible

• It address only 1 M byte of physical memory using A0-A19.

• Inreal addressing mode of operation of 80286, it just acts as a

fast 8086. The instruction set is upward compatible with that of
8086.

The 80286 addresses only 1Mbytes of physical memory using

A0- A19. The lines A20-A23 are not used by the internal circuit
of 80286 in this mode. In real address mode, while addressing the
physical memory, the 80286 uses BHE along with A0- A19. The
20-bit physical address is again formed in the same way as that in
8086. The contents of segment registers are used as segment base
addresses.

As in 8086, the physical memory is organized in terms of

segments of 64Kbyte maximum size. An exception is generated,
if the segment size limit is exceeded by the instruction or the data.
The overlapping of physical memory segments is allowed to
minimize the memory requirements for a task. The 80286
reserves two fixed areas of physical memory for system
initialization and interrupt vector table. In the real mode the first
1Kbyte of memory starting from address 0000H to 003FFH is
reserved for interrupt vector table.

Also the addresses from FFFF0H to FFFFFH are reserved for

system initialization. The program execution starts from FFFFH
after reset and initialization. The interrupt vector table of 80286
is organized in the same way as that of 8086. Some of the
interrupt types are reserved for exceptions, single-stepping and
processor extension segment overrun, etc. When the 80286 is
reset, it always starts the execution in real address mode.

Fig: Real address mode Address calculation

PROTECTED VIRTUAL ADDRESS MODE (PVAM)

80286 is the first processor to support the concepts of virtual

memory and memory management. The virtual memory does not
exist physically it still appears to be available within the system.
The concept of VM is implemented using Physical memory that
the CPU can directly access and secondary memory that is used
as a storage for data and program, which are stored in secondary
memory initially.
The Segment of the program or data required for actual execution
at that instant, is fetched from the secondary memory into
physical memory. After the execution of this fetched segment,
the next segment required for further execution is again fetched
from the secondary memory, while the results of the executed
segment are stored back into the secondary memory for further
references. This continues till the complete program is executed.

During the execution the partial results of the previously executed

portions are again fetched into the physical memory, if required
for further execution. The procedure of fetching the chosen
program segments or data from the secondary storage into
physical memory is called swapping. The procedure of storing
back the partial results or data back on the secondary storage is
called unswapping. The virtual memory is allotted per task.
The 80286 is able to address 1 G byte (230 bytes) of virtual
memory per task. The complete virtual memory is mapped on to
the 16Mbyte physical memory. If a program larger than 16Mbyte
is stored on the hard disk and is to be executed , if it is fetched in
terms of data or program segments of less than 16Mbyte in size
into the program memory by swapping sequentially as per
sequence of execution.
Whenever the portion of a program is required for execution by
the CPU, it is fetched from the secondary memory and placed in
the physical memory is called swapping in of the program. A
portion of the program or important partial results required for
further execution, may be saved back on secondary storage to
make the PM free for further execution of another required
portion of the program is called swapping out of the executable
program.
80286 uses the 16-bit content of a segment register as a selector
to address a descriptor stored in the physical memory. The
descriptor is a block of contiguous memory locations containing
 information of a segment, like segment base address, segment
limit, segment type, privilege level, segment availability in
physical memory, descriptor type and segment use another task.

Physical address calculation in PVAM

Intel
80386
Feature
 32-bit general and offset registers.
 16-byte prefetch queue.
 Memory Management Unit with a Segmentation Unit and a
Paging Uni.t
 32-bit Address and Data Bus.
 4-Gbyte Physical address space.
 64-Tbyte virtual address space.
 i387 numerical coprocessor with IEEE standard-754-
1985 for floating point arithmetic.
 64K 8-, 16-, or 32-bit ports.
 Implementation of real, protected and virtual 8086 modes.
 The protection mode opeartion provides
paging,virtual addressing,multilevel protection and
multitasking capabilities.
Architecture

O
R
The Internal Architecture of 80386 is divided into 3 sections.
•Central processing unit
•Memory management unit
•Bus interface unit

Central processing unit is further divided into Execution unit

and Instruction unit. Execution unit has 8 General purpose and
8 Special purpose registers which are either used for handling
data or calculating offset addresses. The Instruction unit
decodes the opcode bytes received from the 16-byte instruction
code queue and arranges them in a 3- instruction decoded
instruction queue.After decoding them pass it to the control
section for deriving the necessary control signals.

• The barrel shifter increases the speed of all shift and rotate
operations.

• The multiply / divide logic implements the bit-shift-rotate

algorithms to complete the operations in minimum time.Even 32-
bit multiplications can be executed within one microsecond by
the multiply /divide logic.

•The Memory management unit consists of a Segmentation unit and a

Paging unit.

•Segmentation unit allows the use of two address components,

viz. segment and offset for relocability and sharing of code and
data. Segmentation unit allows segments of size 4Gbytes at max.
The Segmentation unit provides a 4 level protection mechanism
for protecting and isolating the system code and data from those
of the application program.

•The Paging unit organizes the physical memory in terms of

pages of 4kbytes size each. Paging unit works under the control
of the segmentation unit, i.e. each segment is further divided into
pages. The virtual memory is also organizes in terms of segments
and pages by the memory management unit. Paging unit converts
linear addresses into physical addresses. The advantage of paging
scheme is that the complete segment of a task need not be in the
physical memory at any time. Only a few pages of the segments,
which are required currently for the execution need to be
available in the physical memory. Thus the memory requirement
of the task is substantially reduced, relinquishing the available
memory for other tasks. Whenever the other pages of task are
required for execution, they may be fetched from the secondary
storage. The previous page which are executed, need not be
available in the memory, and hence the space occupied by them
may be relinquished for other tasks. Thus paging mechanism
provides an effective technique to manage the physical memory
for multitasking systems.
•The control and attribute PLA checks the privileges at the page
level. Each of the pages maintains the paging information of the
task. The limit and attribute PLA checks segment limits and
attributes at segment level to avoid invalid accesses to code and
data in the memory segments.

•The Bus control unit has a prioritizer to resolve the priority of

the various bus requests. This controls the access of the bus.
The address driver drives the bus enable and address signal A0 –
A31. The pipeline and dynamic bus sizing unit handle the related
control signals.

•The data buffers interface the internal data bus with the system bus.
Intel 80486 Feature
 Improved 80386 CPU (6 extra instructions)
 Hard-wired implementation of frequently used instructions (as in
RISCs)
 A 5 stage instruction pipeline
 An 8K Cache Memory + cache controller (previously a separate
device)
 An on-chip Floating Point coprocessor
 Longer Prefetch Queue (32-bytes as opposed to 16 on the 80386)
  Higher frequency operation
 About a million transistors
 Like the 80386 it uses real, protected and virtual 8086
modes and its Memory Management Unit include a
Segmentation Unit and a Paging Unit.

The Pentium Processors

The Pentium microprocessor signals an improvement to the

architecture found in the 80486 microprocessor. The changes
include an improved cache structure, a wider data bus width, a
faster numeric coprocessor, a dual integer processor, and
branch prediction logic. The cache has been reorganized to form
two caches that are each 8K bytes in size, one for caching data,
and the other for instructions. The data bus width has been
increased from 32 bits to 64 bits. The numeric coprocessor
operates at about five times faster than the 80486 numeric
coprocessor. A dual-integer processor often allows two
instructions per clock. Finally, the branch prediction logic
allows programs that branch to execute more efficiently.
Features of Pentium Processors:
 It is a highly integrated device containing about 1.2 million transistors.
 Wider Data Bus Width: The Pentium processors have a wider
data bus width. The data bus width has been increased from 32-
bit to 64-bit to improve the data transfer rate.
 Faster Floating Point Unit: Faster algorithm provides up to ten
times speed-up for common operations including add, multiply
and load.
 Improved Cache Structure: Pentium processors include
separate code and data caches integrated on-chip to meet
performance goals.
 Dual Integer Processor: Pentium processor has integer
processor. It allows execution of two instructions per clock.
 Branch Prediction Logic: The Pentium uses the technique
called branch prediction to check whether a branch will be
valid or invalid.
 Data Integrity and Error Detection: The Pentium processors
have added significant data integrity and error detection
capability.
 Super Scalar Processor: Processors capable to parallel
instruction execution of multiple instructions are known as super
scalar processors. The Pentium is capable, under special
circumstances of executing two integer or two floating point
instructions simultaneously and thus it support super scalar
architecture.
The Pentium MMX version contained an additional MMX unit
that speeds up multimedia and 3D applications. Processing
multimedia data involved instructions operating on large volumes
of packetized data.

Salient Features Of 80586 (Pentium)

A salient feature of Pentium is its superscalar, super pipelined

architecture. It has two integer pipelines U and V, where each one
is a 4-stage pipeline. This enhances the speed of integer
arithmetic of Pentium to a large extent. Moreover, it has an on-
chip floating-point unit, which has increased the floating-point
performance manifold compared to the floating- point
performances of 80386/486 processors.
Another feature of Pentium is that it contains two separate caches,
viz. data cache and instruction cache. In 80486 there was a single
unified data/instruction cache.
The Intel CPU architectures up to 80486 issues only one
instruction to the execution unit per cycle. This obviously leads to
a comparatively slow process of decoding and execution. For
enhancement of processor performance beyond one instruction
per cycle, the computer architects employ the technique of
multiple instruction issue (MII). Thus a microprocessor which is
capable of issuing more thaw instruction per single processor
cycle will be termed as MII microprocessor. Obvious executing
more than one instruction in a cycle, the microprocessor must
have more than execution channels.

Fig. 5 .1 Pentium CPU Architecture

Pentium II
Pentium II is also a 32-bit processor with 64-bit data bus and
36-bit address bus to address up to 64GB of physical memory
space. It is actually a Pentium pro processor with on-chip MMX
(Multi Media Extension). It is available with maximum internal
ratings of 233 MHz to 450 MHz.
The features of Pentium II processor are;

(i) Supports the INTEL architecture with dynamic execution.

 Integrated primary (L1) 16-kb instruction cache and 16-kb
(ii)
write back data cache.
(iii) Integrated 256kb second level (L2) cache.
(iv) Fully compatible with previous microprocessors.
(v) Supports MMX technology.
(vi) Quick start and Deep sleep modes provide extremely low
power dissipation.
(vii) Integrated math co-processor.
The Pentium III
The Pentium III microprocessor is an improved version of the
Pentium II microprocessor. Even though it is newer than the
Pentium II, it is still based on the Pentium Pro architecture.

The salient architectural features are:

1. P-III CPU has been developed using 0.25 micron technology

and includes over 9.5 million transistors. It has three versions
operating at 450 MHz, 500 MHz and 550 MHz which are
commercially available.
2. P-III incorporates multiple branch prediction algorithms.
3. Seventy new instructions have been added to Pentium III. These
instructions are useful in advanced imaging, speech processing
and multimedia applications.
4. Dual independent bus architecture increases bandwidth.
5. P-III employs dynamic execution technology.
6. A 512Kbyte unified, non-blocking level 2 cache has been used.
7. Eight 64-bit wide Intel MMX registers along with a set of 57
instructions for multimedia applications are available
Pentium IV
The most recent version of the Pentium Pro architecture
microprocessor is the Pentium 4 microprocessor from Intel. The
Pentium 4 was released initially in November 2000 with a speed
of 1.3 GHz. It is currently available in speeds up to 2.0 GHz.
There are two packages available for this integrated
microprocessor, the 423-pin PGA and the 478-pin FC- PGA2.
Both versions use the 1.8 micron technology for fabrication. As
with earlier versions of the Pentium, the Pentium 4 uses a 100-
MHz memory bus speed.

Comparison Between different Processors

Nam Dat Internal Cl Data Addr Max:
e e Reg: oc Width ess Mem
k Line ory
Sp s Spac
eed e
8086 197 16 Bit 2 16 bits 20 1M
4 MHZ Bit B
8028 198 16 Bit 6 16 bits 24 16
6 2 MHZ Bit M
B
8038 198 32 Bit 16 32 bits 32 4
6 5 MHZ Bit GB
8048 198 32 Bit 25 32 bits 32 4
6 9 MHZ Bit GB
Penti 199 32 Bit 60 32 32 4
um 3 MHZ bits, Bit GB
64
bit
bus
Penti 199 32 Bit 233 32 32 64
um 7 MHZ bits, Bit GB
II
64 bit
bus
Peni 199 32 Bit 450 32 32 64
um 9 MHZ bits , Bit GB
III 64
bit
bus
Pentiu 200 32 Bit 1.5 32 32 64
m 0 MHZ bits, Bit GB
IV 64
bit
bus