UNIT V

BIASING AND STABILISATION

FIATHFUL AMPLIFICATION

The process of biasing the strength of a weak signal without any change in its general
shape is known as faithful Amplification.
Factors four achieving faithful Amplification
1. Proper Zero signal collector current
2. Zero signal collector current greater than are equal to maximum collector current
due to signal alone.
3. Minimum proper base emitter voltage at any instant
4. Minimum proper collector –emitter voltage at any instant.

NEED FOR BIAS:

Most of the transistor amplifiers are required to work as linear amplifiers .

An amplifier is said to be linear it its output voltage is a linear function of its
input voltage.
Linear operation of an amplifier may be obtained if the transistor is operated in
the active region. Such a linear operation is ensured when Zero signal operating point is
selected desirably in the middle of the active region and operation is restricted to the
linear region the characteristic curves there by averaging distoration of signal waveform.
The selection of the zero signal operating point may be done by suitable biasing
arrangement that is by applying proper d.c voltage at emitter –base junction and
collector-base junction.

OPERATING POINT:

A study of transistor characteristics shows that the transistor functions most

linearly when it is constrained to operate in it active region to establish an operating point
in this region. It’s necessary to provide appropriate direct potential and currents using
external source.
Once the operating point is established time verifying excursions. Of the input signal
should cause an output signal of same waveform It the output signal is not a faithful
reproduction of the input signal .The operating point is unstatic factory and should be
delocated on the collector characteristics. The selectection suitable operating point is
rital four linear amplification. But ever with the freedom. With choose collector
resistance RC load resistance RL and RB VCC connect operate every where in the active
region transistor ratings limit the range of useful operation .These rating are usually
listed in the manufactures data sheet.
The rating so specified are
1. Maximum collector dissipation PC max

157
 2. Maximum collector voltage VC max
3. Maximum collector current IC max
4. Maximum collector Base voltage ratings VCB max

Active region I =100

ICE max Saturation B

Region
IB=80
A.C load line
Vcc/Rc IB=60
Pc max curve
P2 P1 IB=40
Ic
IB=20

D.C load line IB=0

Cut-off region
Vc Vcc

DC LOAD LINE:

For a given collector characteristics and transistor ratings selection of proper

operating point involves selection of suitable values of RC and VCC
Collector current is given by
IC = f(VCE,IB) ....... 1
On applying kvl to the collector circuit including RC (RL= α).
Appling kvl to the output circuit of C-E configuration.
VCC = ICRC+VCE ....2

IC
=

Since VCC is fixed is also point fixed point. Hence the above equitation can be
simplified as an equation of a straight line and is also known as load line.
y= mn+c
m= 1/ RC n= VCE y= IC =
The load line can be plotted on the output characteristics as shown in figure.

158
 Ic

1. For IC= 0
VCE = VCC Vcc/Rc
2. For VCE = 0
IC = Slope – 1/Rc
D.C load line

Vce
Vcc
Combing these two points by a line is called load line.
Assume d.c load line gives the direct relationship between output voltage and
output current. Q-point is always lies on the d.c load line.
Generally Q-point should be located in the entree of the d.c load line.

IC and VCE are quiescent collector current collector and collector voltage at
the Q-point a.c load line.
If RL α through the Q- point P1 we draw an a.c load line for load resistance R L ||
RC
On application of a time valuing input signal the operating point moves
symmetrically about P1 along the a.c load line .In figure that is the maximum swing of the
input signal about Q-point is approximately 40 µA.
For larger input signal swing say 50 µ A. During –eV excursion exceeding 40 µ A the
collector current becomes zero. That is this Q-point serves satisfactorily if the input
signal swing doesn’t exceed 40 µA. For larger input signal swing a more suitable Q-
point has be selected. In order to avoid cut off during the low-current region of the cycle
the Q-point should be located at a higher current on the d.c load line. This selection is by
trial and error.
VCC= IC RL1 + VEC

IC =

RL1 = RC|| RL
Put VCE = VCC
Put VCE = 0

IC =
Suppose if we select the operating point P2 as a Q-point this permits a maximum
input signal swing of 60µA.without cutoff in the low current region and without non-
linearity in the high current region.

159
DISTORTION DUE TO IMPROPER SELECTION OF OPERATING POINT

1. If operating point is properly selected the output signal is not at all distorted .
2. If the operating point is selected at the upper end of the load line we may observe
that collector voltage and collector current wave form get clipped at the +eV
peaks of the input signal.
3. If the zero signal operating point selected at the lower end of the load line the
output collector current and collector voltage wave forms. Get clipped at the -eV
peaks of the input signal wave form.

LOCATION OF Q-POINT

Q- point is taken well below PC max curve

CAUSES TO SHIFT THE OPERATING POINT

1. Transistor replacement.
2. Thermal variation.

BIASING
The proper flow of zero signal collector current and the maintenance of proper.
Collector emitter voltage during the passage of signal is known as transistor biasing.
Means of achieving operating point stability operating point stability may be achieved in
the following points.

BY USING STABILISATION METHODS.

Use of proper biasing circuit which permits such a variation of base biasing current
IB as to maintain. IC almost constant in spite of variation of ICO, VBE and β.

BY USING COMPENSATION METHODS

Use of compensating elements such as diode, transistor, thermistor etc. These

devices produce compensating voltage and currents and maintain the operating point
stable.
Additional means are adopted to maintain the ambient and the junction temperature
constant. These a.c or thermostat chambers may be used to maintain the ambient or case
temperature constant. Heat sink and air blast may be used to remove heat from the
transistor.

DESIRED FEATURES OF BIASING METHODS.

1. To establish conveniently the operating point in the middle of active region of the
characteristics.

160
 2. To make the operating point independent of transistor parameters.
3. To stabilize the collector current against temperature variation.

STABILISATION

The process of making operating point independent of temperature changes of

variations in transistor parameters is known as stabilization.

NEED FOR STABILISATION

Stabilization of the operating point is necessary due to the following reasons.

1. Temperature dependence of IC
2. Individual variations
3. Thermal runway.

The collector current IC is given by

IC = β IB +(1+ β ) ICBO

ICBO is greatly influenced by the temperature change . A rise of 100c doubles the ICBO
This may be high as 0.2mA for lowpowered Ge transistors. As biasing conditions in such
are generally so set the zero signal IC= 1mA.
the change in IC due to temperature variations cannot be tolerated. This necessitates
stabilizing the operating point i.e to hold IC constant in spite of temperature variations.

INDIVIDUAL VARIATIONS

The value of β and V BE are not exactly the same for any two transistor even
of the same type further V BE it self decreases. When temperature increases when a
transistor is replaced by another of the same type, these variations change the operating
point this necessitates stabilizing the operating point.

THERMAL RUNAWAY

The collector current for a configuration is given by

IC = β IB +(1+ β ) ICBO
The collector leakage current ICBO is strong by dependent on temperature the flow of
collector current produces heat within the transistor. This raises the transistor
temperature and if no stabilization is done, the collector leakage current I CBO also
increases. His clear from the above expression. That if I CBO increases, the collector
current Ic increases by ( β+1 ) I CBO. The increased Ic will raise the temperature of the
transistor which in turn will cause I CBO to increase this effect is cummulative and in a
matters of seconds the collector current may become very large causing terms is for to
burn out.
The self destruction if an unstabilised transistor is known as thermal runway in
order to avoid thermal runway and consequent destruction of transistor, it is very
essential that operating point is stabilized i.e Ic kept constant.

161
 In practice this is done by causing IB to decrease automatically with temperature
increase by circuit modification.

STABILITY FACTOR

It is desirable and necessary to keep Ic constant in spite of variations of I CBO the

extent to which a biasing circuit successful in achieving this goal is measured by stability
factors. It is defined as the rate of change collector current Ic circuit collector leakage
current Ico at constant β and VBE
S= at constant β
S1 = it is defined as rate of change of collector current circuit the change in VBE
S11 = it is defined as the rate of change of collector current circuit the variations in β

GENERAL EXPRESION FOR STABILITY FACTOR S

IC = β IB +(1+ β ) ICBO
Differentiating the above expression
With respect to IC

Ideal value of S is I
S>25 the O>P stabilization is poor

DIFFERENT BIASING METHODS.

1. fixed bias with emitter resistance
2. collector to base bias
3. Self bias or potential divider bias.

162
FIXED BIAS
Vcc

RB Rc

Vi
VCE
VBE

In this circuit the quiescent collector current and base currents are provided by a
single power supply VCC.
Apply KVL to the input circuit we get.
VCC = IB RB + VBE ...... 1

VCC>>VBE
---------------2

Thus with fixed VCC and RB the base bias current IB is also fixed and hence name
fixed bias.

IC = β IB +(1+ β ) ICO
ICO is in µA It is very small
It is neglected.
IC = β I B
Apply KVL to the collector circuit
VCC = IC RC + VCE ....... 3
VCE = VCC – IC RC ........ 4
From equation @ it is obvious that

IC RC can never exceed VCC

in case IC exceeds it signifier that the operating point lies in the saturation
region .Thus the collector current IC is limited due to saturation region.

163
CALCULATION OF OPERATING POINT FOR FIXED BIAS CIRCUIT
1. Calculate the base bias current by using equation IB
2. calculate the collector current by using equation I C = β IB
3.Calculate VCE by using equation VCE = VCC – IC RC

STABILITY FACTOR

S=

IC = β IB +(1+ β ) ICBO
Differentiating the above expression circuit ICBO

Substitute IB = Vcc / RB

S = 1+ β
For example if β = 100 then S = 1+ β = 101
This means that IC as such it has power thermal stability and circuit is
susceptible to thermal runway This type of biasing is seldom used or very rarely.

STABILITY FACTOR S1

IC = β IB +(1+ β ) ICBO
Substitute IB =

IC = β ( ) +(1+ β ) ICBO
Differentiating the expression with respect to VBE

164
STABILITY FACTOR S11
IC = β IB +(1+ β ) ICBO
IB =
Differentiating circuit β

IC = β +(1+ β ) ICBO

= + ICBO

S11 = + ICO

= + ICO
By inspection of the above expressions shows that stabilization against V BE and
β is improved by using a high value of base resistor RB.
Figure shows a Si transistor with β = 100 are biased by a base resistor method.
Draw the d.c load line and determine the operating point. Vcc=6v

530K RB Rc
2K

Vi IB
VCE
IB = VBE

= = 0.011mA

= IC = β IB
100 x 0.011 = 100 x = 1.1
VCE = VCC – IC RC
6- 1.1 x 2x 103

Operating point (IC , VCE )

VCC = IC RC +VCE

165
 IC = 0
VCE = VC0 = 6v VCE = 0

IC = = 3 mA

Advantages: Simple circuit it requires single power supply & single resistor.
Disadvantages: - 1. No feed back
2. On replacing of transistor β changes and since I BE is fixed collector current
Ic : βIb changes. This change causes the shift of the operating point.

BIAS COMPENSATION

The collector to base bias and self bias circuits are used to limit the variation in
the operating collector current Ic caused by variation I CO , VBE and β. These circuits are
example of feed back amplifiers, where it is found that a consequence of feed back is to
reduce drastically the amplification of the signal. If this loss in signal gain is intolerable
in a particular application it is often possible to use compensating techniques to reduce
the drift of the operating point. Very often both stabilization and compensation
techniques are used to provide maximum bias and thermal stabilization.

Compensation can be done by the use of certain temperature – sensitive devices

like diodes, thermistors etc.

DIFFERENT METHODS OF COMPENSATION TECHNIQUIES

1. Bias compensation by diode

2. Bias compensation by thermistors
3. Sensistor compensation .

Vcc

R1 Rc
BAIS COMPENSATION BY DIODE

1.DIODE COMPENSATION FOR VBE

R2
RE VOUT
Vin

VD
Rd 166
VDD
 A diode may be used as compensation element for variation in V BE or ICBO in
silicon transistor change of VBE with temperature contributes sufficiently to the change in
Ic while change ICBO is less effective. In germanium transistor, on the other hand change
of ICBO with temperature contributes more towards change in Ic.

The above fig gives the circuit of self biased C E amplifier with diode
compensation the diode is kept biased in the forward direction by the source V DD and
resistance RD . The compensating diode ‘D’ use the same material and same fabrication
techniques as the transistor. Hence the voltage V D across diode D has exactly the same
temperature coefficient as the base –to- emitter voltage VBE of the transistor (-2.5mv/oe)

Vcc

EQUIVALENT CIRCUIT Rc

Rb

Vb
RE

VD
Rd 167
VDD
Apply KVL to the input circuit

Vb – VBE + V d = Ib Re + Ib Rb + IC Re
= (Ic +Ib) Re + Ib Rb
Ib (Rb+Re) + Ic Re. (1)

IC = β IB +(1+ β ) ICBO..........(2)
.
IB =
Substitute equation (2) into equation (1) fields
Vb – VBE +Vd = IC Re + (Rb +Re) ( )

β (Vb – VBE +Vd) = β IC Re + β (Vb – VBE +Vd) (IC -(1+ β ) ICBO )

IC [ β Re + (Rb +Re) ] = β (Vb – VBE +Vd)+ -(1+ β ) ICBO(Rb +Re)

IC ............ (3)

Both VD and VBE vary by similar amounts hence the term (V BE-VD) in equation (3)
remains almost constant in spite of temperature variation. Hence from the above
expression we conclude that as the temperature varies, the collector current I C remains
almost constant in spite of the variation in VBE.

DIODE COMPENSATION FOR ICO: Vcc

In germanium diode, changes in ICO with temperature play the major role in the
collector current stability. The diode compensation circuit shown in fig offers
stabilization against variations in ICO, and is ; useful for stabilizing germanium transistor.
I
R1 Rc

IB
VCE

Io
VBE
168
 If the diode the transistor are of the same type and material, the reverse saturation
current ID of the diode will increase with temperature at the same rate as the transistor
collector saturation current Ico from fig current through resistor RI is given by

IC = = constant ....(1)

Since the diode D is reverse biased by VBE which is equals to 0.2V for germanium
device it follows that the current through D is Io. The base current IB is given by.

IB = I- Io..........(2)

IC = β IB +(1+ β ) ICBO..........(3)

Substitute equation (2) into equation (3)

IC = β (I-IO )+(1+ β ) ICBO.

If β >> I

IC = β(ICO –IO)+βI

If IO of D and Ico of Q track each other over the desired temperature range, then Ic
remains essentially constant.
THERMISTOR COMPENSATION

Thermistor is a temperature sensitive resistive element having –ev temperature

coefficient of resistance, its resistance decreases with increase of temperature T. As T
raises RT decreases and the current fed through R T into RE increases, the voltage drop
across RE increases tends to produce reverse bias as the emitter junction I E. This reverse
bias causes the net forward bias provided by R1 & R2 to decrease the collector current Ic
to reduce.

169
 Thus the thermistor tends to compensate or cancel the increases in Ic due to raise
the temperature. Vcc

R1 RC R

Vin

R2
RE

Instead of a thermistor, it is possible to use of temperature sensitive resistor with a

+ev temperature coefficient such as a metal or the Sensistor. The Sensistor has a
temperature coefficient resistance which is + 0.7% / OC . A heavily doped diode
semiconductor can exhibits a +ev temperature coefficient of resistance for under these
conditions the material acquires metallic prosperities and the resistance decrease because
of their decrease of carrier mobility with temperature. In the above circuit temperature
compensation may be obtained by placing a Sensistor either in parallel with R 1 or in
parallel with Re.

Vcc
2. COLLECTOR – BASE BIAS
Ib + Ic

RB Rc
Ib

VCE

VBE

170
 This bias is also called as feed back bias. The resistor provides feed back. So it
known as feed back bias.

Apply KVL in the output circuit

VCC =(Ib + IC ) Rc+VCE ...........(1)

Ib is in μA : Ib RC neglected

VCC = IC Rc+VCE

IC = ........................(2)

Apply KVL in the input loop.

VCC =( IC + Ib) Rc + Ib Rb +VBE ........(3)

Ib ( Rb +Rc ) VCC - VBE .- IC.Rc

Ib = VCC -- VBE .-- IC.Rc //( Rb +Rc ) ........(4)

S= .............................(5)

= ...............(6)

171
 S= .....................(7)

This value of S is smaller than 1+β that is there is some improvement in

stability.

Improvement in stability is explained as follows if the temperature increases

collector leakage current increase as soon as Ic increases V CE decreases due to greater
voltage drop across RC as a result VCB decreases that is voltage drop across RB decreases.
Hence the base current Ib decreases. Smaller Ib tends to decrease the collector to its
original value.

STABILITY S1

IC = +(1+ β ) ICBO.. β IB........(8)

Substitute equation (4) into equation (9)

= .+(1+ β ) ICBO...........(9)

IC = (IC.Rc )
Differentiate equation (5) circuit VBE

S1 =

IC ( )

172
 =0

STABILITY FACTOR S11

differentiate equation (9) W.R.T β

= - = .+ ICBO+. β ICBO

= - [ + ] + ICBO

= -

= ( )= + ICBO

( =

S11 =

Disadvantages:

The base bias resistor Rb is connected to the collector. As a consequence an a.c

signal at the output will be feed back out of phase with the input. This type of feed back
is called –ev feed back. If effectively reduces input voltage there by reducing the output
voltage.

173
Collector to base bias with emitter resistance:

Vcc

RB Rc
Ib

VCE
VBE

Re
Apply KVL to the output circuit

VCC =( Ib + IC) Rc + VBE ........(1)

: Ib is in μA : Ib RC neglected

ICC = ................(1)

Apply KVL to the circuit

VCC = Ib Rb + IC Rc + Ib IC +Ie Re + VBE

= VBE + Ib Rb + (Ib IC ) Rc + Ie Re

= Ib Rb + (Ib IC ) Rc + (Ib IC ) Re = VCC - VBE

= Ib [Rb +RC +Re] = VCC - VBE -IC(RC + Re)

Ib = VCC – VBE – IC (RC + Re) / Rb + RC + Re.

Different above equation circuit IC

= S=

174
 IC = +(1+ β ) ICBO.. β IB

β = .+(1+ β ) ICBO

= + ICBO

]+ ICBO

S1=

S11 = =

3 SELF BIAS OR VOLTAGE DIVIDERVcc

BIAS OR POTENTIAL:

R1 Rc

Vin

R2
RE

175
 R1 and R2 provides necessary bias and RE provides stabilization.

The voltage divider network provides the necessary bias and the emitter resistance
provides stabilization. If Ic increases due to increase in temperature. The voltage drop
across Re increases. This causes the decrease of VBE leading to a decrease of Ib.
decrease in Ib tends to reduces the collector current Ic to its original value.

The equivalent circuit for the above circuit

Vcc

Rc

RB

VB RE

Apply KVL in the input loop in figure (b)

Vb = Ib Rb +Ie Re + VBE .............(1)

= Ib Rb + (Ib IC )Re + VBE

= Ib Rb + Ib Re + IC Re +VBE = Vb

= Ib (Rb + Re ) = Vb -VBE - IC Re

differentiate the expression circuit IC

176
 =

S =

= .................. (2)

In general Rb/Re is nearly small.

Re must be very much greater than Rb in order to get S< 10.

IC = +(1+ β ) ICBO..

β IB = IC = +(1+ β ) ICBO..

IB =

Substitute Ib in (1)

Ib (Rb + Re ) Vb -VBE - IC Re

IC = - (1+ β ) ICBO

= Vb -VBE - IC Re

177
 = = -1- Re

= -1

= =

differentiate (4) circuit β

(Rb + Re ) +

= Re

- +

= Re

= -[ +Re] = = (IC - ICBO..)

= -[ ] = = (IC - ICBO..)

= =

= =

178
 [ ]

= - +

=- Re

-[ +Re] = = (IC - ICBO..)

= =

= =

THERMAL STABILITY

Junction temperature (Jc) rises due to raise in ambient temperature. Self heating
caused by power dissipation at Ic.

Proper designed layout and use of heat sinks reduces the junction temperature. The
maximum permissible temperature Ic for Ge transistor lies in between 65 OC to 100OC and
for Si transistor it is 150 OC to 200 OC.
The self destruction of a transistor due to raised in temperature is called thermal runway.

THERMAL RESISTANCE

179
 It is found experimentally that the steady state temperature raise at the collector
junction is proportional to the power dissipated at the junction. Mathematically it can be
represented as

∆ T = Te –Tj % Po

We define a proportionality constant called θ then

∆ T = TC –TJ = θ Po

This θ is called as thermal resistance and its units is P OC / watt

Tc represents collector junction temperature unit :- OC.

Tj represents ambient temperature units OC

PD – average power dissipated at the collector junction.

θ depends on the size of the transistor smaller the size higher is the value of the θ .

For high power transistor with efficient heat sink θ may vary from 0.2 OC /W for low
power transistor operating in air θ varies unto 1000 OC/W .

3. Conversion and radiation of heat.

4. nature of cooling.

Thermal connection of the transistor to the metal chases.

OPERATING POINT CONSIDER ATIONS

300w
A

Q1
500w
100w

Q
Q2

B
VCC/2 VCC VCE

180
 Figure shows three constant power hyperbolas and a d.c load line tangent to one
of them. The point of tangency bisects the load line, consider a point Q 1, above the point
of tangency Q if now the collector current increases the result is Q lower collector
dissipation consider the point Q2 below the point of tangency Q if Now collector current
increases the result is the higher collector dissipation. We can conclude that V CE
The Q2 lies in the same region. Where an increase in collector current results in decrease

power dissipation if V< the self heating results causing more power dissipation.
From the above study it is clear that in order to avoid thermal runway the transistor

should be biased such that V CE < . However in practice in many causes it is not
possible to satisfy this conditions.

CONDITIONS FOR AVOIDING THERMAL RUNWAY

Thermal runway may be avoided by making the rate of release of heat at the
collector junction less than the rate of heat dissipation.

< ..............(1)

∆ T = θ PD TC –TJ .....................(2)

Differentiating equation (2) circuit TC

= +1

= ........................(3)
Comparing equations (1) and (3)

<
This is the necessary sufficient conditions to avoid thermal runway

If thermal conductivity is more than the rate of power dissipation circuit

temperature thermal runway is prevented .
This can be justified as follows

181
Comparing the heat from the transistor junction into the surroundings as quickly as it is
generated. As long as the heat is radiated away the junction thermal runway is prevented.

>

In low power transistor thermal runway can be prevented by careful selection of the Q
point. The power generated collector junction under no signal condition is given by

Pc = ICQ VCEQ – (1)

Apply KVL in the output loop of CE

VCE=VCC-IC (RC+Re) – (2)

Substitute equation(2) in equation (1)

VCC ICQ represents the d.c power supplied by the d.c source VCC.
A part of this power is consumed as power dissipated in resistor RC & RE .
Dissipated power PD = JC2Q(RC+Re) ...(4)

The necessary and sufficient condition to avoid thermal runway is

<

>

= > . .

= > . S O.O7 ICO

Differentiate equation (3) circuit ICQ

182
 = VCC-2 ICQ (RC+Re)

= VCC-2 ICQ (RC+Re)

= VCC-2 ICQ
= > (VCC-2 ICQ ) S O.O7 ICO

VCEQ < .

For this inequality to be satisfies is requires that V CC – 2VCEQ is +ev so that

VCEQ < .

FET BIASING

There are more varieties of FETs then there are of bipolar transistor. They are
JFET and MOSFET (Depletion and enhancement modes). In each of these categories.
We have n- channel and p channel devices. However, we have only two types of FETs as
for as modeling is concerned.

JFET and depletion MOSFET are depletion more devices and they are represented by one
method. The second model deals with enhancement mode ‘MOSFET ‘s ‘

Depletion mode devices are biased to operate in the saturation region where the
signal gain is large.

For operation of the devices in the saturation region the conditions to be satisfied
is given by
VDS>> VGS – Vp for JFET or depletion type MOSFET

183
VDS >> VGS – VT for MOSFET [Enhancement]
In the saturation region ID is independent of VDS is given by

ID = IDSS - JFET

ID = k (VGS-VT) 2 → MOSFET

In this region rd = VT is thresh old voltage

Types of biasing circuits

1. Fixed bias
2. Self bias
3. Voltage divider bias

1. FIXED BIAS ARRANGEMENT (JFET)

VDD= 16v -VDD

RD= 2K RD

ID ID
RG= 1M RG

VDS VDS
1.5v VGG VGG

This biasing method is called fixed bias because gate to source voltage is fixed by
the constant voltage applied across these terminals. The basing supply is –ev for n -
channel
Device IQ = 0 => VGS =NVchannel
GG P channel
Apply KVL to the output loop.
VDD-VDS = IDRD

ID = ...(1) n channel

ID = ..........(2) P channel
equation (1) and (2) are the equations of the d.c load line for n channel and p channel
JFET

184
ID =

VDS = 0 => ID = VDD/RD

ID = 0 => VDD =VDS

Combining these two points by a straight line is called load line. This line intersects the

VDS axis at VDD and ID at .

VDD/RD VGS= 0 v

VGS= -0.5v

Q VGS= -1.5v
3.9v
v V = -3 v
GS

8 VDD

ID = = 8mA

VDS = VDD = 16v

Q points is the intersection of load line with the characteristic curve for VGS = -1.5V

Q point is (8V1 3.9 mA)

The Q point can also be determined by using square law characteristics.

For JFET IDSS = 10mA VP = -4V for VGS = 1.5V

ID = IDSS

= 3.9 mA

VDS = VDD – IDRD = 8.2v

VDS >>| VP| - |VGS|

8.2 >> 2.5 hence law of square law is justified.

185
SELF BIAS ARRANGEMENT:
VDD =+15v
ID
RD = 1.5K 10mA
Bias line
ID (-3v, 5mA)

VDS
(-1.8v, 3mA) Q 3

RS = 600
VGS 2
Q-point determination

This bias arrangement requires only singles supply voltage. This method is called
self – bias because the voltage drop across RS due of flow of quiescent current
determines the Q value of VGS. The current ID following through Rs generates Q voltages
drop IDRS at the source terminal circuit ground.

For n- channel FET source is +ev circuits the gate since the gate is grounded. The
gate is –ev by IDRS volts circuit the source as required by an n- channel FET, V GS = TDRS
is called the bias line . The Quiescent value of I D in the self bias arrangement can be
determined graphically by plotting the bias line on the same set of axes with the transfer
characteristics as shown in fig.

VGS = - IDRS
VGS = 0 , RD = 0
VGS = -3V, IP = 5mA =

Thus the two points for bias line ae (0,0) (-3v, 5mA). The Q – point is given by the
intersection of the bias line and the transfer characteristic.

From the graph

VGS = -1.8V ID = 3mA
VDS = VDD – ID (RD + RS))
= 8.7V
The co-ordinates of the Q – point can also be obtained by using the algebraic method for
JFET
IDSS = 10mA VP = -4v

ID = IDSS -

186
 = -

VGS = -600 ID

ID = 14 .77 / 3mA

14- 77mA is more than IDSS (10mA) so it cannot be accepted hence ID = 3mA
VGS = -600 X 3X10-3
= -1.8v

These values agree with those obtained graphically.

VOLTAGE DIVIDER BIAS:

VDD

RD
R1
ID

VG
R2 RS

An n- channel JFET with voltage divider bias arrangement as shown in fig.

VG – potential across R2 makes the gate +ev circuit ground V RS makes the source terminal
+ ev circuit ground VS is always larger than VG leading to Q – ev VGS.

From the circuit

VG = VGS + IDRS
VGS = VG – IDRS – (1)

Practically no gate current flows

VG = R2

VGS = VDD -ID RS

187
The sources voltage VS = VG – VGS
And the drain current
ID = =

Graphical Analysis:
IDSS

(VGS, ID)

VG / RS

-VGS VP VGS

In the JFET with voltage divider bias

VG = IDRS = O

For ID = O VGS = VG – VS = VG

ID = O and VGS = Vp. One point on the load line

For VGS = O ID =

Second point (0, )

The intersection of the load line and the transfer characteristics gives the Q – point.

Depletion of MOSFET
VDD of JFET and depletion type MOSFET are similar. The
The transfer characteristics
analysis of biasing techniques in the same if JFETs is replaced by a depletion type
MOSFET. RD C
Vo

RG
C in
Vin S

188
DC equivalent circuit
Feedback biasing
 The resistor Rg brings a large voltage to switch of the MOSFET ‘ON’ since I G =
O VRG = O the D.C equivalent Circuit is shown in fig. As a result VD, VG and
VDS = VGS
For the output loop VDS = VDD – IDRD = VGS . The result is an equation of straight line
Let ID = O VGS = VDD and VGS = O

ID =
The first of the straight line is given by ID = O and VGS = VDD
The second point VGS = O ID= Join
These two points the resulting straight line intersects the device characteristic at Q –
point.
ID
VDD/RS

BIASING OF MOSFET:
ID(Q) Q Point

The source of self bias arrangement cannot be used in case of enhancement

VGS (Q) VDD
MOSFET because the voltage drop across Rs is in such a direction as to reverse bias the
gate where as forward bias at the gate is needed. In this circuit V GS = VDS. Since no
current flows through RG however, far ensuring linearly in device operation as for getting
max output voltage it may become necessary to keep VGS = VDS.
Then the circuits modified by adding a resistor R1 b/w gate and source.
Biasing against device variation
Diagram
The max and min values of IDSS and Vp and room temperature are usually given
by FET manufactures. They also supplied data to correct these quantities for temperature
variations the transfer characteristics for a given time of n- channel FET may be seen in
fig. Where the top and bottom curves are for extreme values of temp and device
variation.

189
 It is necessary to bias the device at a current which does not drift outside of I D = Ia
and ID = IB. Then the bias line VGS = IDRS must intersect the transfer characteristics and
the slope of the bias line is determined by source resistance Rs. For any transfer
characteristic b/w the two extremes indicated, the current It is such that IA < IB is desired.
This bias line satisfies the equation.
VGS = VGG – IDRS
Such a bias relationship may obtained by adding a fixed bias to the gate in
addition to the source self bias.

SELF BIASED METHOD OR POTENTIAL DIVIDER METHOD OR EMITTER

BIAS METHOD:

Vcc

R1 Rc

VCE

Vc Vb VBE
R2
Re

Figure gives the CE Amplifier using self bias or emitter bias. This biasing method
is most popularly used because it produces excellent operating point stability. The D C
component of current through the resistor RC causes a D C voltage drop Ve in the polarity
as shown in the fig. This voltage drop causes a reverse bias at the base relative circuit to
emitter. The net forward bias at the emitter junction is equal to V b – Ve , R1 R2
combination across the VCC supply produces a required D C voltage at the base junction.

STABILIZATION ACTION OF SELF BIAS CIRCUIT

Any rise in temperature causes rise in ICBO and hence increase in I. This increased
current through Rc causes increased DC voltage of across of Ic and hence results in
reduced net emitter to base bias. This reduction in base bias causes reduced in base
current Ib and hence reduced in collector current Ic. This reduction in Ic tends to cancel
the rise in Ic as caused by raise in temperature operating point stability is thus improved.

ANALYSIS

190
Apply KVL to the collector circuit

VCC = IC RC + VCE + Ie Re

= IC RC + VCE + IC RC + Ib Re

= IC (RC + Re ) + VCE
I b Re is very less than Ic Re

: neglected Ic Re in the above expression

VCE = VCC -IC (RC + Re )

Apply the verins theorem to the I/P circuit, we arrive at the simplified equivalent circuits
to the left of the points.

Vb =

RB = R1 || R2

Stability but even if Rb = O, S = 1 i.e the change in Ic equals the change in I CBO. In
general, increase in Ic is always exceeds the increase in I CBO for well defined self bias CE
Amplifier ‘S’ lies in the range 5 to 10.

Consider the equation,

Drift the above expression circuit

VBE (IC = Ib)

VBE = Vb - Ib Rb – ( Ib + IC ) + Re

VBE = Vb - Ib Rb – ( Ib + Ib (1+ ) ICBO ) Re

VBE = Vb - Re - Rb- IC Re

VBE = V b - IC [ ]drift the above expression circuit VBE

191
 1= [ ]

S1 = [ ]

S1 =

From this expression we see that S is reduced , S1 is also reduced .

Consider the equation

Vb = ( Rb + Re )+ IC Re +VBE

Vb -VBE = ( Rb + Re )+ IC Re

Drift the above expression circuit ‘ ’

0= + IC d

+ d IC Re
d IC = [ ]d IC [ ]

d IC = [ ]d IC [ ]

S11 =

STABILITY FACTOR (S)

192
 S=

Consider the equation

Vb = Ib Rb + VBE + ( Ib + IC ) Re

Drift the above expression circuit Ic

O= Rb + R e + Re

(Rb +Re ) = - Re

S = =

S=

From this equation we find that

1) if Rb/Re << 1 ‘S’ becomes 1.
2) The value of ‘S’ increases with increase of ratio Rb/Rc
3) ‘S’ becomes 1+b if Re tends to α
4) Thus smaller the value of ‘Re’ , smaller the value of ‘S’ and better the
where

Vb = & Rb =

Apply KVL to the I/p loop we get ,

193
Vb = Ib Rb + VBE + IC Re
= Vb = Ib Rb + VBE + ( Ib + IC ) Re

Ib Rb + VBE+ ( 1 +β) Ib Re

= Ib Re ( 1 +β) Vb -VBE - Ib RC

Vb = Ib Re +VBE [Ib + RE
This equation relates the base current Ib with VCE Thus using this equation
calculate VCE for each value of Ib and plot a curve called the bias curve. The point of
intersection of a load line bias current gives the Q – point.

IC Ib4

Bias curve Ib3

Q Ib2
Ib1

VCE

CHARACTERISTIC PARAMETERS OF THE JFET

MUTUAL CONDUCTANCE OR TRANS CONDUCTANCE

It is denoted by gm.
It is the slope of the transfer characteristic curve and is defined as ratio of small
change in drain current to the corresponding small change in gate voltage at a constant
drain voltage.

IDSS
ID ( mA)

VP
VGS 194
Transfer Characteristics
 gm = || VDS

= || VDS constant
DRAIN RESISTANCE (RD)

It is the reciprocal of the slope of the drain characteristics and is defined by RD.

RD = || VGS

= || VGS constant

AMPLIFICATION FACTOR (μ)

At constant drain current ID

μ =[ ] ID

= | ID
RELATION BETWEEN FET PARAMETERS

As IDS depends upon the drain to source voltage and gate to source voltage.
ID = f (VGS ,VDS)
If the drain voltage is changed by a small amount from V DS to VDS + ΔVDS and the gate
voltage is changed by a small amount from VGS to VGS + ΔVGS then the corresponding
small change in ID may be obtained by applying Taylor’s theorem, neglecting the higher
order terms. Thus the small change in ID is given by

Δ ID ΔVDS + ΔVGS .............(2)

Dividing both sides of equation (2) by ΔVGS

= +

195
 μ + gm = + gm

if ID is constant then

=0
Then the above equation is reduced to

0= + gm

- gm
μ = rD gm μ= gm rD

channel at a point along channel If I D =0 ID (n) and V (n) are independent of n and b(n)
= Pb =0
V(n) = V
Substitute these two in equation (3) and solve for V and also make one as assumption |
V0| << V
a-b =

b=a-

a2 =

V=
: under these conditions V = |VP |

: |VP | =
We substitute VGS for V and a-b for a then the above equation becomes.

VGS =

196
 =

= = |VP |

= VP
EXPRESSION FOR DRAIN CURRENT ID
ID = J X A
A = Cross sectional area = 2bw
Where 2b is the channel width corresponding to zero drain current and is obtained
by using this equation

VGS == VP

= 1-

b= a

current density J = neμ

L = Drain current
= Jx A
= 2 bw x J

2xa w x ne μ

drain resistance
rD = | VGS constant

= =

EXPRESSION FOR SATURATION DRAIN CURRENT

197
 The transfer characteristics ID VS VGS is shown in figure. The shape of the transfer
characteristics is very nearly a parabola. It is found that the characteristic approximately
represented by a parabola.

IDS = IDSS ..............(1)

Where IDS = saturation drain current

IDSS is the value of IDS when VGS = O
VP represents the pinch off voltage .
Differentiating equation (1) circuit VGS

= IDSS 2 .

.....................(2)

we know that is gm

gm = [ ] ...........(3)
from equation (1)

= ..............(4)

substitute equation (4) in equation (3)

gm = . = ............(5)

when VGS = 0 gm = gmo

then from equation (3)

gm = ..............(6)

then gm = gmo = ...........(7)

The above equation (5) shows that gm varies as the -> saturation drain

current

198
 Equation (7) shows gm decreases linearly with increases of VGS

1. When a reverse gate voltage of 12 v is applied to FET the gate current is

determine the resistance between gate and source.

RGS =

= 12 x 10 -9
When a reverse gate voltage of FET changes from 4V to 3.9V the drain current
changes from 1.3 to 1.6 ma find the value of trance conductance.

gm = =

= +0.3 x 10 -2
= + 3 x 10-3
A FET has drain current of 4 mA if I DSS = 8mA and VGS off = - 6V find the value of
VGS and VP
IDSS 4mA IDSS = 8mA

IDS = IDSS

4 x 10-3 = 83 x 10-3

= -1

VGS = 6 [ 0.707-1]
= 6 x (0.293)
= -1.758v.
= -1.76v

199
1- =

0.293 =

|VP| =

= |-6|
= 6v

EXPRESSION OF PINCH OFF VOLTAGE

Assuming that the p – region is doped with N A acceptors per cubic meter that the
n- region is doped with ND donors per cubic meter and that the junction formed is abrupt.
Assumptions of an abrupt junction is same as that abrupt junction made in p-n junction
diode if NA >> ND then WP << WN for the space charge width Wn(n) = W(n) at distance x
along the charge.

S D
2a 2 b (x)

W(n) = a-b(n) ......(1)

From abrupt P-N junction diode
W= .........(2)

a-b (n) =[ (VO –V(n)).]η2...........(3)

Where E is the dielectric constant of channel material
e = Charge of electron
Vo = Junction contact potential
V(n) = applied potential across

The space charge region at a x this x is a - ev numbers a-b (x) is the penetration
of w(x) into the channel at a point x along the channel.

200
 If the drain current is zero b(x) and r(x) are independent of x and b(x) = b. If in
equation(3) we substitute b(x) : b = O and solve for V, on the assumption that | V o| << | V
|, we obtain the pitch of voltage Vp,

a-D = [ (VO –V).]1/2

a2 = (-VP)

| VP| = .......................(5)

if we substitute VGS for V and a-b for n in the below equation

V =

VGS = (a-b) 2

.a2 = [ ]

= VP

The voltage VGS in equation (6) represents the reverse bias across the gate
junction and independent of channel if ID =0.

PREVIOUS UNIVERSITY QUESTIONS

1. a) Draw the circuit of a self bias circuit and derive expression for S. Why it is
widely used?
b) How to obtain Q point graphically for a transistor amplifier of CE.Explain?
2. What is meant by Thermal Run away? Briefly explain. What is the condition for
thermal stability?
3. An n-p-n transistor if  = 50 is used in CE circuit with V CC = 10volts and RC =
2K. The bias is obtained by connecting 100K resistance from collector to base.
Find Q point and S?
4. Define the stability factors S, S  and what is the need of this in BJT circuits?

201
 5. Draw the circuit of self bias BJT and explain how to determine the values of R 1
and R2.
6. What are the compensation techniques used for V BE and ICO? Explain with the
help of suitable circuits.
7. Draw the circuit of Fixed bias circuit in CE configuration and obtain the
expression for IB. Why the circuit is not suitable if the  of the transistor is
changed.
8. Briefly explain about thermal stability.

FILL IN THE BLANKS

1. In an amplifier circuit, maximum output swing can be achieved by choosing the Q-

point-----[at the mid point of the load line]
2. Operating point specifies ----------- [the dc input voltage, the dc output current when
there is no ac input]
3. Drift of the operating point is caused by ------------. [Variation of collector current
with temperature, variation of transistor parameters with temperature, variation of
transistor parameters with aging]
4. For an ideal amplifier, the stability factor should be -----------. [Small]
5. The stability factor of a practical amplifier lies between --------- [1 and (+1)]
6. The voltage divider bias is used to make the operating point--------- [independent of
]
7. Improper biasing leads to ------------- [distortion of the output waveform]
8. For a BJT amplifier to work------------ [the base-emitter junction should be forward
biased, the base-collector junction should be reverse biased]
9. For fixed bias circuit, the stability factor is -----------. [+1]
10. Thermal stability of the fixed bias circuit is ----------. [Poor]
11. Inclusion of a resistor in the emitter circuit --------. [Improves stability]
12. The Q-point specifies ------- and --------- when there is no ac input. [Dc output
voltage, current]
13. ---------- in an amplifier sets the dc output level some where in the ---- of the range of
possible output voltages. [Bias, middle]
14. -------- Represents all collector current levels and corresponding collector-emitter
------- that can exist in the circuit. [Load line, voltages.]
15. The process of making the operating point ------ of temperature variations is called
---------- [Independent, bias stabilization]
16. The basic equation that is made use of in deriving an expression for stabilization
factor is IC = ------ + ---------. [IB, (1+) ICBO]
17. The stability factor for the fixed bias circuit is -------------. [1+]
18. ----------- Bias circuit is susceptible to thermal runaway. [Fixed]

202
19. --------- Bias circuit provides very good stability. Typical value of S i = 10. [Voltage
divider bias.]
20. The condition to be satisfied for preventing thermal runaway is Pc/Tj < --------.
[PD/Tj]
21. To prevent thermal runaway VCE < ----------. [VCC/2]

203