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RTL Design of APB (Advanced Peripheral Bus) Protocol

The APB (Advanced Peripheral Bus) protocol is a low-cost interface, optimized for minimal power consumption
and reduced interface complexity.
• The APB interface is not pipelined and is a simple synchronous protocol (clock required for transaction).
• Every transfer takes at least two cycles to complete.

The APB interface is designed for accessing the programmable control registers of peripheral devices.
• APB peripherals are typically connected to the main memory system using an APB bridge.
• Example -> A bridge from AXI to APB could be used to connect several APB peripherals to an AXI memory
system.

APB transfers are initiated by an APB bridge.

• APB bridge can also be referred to as a Requester. A peripheral interface responds to requests.
• APB bridge can also be referred to as a Requester. A peripheral interface responds to requests.
• APB peripherals can also be referred to as a Completer.
• In this project, we will use Requester and Completer.

Signal Description

Signal Source Width Description

PCLK Clock 1 PCLK is a clock signal. All APB signals are timed against the
rising edge of PCLK.
PRESETn System bus 1 PRESETn is a reset signal and active – LOW. PRESETn is
reset directly connected to the system bus reset signal.
PADDR Requester ADDR_WIDTH PADDR is the APB address bus. PADDR can be up to 32-bits
wide.
PPROT Requester 3 PPROT indicates the normal or secure protection level of the
transaction and whether the transaction is a data access or
instruction access.
PSEL Requester 1 PSEL indicates that the completer is selected and that a data
transfer is required. The requester generates a PSEL signal
for each completer.
PENABLE Requester 1 PENABLE indicates the second and subsequent cycles of an
APB transfer.
PWRITE Requester 1 PWRITE indicates an APB write access when PWRITE is
asserted HIGH and read access when asserted LOW
PWDATA Requester DATA_WIDTH The PWDATA write data bus is driven by the APB bridge
requester during write cycles when PWRITE is HIGH.
PWDATA can be 8, 16, or 32 bits wide.
PSTRB Requester DATA_WIDTH/8 PSTRB indicates which byte lanes to update during a write
transfer. There is one write strobe for each 8 bits of the write
data bus. PSTRB[n] corresponds to PWDATA [(8n + 7):
(8n)].
PSTRB must not be active during a read transfer.

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PREADY Completer 1 PREADY is used to extend an APB transfer by the Completer.

PRDATA Completer DATA_WIDTH The PRDATA read data bus is driven by the selected
Completer during read cycles when PWRITE is LOW.
PRDATA can be 8 bits, 16 bits, or 32 bits wide.
PSLVERR Completer 1 PSLVERR is an optional signal that can be asserted HIGH
by the Completer to indicate an error condition on an APB
transfer.

[NOTE: There are some more optional signals, I have considered only essential signals in this project.]

Address Bus ->

An APB interface has a single address bus, PADDR for read and write transfer. PADDR indicates
a byte address, and PADDR is permitted to be unaligned concerning the data width, but in such case the result is
UNPREDICTABLE.
Example: A completer might use the unaligned address, the aligned address, or signal an error response.

Data Bus ->

The APB protocol has two independent data buses, PRDATA for read data and PWDATA for write
data. The buses can be 8, 16, or 32 bits wide.
WARNING: The read and write data buses must have the same width.
NOTE: Data transfer can’t occur concurrently because the read data and write data buses do not have their own
individual handshake signals.

Error Response ->

PSLVERR can be used to indicate an error condition on an APB transfer. Error conditions can
occur on both read and write transactions.
PSLVERR is only considered valid during the last cycle of an APB transfer when PSEL, PENABLE, and PREADY are
all HIGH.
NOTE: Error response is recommended, but not required, that PSLVERR is driven LOW when PSEL, PENABLE, or
PREADY are LOW.

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Operating States

The state machine operates through the following states:

IDLE: This is the default state of the APB interface.
SETUP: When a transfer is required, the interface moves into the SETUP state, where the appropriate
select signal, PSEL is asserted. The interface only remains in the SETUP state for one clock cycle and
always moves to the ACCESS state on the next rising edge of the clock.
ACCESS: The enable signal, PENABLE is asserted in the ACCESS state. The following signal must not
change in the transition between SETUP and ACCESS and between cycles in the ACCESS state:
• PADDR
• PPROT
• PWRITE
• PWDATA, only for a write transaction
• PSTRB
EXIT from the ACCESS state is controlled by the PREADY signal from the completer.
• If the PREADY is held LOW by the Completer, then the interface remains in the ACCESS state.
• If the PREADY is driven HIGH by the Completer, then the ACCESS state is exited, and the bus
returns to the IDLE state if no more transactions are required. Alternatively, the bus moves directly
to the SETUP state if another transfer follows.

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Write and Read Transfer

1. Write Transfer
APB interface consists of two types of write transfer:
• With no wait states
• With wait states

With no wait states

The setup phase of the write transfer occurs at T1. The select signal, PSEL, is asserted, which means
that PADDR, PWRITE, and PWDATA must be valid.
The access phase of the write transfer occurs at T2, where PENABLE is asserted. PREADY is asserted
by the Completer at the rising edge of PCLK to indicate that the write data will be accepted at T3. PADDR,
PWDATA, and any other control signals must be stable until the transfer is completed.
At the end of the transfer, PENABLE is de-asserted. PSEL is also de-asserted unless there is another
transfer to the same peripheral.

With wait states

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During an access phase, when PENABLE is HIGH, the Completer extends the transfer by driving PREADY
LOW. The other signals (PADDR, PWRITE, PSEL, PENABLE, PWDATA, PSTRB, PPROT) must be
unchanged while PREADY remains LOW.
PREADY can take any value when PENABLE is LOW. This ensures that peripherals that have a fixed two-
cycle access can tie PREADY HIGH.

2. READ Transfer
APB interface consists of two types of read transfer:
• With no wait states
• With wait states

With no wait states

The timing of the address, write, select, and enable signals are the same as described in WRITE Transfer.
The Completer must provide the data before the end of the READ Transfer.

With wait state

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The transfer is extended if PREADY is driven LOW during an access phase. Other signals (PADDR,
PWRITE, PSEL, PENABLE, PPROT) remain unchanged while PREADY remains LOW.
NOTE: Any number of cycles can be added from zero to upwards.

WRITE Transfer with Error

When a write transaction receives an error, this does not mean that the register within the peripheral has
not been updated.

READ Transfer with Error

Read transactions that receive an error can return invalid data. There is no requirement for the peripheral
to drive the data bus to all 0s for a read error. A Requester which receives an error response to a read
transfer might still use the data.
A read transfer can also be completed with an error response, indicating that there is no valid read data
available.

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RTL Schematic

Simulation Result

Check my previous post: “RTL Design of AXI Stream Protocol”.

“RTL Design of UART Protocol”.

Reference: ARM IHI0024E

✔️ For source code ping me on LinkedIn.