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04 01 FSEMI Design Specification

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Nguyễn Thanhthanh
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22 views16 pages

04 01 FSEMI Design Specification

Uploaded by

Nguyễn Thanhthanh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FPT Semiconductor | December, 2023

Table of Content

1. General Design Specification Flow


2. FSM State Machine
3. Design Practice

2
1 General Design Specification
Analyzation from Spec
High level Block Design
Level Block Design
1. General Design Specification Flow
Start

Research

False High Level


Block Design
True Low Level
Fix
Block Design
False
Syntax True
RTL Description
Err

Syntax and Design


Rule Check

False
Satisfy?

4
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2 Finite State Machine (FSM)
Definition
Operation
Application
2. Finite State Machine (FSM)
Definition
▪ Sequential Circuit which is used for modelling control operation following step
▪ Three main components: Next state generation, State register, Output generation
Exist or Not

Inputs Outputs
Comb Comb

Type
Inputs Outputs
[Moore FSM] Comb Comb
Output depends on only current
6
6

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2. Finite State Machine (FSM)
Type
[Mealy FSM]
▪ Output depends on both current state and input

Inputs Outputs
Comb Comb

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2. Finite State Machine (FSM)
Usage
[Example]
▪ Detect “001” in randomized bit string

▪ Moore FSM

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2. Finite State Machine (FSM)
always @ (*) begin
Usage case (current_state[1:0])
IDLE: begin
[Example] if (~s_in) next_state[1:0] = D0;
▪ RTL Coding else next_state[1:0] =
parameter IDLE = 2'd0; current_state[1:0];
parameter D0 = 2'd1; end
parameter D00 = 2'd2; D0: begin
parameter D001 = 2’d3; if (~s_in) next_state[1:0] = D00;
else next_state[1:0] = IDLE;
end
State Definition D00: begin
if (s_in) next_state[1:0] = D001;
else next_state[1:0] =
current_state[1:0];
end
D001: begin
if (s_in) next_state[1:0] = IDLE;
Next State Generation else next_state[1:0] = D0;
end
default: next_state[1:0] = IDLE; 9
endcase
end
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2. Finite State Machine (FSM)
Usage
[Example]
▪ RTL Coding
always @ (posedge clk, negedge
rst_n) begin State Register
if (~rst_n)
current_state[1:0] <= IDLE;
else current_state[1:0] <=
next_state[1:0];
end

always @ (*) begin


if (current_state[1:0] ==
D001) valid = 1'b1; Output
else valid = 1'b0;
end 10

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2. Finite State Machine (FSM)
Usage
[Example]
▪ Detect “001” in the randomized bit string

▪ Mealy FSM

11

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2. Finite State Machine (FSM)
Usage
[Example]
▪ RTL Coding?
Q: Coding?

12

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3 Design Practice
Design data transmission between parallel and serial
Design NVM reader
3. Design
Data Transmission Between Parallel and Serial
Design Requirement
▪ Design a circuit which has 2 functions: 8 bit data transmission from parallel to serial and vice – verse.
▪ The circuit executes one function at a moment.

14

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3. Design
NVM Reader

Design Requirement
▪ Design a reader circuit which read data from NVM memory: Flash, EPROM,…
▪ This reader circuit receives request signal from system: system sends a read signal, address of 1 byte
data need to be read, after that this circuit send signal to NVM for getting data from NVM (data
output is transmitted in serial output)
▪ NVM has 32 register, each register is 8 bit
▪ The NVM register address map is as below:

15

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THANK YOU

16

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