Unit 9 – SUN SPARC Microprocessor

1. INTRODUCTION
 SPARC is an acronym for Scalable Processor ARChitecture
 Designed to optimize compilers and pipelined hardware implementations.
 Offers fast execution rates.
 SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II designs
engineered at the University of California at Berkeley from 1980 through1982.
 SPARCs are load/store RISC processors. Load/store means only loads and stores access
memory directly.
 RISC (Reduced Instruction Set Computer) means the architecture is simplified with a
limited number of instruction formats and addressing modes.
 SPARC was designed as a target for optimizing compilers and easily pipelined hardware
implementations.
 SPARC implementations provide exceptionally high execution rates and short time-to-
market development schedules.
 A SPARC processor logically comprises an integer unit (IU), a floating-point unit (FPU), and
an optional coprocessor (CP), each with its own registers.
 All of the registers with the possible exception of the coprocessor’s — are 32 bits wide.
 The processor can be in either of two modes: user or supervisor.
1) Supervisor Mode: The processor can execute any instruction, including the
privileged (supervisor-only) instructions.
2) User Mode: An attempt to execute a privileged instruction will cause a trap to
supervisor software. “User application” programs are programs that execute while
the processor is in user mode.

2. FEATURES:
 Performance and Economy
 Simplified instruction set
 Higher number of instructions with fewer transistors
 Scalability
 Flexible integration of cache, memory and FPUs
 Open Architecture
 Compatible technology to multiple vendors
 Base on RISC Architecture
 64-bit addressing and 64-bit data bus
 Increased bandwidth
 Fault tolerance
 Nine stage pipeline; can do up to 4 instructions per cycle
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 Unit 9 – SUN SPARC Microprocessor
 On-chip 16Kb data and instruct caches with 2Mb external cache
 A large “windowed” register file — at any one instant, a program sees 8 global integer
registers plus a 24-register window into a larger register file. The windowed registers can
be described as a cache of procedure arguments, local values, and return addresses.

3. Architecture

Figure: SUN Super SPARC Architecture

 The SPARC processor is divided into three parts:
1) an Integer Unit (IU)
2) a Floating-Point Unit (FPU)
3) an optional CoProcessor (CP)
each with its own registers. (32-bits wide)

3.1 Integer Unit

 Contains the general purpose registers and controls the overall operation of the processor.
 May contain from 64 to 528 general-purpose 64-bit r registers. They are partitioned into 8
global registers, 8 alternate global registers, plus a circular stack of from 3 to 32 sets of 16
registers each, known as register windows.
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 Unit 9 – SUN SPARC Microprocessor
 Executes the integer arithmetic instructions and computes memory addresses for loads
and stores.
 Maintains the program counters and controls instruction execution for the FPU.

The Register Window

 At any time, an instruction can access the 8 global registers and a 24-register window
 A register window comprises a 16-register set- divided into 8 in and 8 local registers-
together with the 8 in registers of an adjacent register set, addressable from the current
window as its out registers.
 When a procedure is called, the register window shifts by sixteen registers, hiding the old
input registers and old local registers and making the old output registers the new input
registers.
Input registers: arguments are passed to a function
Local registers: to store any local data.
Output registers: When calling a function, the programmer puts his argument in these
registers.
 The current window into the r registers is given by the current window pointer (CWP)
register.

Fig: Three overlapping register windows

 The active window is identified by the 5-bit Current Window Pointer (CWP).
 Decrementing the CWP at procedure entry causes the next window to become active.
 Incrementing the CWP at procedure entry causes the previous window to become active.

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 Unit 9 – SUN SPARC Microprocessor

Fig: Eight register windows forming a circular stack

 Register window overflow and underflow conditions are handled in software by a kernel
trap handler.
 The Window Invalid Mask (WIM) can tag any window so that an overflow or underflow
trap is generated whenever the CWP is about to point a tagged window.

ADVANTAGE

 Make very fast procedure calls as they avoid the need to save a processor’s current in
memory, further reducing off-chip traffic.
 Instead, the state variables are held in the current window, and the next window is opened
for the new procedure.
 A refinement on this idea in that the input and output registers of adjacent windows
overlap, allowing variables and parameters to be passed to the next process without
physically moving data.
 The additional registers are hidden from view until you call a subroutine or other function.
Where other processors would push parameters on a stack for the called routine to pop off,
SPARC processors just "rotate" the register window to give the called routine a fresh set of
registers.
 The old window and the new window overlap, so that some registers are shared.

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 Unit 9 – SUN SPARC Microprocessor

3.2 Floating-point Unit (FPU)

 The FPU has 32 32-bit (single-precision) floating-point registers, 32 64-bit (double-
precision) floating-point registers, and 16 128-bit (quad-precision) floating-point registers.
 Double-precision values occupy an even-odd pair of single-precision registers.
 Quad-precision values occupy an odd-even number pair of double precision registers.
 Floating-point load/store instructions are used to move data between the FPU and
memory.
 The memory address is calculated by the IU.
 Floating-Point operate (FPop) instructions perform the floating-point arithmetic
operations and comparisons.
3.3 Coprocessor Unit (CU)
 The instruction set includes support for a single, implementation-dependent coprocessor.
The coprocessor has its own set of registers.
 Coprocessor load/store instructions are used to move data between the coprocessor
registers and memory.
 Floating-point instructions mirror coprocessor instructions.

4. SPARC DATA TYPES

 SPARC supports
 integer data types that are signed and unsigned bytes
 16-bit half words
 32-bit words
 64-bit double words.
 There is a tagged word format in which the 2 least significant bits serve as flags to indicate
the type of object.
 The floating point numbers can be 32(single), 64 (double), or 128 (quad) bits long; they
conform to the IEEE 754 standard.
 SPARC is "big-endian"- it stores multiple byte objects in memory with the most significant
byte at the lowest address.

5. SPARC Instruction Types

There are very few addressing modes on the SPARC, and they may be used only in certain very
restricted combinations. The three main types of SPARC instructions are given below, along with

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 Unit 9 – SUN SPARC Microprocessor
the valid combinations of addressing modes. There are only a few unusual instructions which do
not fall into these categories.

1. Arithmetic/Logical/Shift instructions
opcode reg1,reg2,reg3 !reg1 op reg2 -> reg3
opcode reg1,const13,reg3 !reg1 op const13 -> reg3

 All "action" instructions (add, sub, and, or, etc.) take three operands.
 The destination is always the third operand.
 The middle operand may be a 13-bit signed constant (-4096...+4095).
 Otherwise, all operands are registers.
 Examples:

add %L1,%L2,%L3 !%L1+%L2->%L3

2. Load/Store Instructions

opcode [reg1+reg2],reg3
opcode [reg1+const13],reg3

 Only load and store instructions can access memory.

 The contents of reg3 is read/written from/to the address in memory formed by adding
reg1+reg2, or else reg1+const13 (a 13- bit signed constant as above).
 The operands are written in the reverse direction for store instructions, so that the
destination is always last.
 One of reg1 or const13 can be omitted. The assembler will supply $g0 or 0. (This is a
shorthand provided by the assembler. Both are always there in machine language.)
 Examples:

ld [%L1+%L2],%L3 !word at address [%L1+%L2]->%L3

3. Branch Instructions

opcode address

 Branch to (or otherwise use) the address given.

 There are actually 2 types of addresses but they look the same.
 Examples:

call printf
be Loop

Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing 6