UNIT 2 – ARITHMETIC UNIT

INTRODUCTION

In this chapter mainly we are going to study about the Arithmetic and Logic
operations. Arithmetic and Logic operations means, Addition, Subtraction,
Multiplication and Division for the binary numbers. After studying this chapter, you
can able to understand the distinction between the way in which numbers are
represented (the binary format) and the algorithms used for the basic arithmetic
operations. Also, in this chapter we will study about twos complement representation,
present an overview of the techniques for doing basic arithmetic operation in two
complement notations. We begin our examination of the processor with an overview of
the arithmetic and logic unit (ALU). The chapter then focuses on the most complex
aspect of the ALU, computer arithmetic. The logic functions that are part of the ALU
are described in earlier, and implementations of simple logic and arithmetic functions
in digital logic are also described. Computer arithmetic is commonly performed on two
very different types of numbers: integer and floating point. In both cases, the
representation chosen is a crucial design issue and is treated first, followed by a
discussion of arithmetic operations.

In this system, he most significant (leftmost) bit in the word as a sign bit. If the
sign bit is 0, the number is positive; if the sign bit is 1, the number is negative. The
simplest form of representing sign bit is the sign magnitude representation. One of the
draws back for sign magnitude number is addition and subtraction need to consider both
sign of the numbers and their relative magnitude. Another drawback is there are two
representations for 0 (Zero) i.e +0 and -0.

One’s Complement (1’s) Representation

In this representation negative values are obtained by complementing each bit of

the corresponding positive number. For example, 1s complement of 0101 is 1010. The
process of forming the 1s complement of a given number is equivalent to subtracting
that number from 2n -1 i.e from 1111 for 4 bit number.

Two’s Complement (2’s) Representation

Forming the 2s complement of a number is done by subtracting that number from
2n. So 2s complement of a number is obtained by adding 1 to 1s complement of that
number.
Example: 2’s complement of 0101 can be like
Original value is 0101
1’s complement is 1010
2’s complement is 1
1011

For our understanding, in all three systems, the leftmost bit is 0 for positive number and
1 for negative number.

Addition
In addition two numbers are added like addition of +ve integers. On any addition,
the result may be larger than can be held in the word size being used. This condition is
called overflow. When overflow occurs, the ALU must set the overflow bit as 1
indicating the overflow. If two numbers are added, and they are both positive or both
negative, then overflow occurs if and only if the result has the opposite sign. If one of
the operand is –ve then it has to be represented in either of the complement form for
getting correct result.
Subtraction
To subtract one number (subtrahend) from another (minuend), take the 2’s
complement ( or negation) or 1’s complement of the subtrahend and add it to the
minuend. When using the complement methods in subtraction and having no additional
1 in the extreme left cell, then, this means a negative result. In this case, the solution is
the negative of 1’s complement of the result (if using 1’s complement initially), or the
negative of 2’s complement of the result (if using 2’s complement initially).If there is a
carry in the extreme left then in 1’s complement, it is discarded and 2’s complement, it
is added to the result.
 Arithmetic Operations occur at the machine instruction level. They are
implemented along with basic logic functions such as
 Now we are going to discuss about the addition and subtraction of the numbers
are how taking part in the logic circuit. Generally, in the login circuit consider that three
inputs and two outputs in which one input will be the carry in and one output will be
the carry out.
In this table Xi, Yi, Carry-in (Ci) are the inputs and sum of all these numbers are
mentioned in Si, Carry-out of this input is given in Ci+1. Binary numbers of 1 to 7 is
given as input and corresponding output is given in Si and Ci+1. Also, the calculation
of this Si and Ci+1 is given below in equation.
Consider an example of addition of 4 bits unsigned numbers 7 and 6. The
following example takes place of this.

Addition logic for a single stage addition is

 Sum and Carry is implemented with a two level AND-OR logic circuit. A
convenient symbol for the complete circuit for a single stage of addition is called a Full
Adder (FA) which is shown in this diagram.

In this diagram xi, yi are the normal input and ci is the carry input. Si is the sum of the
input and ci+1 is the carry out.

n bit Ripple Carry Adder

Earlier we have discussed full adder and now we are going to discuss with some
other methods. A Cascade connection of n full adder blocks can be used to add two n
bit numbers. since the carry must propagate through this cascade, the configuration is
called n bit Ripple Carry Adder.

In this Ripple carry adder circuit is used for more number of stages need to be added
means, this can be used. And one stage (Full Adder) carry out value will be the carry in
value for the next stage.
Subtraction Operation on two unsigned Numbers
In-order to perform subtraction operation X-Y on two’s complement number X
and Y, determine the two’s complement of Y and add it to X.

In this above circuit, Binary Addition/Subtraction Logic Network can be used to

perform either addition or subtraction based on the value applied to Add/Sub input
control line. Add/Sub Control line is set to zero for addition, applying the Y vector
unchanged to one of the adder inputs along with a carry in signal, c0 of 0. When the
Add/Sub control line is set to one, the Y vector is 1’s complemented by the XOR gates
and c0 is set to 1 to complete the two’s complementation of Y.

Design of Fast Adders

If an n bit ripple carry adder is used in addition/subtraction unit, it may have too
much delay in developing its outputs, s0 through sn-1 and cn. Delay through a network
of logic gates depends on 1) IC Electronic technology used in fabricating the network
and 2) Number of gates in the paths from inputs to outputs. Delay through any
combinational logic network constructed from gates in a particular technology is
determined by adding up the number of logic gate delays along the longest signal
propagation path through the network. In case of n bit ripple carry adder, longest path
is from inputs x0, y0, c0 at Least Significant Bit Position (LSB) to outputs cn, sn-1 at
the Most Significant Bit (MSB) Position.
Recall the equations from the beginning of this chapter

si  xi  yi  ci
ci 1  xi yi  xi ci  yi ci

Second equation can be written as:

ci 1  xi yi  ( xi  yi )ci
We can write the above equation like

ci 1  Gi  Pi ci
where Gi  xi yi and Pi  xi  yi

In the above equations, Gi is called generate function and Pi is called propagate

function. Gi and Pi are computed only from xi and yi and not ci, thus they can be
computed in one gate delay after X and Y are applied to the inputs of an n-bit adder. All
carries can be obtained 3 gate delays after X, Y and c0 are applied. One gate delay for
Pi and Gi. Two gate delays in the AND-OR circuit for ci+1. All sums can be obtained
1 gate delay after the carries are computed. Independent of n, n-bit addition requires
only 4 gate delays. This is called Carry Lookahead adder.

ci 1  Gi  Pi ci
ci  Gi 1  Pi 1ci 1
 ci1  Gi  Pi (Gi 1  Pi 1ci 1 )
continuing
 ci1  Gi  Pi (Gi 1  Pi 1 (Gi  2  Pi 2 ci 2 ))
until
ci1  Gi  PiGi 1  Pi Pi1 Gi 2  ..  Pi Pi 1 ..P1G0  Pi Pi 1 ...P0 c 0
 xi yi

. .
. ci

B-cell for a single stage

B
cell

Gi Pi si

Let us consider the design in a 4-bit adders. The carries can be implemented as

c1  G0  P0 c0
c2  G1  PG
1 0  P1 P0 c0

c3  G2  P2G1  P2 PG
1 0  P2 P1 P0 c0

c4  G3  P3G2  P3 P2G1  P3 P2 PG
1 0  P3 P2 P1 P0 c0

The above diagram explains about the 4-bit carry lookahead addition using the B cell
which is explained in pervious topic. Same like this 4n bit adder also can be explained
by using the diagram given below.
After xi, yi and c0 are applied as inputs the following can be handled in this.
- Gi and Pi for each stage are available after 1 gate delay.
- PI is available after 2 and GI after 3 gate delays.
- All carries are available after 5 gate delays.
- c16 is available after 5 gate delays.
- s15 which depends on c12 is available after 8 (5+3) gate delays (Recall that for a 4-
bit carry lookahead adder, the last sum bit is available 3 gate delays after all inputs are
available)

So far we have discussed about binary addition and subtraction. Now we are going to
discuss about the binary multiplication.

MULTIPLICATION
In this multiplication we are going to discuss the following different methods.
1. Multiplication of unsigned numbers
a. Sequential Multiplication
2. Signed-Operand Multiplication
a. Booth Algorithm
3. Fast Multiplication
a. Bit-Pair recording of multipliers
b. Carry-save addition of summands
Above different methods are having the different algorithms and circuits that leads to
solve the problems using the binary numbers.

1. a. Multiplication of unsigned numbers - Sequential Multiplication

In this topic we will be discussing about the binary multiplication of unsigned
numbers. Unsigned numbers means there wont be sign values ( + or - ) in the given
Multiplicand and Multiplier values.
Now we are going to study about the normal binary multiplication of two
numbers. In this example consider the value of Multiplicand (M) is 13 and Multiplier
(Q) is 11.
When we convert this into the binary
M  13 = 1 1 0 1
Q  11 = 1 0 1 1
In this the binary values of M will be represented as like
1 1 0 1  M3, M2, M1, M0
Similarly Q is
1 0 1 1  Q3, Q2, Q1, Q0

Now we are going to do the Normal binary multiplication.

 In this above calculation, take the multiplier bits and multiply with the
multiplicand. So first multiplier bit (Q0) is 1 and multiply with the multiplier. Next
you have to take 2nd bit of multiplier (Q1) i.e 1 and multiply. Next take the 3rd
multiplier bit (Q3) i.e 0 and multiply. Finally take the 4th multiplier bit (Q4) and
multiply. Once multiplying all the bits with multiplier, then you can add those bits.
Finally, you will get a product.
This can be derived in a diagram

In this case each of multiplication taken care with typical multiplication cell.
Multiplication is usually provided in the machine instruction set of a processor. Practical
size of multiplying numbers as 32 or 64 bit numbers. The simplest way to perform
multiplication is to use adder circuitry in the ALU for a number of sequential steps.

Sequential Multiplication
So far we have discussed about normal binary multiplication. But when the
computer operates the instructions execution, it may work with the sequential
multiplication to avoid the more carry values to be added. Now we are going to discuss
the sequential multiplication method with its algorithm.
Algorithm:
1. Recall the rule for generating partial products:
If the ith bit of the multiplier is 1, add the appropriately shifted
multiplicand to the current partial product.
Multiplicand has been shifted right when added to the partial product.

2. However, adding a right-shifted multiplicand to an unshifted partial product

is equivalent to adding an unshifted multiplicand to a right-shifted partial
product.

Sequential Circuit Multiplier:

 In this example, the 4 bit multiplier is stored in Q register, the 4 bit multiplicand
is stored in register B and the register A is initially cleared to zero. The multiplication
process starts with checking of the least significant bit of B whether it is 0 or 1. If the
B0 = 1, the number in the multiplicand (B) is added with the least significant bits of the
A register and all bits of C, A and Q registers are shifted to the right one bit. If the bit
B0 = 0, the combined C and Q registers are shifted to the right by one bit without
performing any addition. This process is repeated for n times for n bit numbers. This
method of binary multiplication is called as parallel multiplier.

Consider the above figure in which the multiplier and multiplicand values are
given as 1011 and 1101 which are loaded into the Q and A registers respectively.
Initially the register C is zero and hence the A register is zero, which stores the carry in
addition. Since the B0 =1, then the number in the B is added to the bits of A and produce
the addition result as 1101, and the Q and A register are shifted their values one bit right
so the new values during the first cycle are 0110 and 1101 respectively. This process
has to be repeated four times to perform the 4 bit multiplication. The final multiplication
result will be available in the A and Q registers as 10001111.

2. Signed-operand Multiplication
In this method, Sign will be used (+ or -) also will be there. So, one more bit for
the sign need to be added along with the original values.
Considering 2’s-complement signed operands, what will happen to (-13) x (+11)
if following the same method of unsigned multiplication?

In this above example, after completing the normal multiplication, sign bit need
to extended as like given in red color. Since this is a signed multiplication, this
procedure needs to follow. For a negative multiplier, a straightforward solution is to
form the 2’s-complement of both the multiplier and the multiplicand and proceed as in
the case of a positive multiplier. This is possible because complementation of both
operands does not change the value or the sign of the product. A technique that works
equally well for both negative and positive multipliers – Booth algorithm. Now we are
going to discuss the Booth Multiplication with examples.

Consider in a multiplication, the multiplier is positive 0011110, how many

appropriately shifted versions of the multiplicand are added in a standard procedure?
In this booth multiplier, the following truth table is used for the multiplicand and while
applying, Bit i and bit i-1 should be considered.

Since 0011110 = 0100000 – 0000010, if we use the expression to the right, what
will happen?

If you applying the truth table and now you will get the value as
 The Booth algorithm generates a 2n-bit product and treats both positive and
negative 2‟scomplement n-bit operands uniformly. In general, in the Booth algorithm,
−1 times the shifted multiplicand is selected when moving from 0 to 1, and +1 times the
shifted multiplicand is selected when moving from 1 to 0, as the multiplier is scanned
from right to left.

Example 2:
We may also consider another example for the booth multiplication that
Multiplicand (M) is (+13) and Multiplier (Q) is (-6).
Binary values for the above M and Q are

In this case we need to know, how can we find the binary number for negative
multiplier. As we know, if the sign bit of the multiplicand or multiplier is + then we
should add 0 and if the sign bit is – then we should add 1.
In this example Multiplier is -6. So initially we should write the binary for +6. Next
should find the 1’s complement value. To find once complement of the given value, if
a bit is 0 then change it to 1 and if a bit is 1 then change it 0. After finding 1’s
complement, Add 1 with the 1’s complement value. Now you have the 2’s complement
value. This is given below to understand clearly.

Now we are going to apply the booth multiplication in multiplier values.

In general, in the Booth scheme, -1 times the shifted multiplicand is selected when
moving from 0 to 1, and +1 times the shifted multiplicand is selected when moving
from 1 to 0, as the multiplier is scanned from right to left.
Above is the booth recording of a multiplier. In this booth multiplier based on the sifting
the bits, can be classified into 3 methods.

a. Worst-case multiplier
b. Ordinary multiplier
c. Good multiplier

Example for the above methods are

3. Fast Multiplication

In this fast multiplication, there are two different methods can be used.

a. Bit-Pair Recording of Multipliers

b. Carry-Save Addition of Summands

Now we are going to discuss one by one with suitable example.

a. Bit-Pair Recording of Multipliers

Bit-pair recoding halves the maximum number of summands (versions of the

multiplicand). In this case also we have to follow the truth table as like Booth
Multiplication. The difference is we have considered ith bit and i-1 bits are
considered for booth multiplication. In this Bit-Pair Recording of Multipliers we
are going to consider ith bit, i-1 and i+1 bits. Before going to discuss with the
example, we are going to discuss the truth table.
Now we can write the binary values for given multiplicand and multipliers are

From this we already know how to apply the booth multiplication. To understand easily
booth multiplication can be solved like,
 Now we are going to apply Bit-Pair Recording of multipliers method in given
problem. After applying the truth table in multiplier we get the values. Then have to
do like this.

Once the values are applied and got the values, before going to the final step sign bit
extension also should be extended as like given on “Blue” color. After that can add
those multiplier values. While adding this finally, if any carry comes then it should be
discarded.

b. Carry-Save Addition of Summands

Consider the addition of many summands, we can Group the summands in threes
and perform carry-save addition on each of these groups in parallel to generate a set
of S and C vectors in one full-adder delay. Group all of the S and C vectors into
threes, and perform carry-save addition on them, generating a further set of S and
C vectors in one more full-adder delay. Continue with this process until there are
only two vectors remaining. They can be added to produce the desired product. So
when we apply this method and executing, total number carry forwarding will be
avoided and each bit position calculation itself carry will be kept. So maximum only
one carry will be forwarded to next position and calculation will be very easy in
carry-save addition of summands. The original process will be like given in this
diagram.
When we are applying the Carry-Save Addition of Summands method, this can be
changed as given below.

Now we are going to discuss with the example.

In this example the given value of Multiplicand (M) is 45, and Multiplier (Q) is 63.
When we are converting this into binary and follow the normal binary multiplication as
like given here.

Finally, when we are finding the product, in some places a more number of 1’s is going
to be added. At that time carry out value will be higher. To avoid that only carry save
addition of summands will be used. To us this method, you have to understand this.
In this case given bits are considered as A, B, C, D, E, and F. So set of 3 multiplier
values are taken for adding in each stage. After adding each stage we will get one Sum
(S) value and one Carry (C) value.

When we start doing to solve this problem, the position of the bits should not be
changed. If the position is changed when we are doing the problem, then the hole
calculation will be wrong. So as solved in this example, have to follow with each and
every step. Here instead of forwarding the carry value into other bits, it is saved in that
particular bit position. So through out this calculation, maximum number of 1s can be
added is only three. So the carry also will be the 1 maximum.
INTEGER DIVISION
Integer Division has generally two different methods.
1. Restoring Division
2. Non-Restoring Division

These above two methods are having different algorithms to be following. Now
we are going to study one by one. First we are going to solve some problems using the
Restoring Division. Before going to start, we should know the normal binary division.
So we will have Dividend value and Divisor values. If the values are given in numerical,
then it should be converted into binary and no sign bits will be used here.

Now we are going to solve the Numerical division and Binary division.

Numerical division

For the same Dividend and Divisor, we are going to do the Binary Division

Binary division
Now we are going to implement the Integer Division by using a algorithm. Position the
divisor appropriately with respect to the dividend and performs a subtraction. If the
remainder is zero or positive, a quotient bit of 1 is determined, the remainder is extended
by another bit of the dividend, the divisor is repositioned, and another subtraction is
performed. If the remainder is negative, a quotient bit of 0 is determined, the dividend
is restored by adding back the divisor, and the divisor is repositioned for another
subtraction.

Algorithm

Step 1: Shift A and Q left one binary position

Step 2: Subtract M from A, and place the answer back in A

Step 3: If the sign of A is 1, set q0 to 0 and add M back to A (restore A);

otherwise, set q0 to 1

Step 4: Repeat these steps n times

Circuit arrangement of the above algorithm is like

Now we are going to see with the examples. In this example we consider the Dividend
(M) is 8 and Divisor (Q) is 3. Initially we have to find the binary value of it. So

M1 1 1 1

Q0 0 1 1

Before doing the Integer division, first do the normal binary division
Non-Restoring Division

Same like Restoring algorithm, we are going to see the Non-restoring method to be
followed by using the algorithm. To avoid the need for restoring A after an unsuccessful
subtraction, we implement the following algorithm.

Algorithm

Step 1: (Repeat n times)

If the sign of A is 0, shift A and Q left one bit position and subtract M
from A; otherwise, shift A and Q left and add M to A.

Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.

Step2: If the sign of A is 1, add M to A

Circuit arrangement of the above algorithm will be like

Now we are going to see with the examples. In this example we consider the Dividend
(M) is 8 and Divisor (Q) is 3. Initially we have to find the binary value of it. So
 M1 1 1 1

Q0 0 1 1

Before doing the Integer division, first do the normal binary division
After all the cycles has been completed, only in this Non-Restoring division we have to
check the carry bit. If carry bit 0, then we can stop the process and write the Quotient
and Remainder.

But, after completion of all the cycles, the carry bit is 1, then we have to do one more
like add the M value with the remainder and stop the process for restoring it.

Now we can write the Quotient is 0 0 1 0, and Remainder is 0 0 0 1 0.