Verilog:

1. What will be the equivalent code of the following Verilog code using blocking statements? No
temporary variable.
Initial
Begin
A = 10;
A <= 25;
B <= A;
End

2. Difference between a task and a function.

Answer: The following rules distinguish tasks from functions:
A function must execute in one simulation time unit; a task can
contain time-controlling statements.
A function cannot enable a task; a task can enable other tasks and
functions.
A function must have at least one input argument; a task can have
zero or more arguments of any type.
A function returns a single value; a task does not return a value.

3. Write a Verilog code for a simple one hot state machine?

Answer: -

4. What will be the logic implementation using a case statement and an if-else statement?
Answer: - Multiplexer.

5. How to model inertial and transport delay using Verilog?

Answer: - Following simple example can illustrate the concept.

module delay(in,transport,inertial);
input in;
output transport;
output inertial;

reg transport;
wire inertial;

// behaviour of delays
always @(in)
begin
transport <= #10 in;
end

assign #10 inertial = in;

endmodule // delay

The timing Diagram for input and outputs

_______ __
in _____| |_____||_______
 _______ __
transport _________| |_____||_____

_______
inertial _________| |____________

Non blocking assignment gives you transport delay. Whenever input changes, output is immediately
evaluated and kept in a event queue and assigned to output after specified "transport" delay.

In Continuous assign statement the latest event overrides the earlier event in the queue.

I am attaching rudimentary testbench and its output. Hope this helps.

module test;
reg in;
wire transport, inertial;

// instantiate delay module

delay my_delay(in,transport,inertial);

// apply inputs
initial
begin
in = 0;
#20 in = 1;
#20 in = 0;
#30 in = 1;
#5 in = 0;
#30 in = 1;
#30 $finish;
end
// monitor signals
initial
begin
$monitor($time," in = %b transport = %b inertial = %b",
in,transport, inertial);
end

endmodule // test

log file
Compiling source file "delay.v"
Highest level modules:
test

0 in = 0 transport = x inertial = x
10 in = 0 transport = 0 inertial = 0
20 in = 1 transport = 0 inertial = 0
30 in = 1 transport = 1 inertial = 1
40 in = 0 transport = 1 inertial = 1
50 in = 0 transport = 0 inertial = 0
 70 in = 1 transport = 0 inertial = 0
75 in = 0 transport = 0 inertial = 0
80 in = 0 transport = 1 inertial = 0
85 in = 0 transport = 0 inertial = 0
105 in = 1 transport = 0 inertial = 0
115 in = 1 transport = 1 inertial = 1
L35 "delay.v": $finish at simulation time 135
81 simulation events

6. always clock = #2.5 clock; delayed_clock = #7 clock. What will be the simulation result?
Question: - Write a Verilog code for a single clock FIFO.
Answer: -

Question: - Difference between $display and $monitor?

Answer: - These commands have the same syntax, and display text on the screen during
simulation. They are much less convenient than waveform display tools like
GTKWave. or Undertow or Debussy. $display and $strobe display once every time
they are executed, whereas $monitor displays every time one of its parameters
changes. The difference between $display and $strobe is that $strobe displays the
parameters at the very end of the current simulation time unit rather than exactly
when it is executed.

7. Difference between compiled code and normal simulator. A compiled code simulator compiles all
the files(design and verification) and writes out an executable(similar to a.out, for people familiar
with C language). The engineer then needs to run this executable in order to perform the
simulation. This simulator will speed up the simulation since it need not compile each and every
file for every simulation run. It will detect the files that are modified and compile those files and
files that depend on those modified files. A normal simulator performs compilation and execution
in the same step. So it has to compile each and every file whenever a simulation is performed.
8. Blocking and Non-blocking assignments*
Case I: Blocking Procedural Assignments
Initial begin
#1 a=b;
#1 c=d;
#1 e=f;
end
In this case, as soon as the initial block is entered, we wait for 1time unit and then sample the
value of b and assign that value of b to a. Then wait for 1 more time unit, sample the value of d
and assign that value of d to c and so on.
Case II: Blocking Intra-procedural assignment
Initial begin
a= #1 b;
c= #1 d;
e= #1 f;
end
In this case, as soon as the initial block is entered, we sample the value of b, then wait for 1 time
unit and assign that value of b to a. Then sample the value of d, wait for 1 more time unit, and
assign that value of d to c and so on.
Case III: Non-Blocking procedural assignment
Initial begin
 #1 a <= b;
#1 c <= d;
#1 e <= f;
end
In this case, as soon as the initial block is entered, we wait for 1time unit and then sample the
value of b and assign that value of b to a. Then wait for 1 more time unit, sample the value of d
and assign that value of d to c and so on. Because its non-blocking assignment, the assignment
is made at the END of the timestep.
Case IV: Non-Blocking Intra-procedural assignment
Initial begin
a<= #1 b;
c<= #1 d;
e<= #1 f;
end
In this case, as soon as the initial block is entered, we sample the value of b,d and f, then wait for
1 time unit and assign that value of b to a, value of d to c and the value of f to e.

Question: - Difference between casex and case statements?

Answer: - Special versions of the case statement allow the x ad z logic values to be used
as "don't care":

 casez : Treats z as don't care.

 casex : Treats x and z as don't care.

Question: - What is defparam used for?

Answer: - Defparam is used to override the parameter declarations during run-time.

Question: - What's the difference between a latch and a flip-flop? Write Verilog RTL code for
each?
Answer: - A latch is a level sensitive where as Flip-Flop is a edge sensitive.

Question: - assign #4 out = in; in the above statement if the signal in changes with in 4 units of
time what will be the value of out after 4 units?
Answer: -

Question: - Whatever a function does, a task can also do. Why do we still use functions?

Answer: - function returns a value but task does not.

Question: - How to override parameters?

Answer: - By using defparam.

Question: - Write a 2:1 MUX Code?

Answer: - Tertiary Operator

Out = select?In1:In2;
 Always @ (select or In1 or in2)

Begin

Case{select}

2’b0 : out = in2;

2’b1 : out = in1;

Endcase

End

Question: - Define types of coding?

Answer: - There are four-types of coding:

 Behavioral (comes in always/initial blocks)

 Structural (netlist)
 Dataflow (in terms of expression)
 Switch level (FET/BJT Level, similar to spice netlists)

Question: - Define various verilog data types?

Answer: - net, reg,

Question: - Non/Synthesizable constructs?

Answer: - Non-Synthesizable constructs are :-

 Initial - used only in test benches.

 Events - Event makes more sense for synthesizing test bench
components.
 Real - real data type not supported.
 Time - time data type not supported.
 Force and release - force and release of data type not
supported.
 Assign and deassign - assign and deassign of reg data
type not supported but assign on wire data type is supported.
 Fork – join - use non-blocking assignment to get the
same.
 Primitive - only gate level primitive are supported
 Table - udp and table are not supported.

Question: - What are the various timing violations: setup, hold, width, recovery, remova

9. Describe non/blocking assignments.

10. Race condition in the given code! Give Example.
11. Multiple drivers. Give Example Code
12. Learn writing codes for State Machines (FSM).
13. Draw Timing Diagrams for given code/ckt.
14. Inferrence of design blocks (latches, ff etc)

Question: - Define timescale?

Answer: - A time scale specifies divisions of time, in Verilog `timescale

is used for specifying
the reference time unit for the simulator. Syntax of the `timescale is as below:

`timescale <reference_time_unit>/<time_precision>

example : `timescale 10ns/1ns

Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation.

15. Automatic task/functions -- What are?

task m;
--
--
endtask;

module mdl;
--
--
fork
m;
m;
m;
join

1 module re_entrant_task();
2
3 task automatic print_value;
4 input [7:0] value;
5 input [7:0] delay;
6 begin
7 #(delay) $display("%g Passed Value %d Delay %d", $time, value,
delay);
8 end
9 endtask
10
11 initial begin
12 fork
13 #1 print_value (10,7);
 14 #1 print_value (8,5);
15 #1 print_value (4,2);
16 join
17 #1 $finish;
18 end
19
20 ndmodule

Question: - Tertiary operator, how will it look after synthesis?

Answer: - It will act like Mux.

16. Verilog code for clock generation(wrote).

17. What is initial block, Whether it can be kept in designs(No, cauz can not be synthesized).
18. assign out = sel?in1:in2; // How out will respond to sel = X? // I think out should go X
19. always@(sel or in1 or in2)
20. if(sel)
out = in1;
else
out = in2;
//How out will respond to sel = X? Should go to else block!!!