State Machine:

1. Mealy Vs Moore state machines?

2. State machine to detect a pattern. For Example 10110.
3. State Machine for a Car Indicator(Blinker) system
4. Design a FSM (Finite State Machine) to detect more than one "1"s in last 3 samples.
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0
5. To enter the office people have to pass through the corridor. Once someone gets into the office
the light turns on. It goes off when no one is present in the room. There are two registration
sensors in the corridor. Build a state machine diagram and design a circuit to control the light.

6. Design a logic which mimics an infinite width register. It takes input serially 1 bit at a time. Output
is asserted high when this register holds a value which is divisible by 5. KEY: You can make such
ckt not only for 5 but for any number.
7. How can "X"s be used to debug state machines?
8. Where we can use one hot state machine?
9. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that
results in heads.
10. Design a Pattern matching State Machine. Output is asserted if pattern "101" is detected in last 4
inputs. How will you modify this design if it is required to detect same "101" pattern anywhere in
last 8 samples?
11. Design a finite state machine to behave like a modulo 3 counter when x = 0 and modulo 4 when
x=1.
12. What is a modulo operator? Why do we call a Modulo-N Counter?
13. Asynchronous FIFO Controller with full and empty flags.
14. Calculate a Sync FIFO depth for the following spec. Input data rate = 80 clocks
continuous data and 20 clocks idle. Output data rate = 8 clocks data and 2 clocks
idle. ANSWER is as Below

Worst write can be as follows:

<-20-><-80->|<-80-><-20->
First burst | second burst

Here, effective writing is only for 160 clock cycles, So worst write is 160 words/160 clks.

Now, Read speed is 8 words/ 10 clk cycles.

So, in 160 (16 * 10) read clk cycles, we can read 128(16 * 8 ) words. remaining words we
 need to store in fifo. that is 32(160 - 128).
In 10 cycles -> 8 reads are possible, hence in 160 cycles -> 128 reads are possible. But
writes in 160 cycles are 160, hence the FIFO depth should e 160-128 = 32.
So, I guess fifo depth need to be 32 only...

15. Why do we need grey code for the dual clock FIFO design?
16. FIFO Depth Calculation: Write clock is 4 times faster than Read clock. There will
be only one write once in 4 write clocks, but can be any clock of 4 clocks. Where
as Read will happen every clock. What will be the minimum depth for the Full and
Empty condition wont be asserted.
17. simplify this : (A + B) (A + Bbar)
18. What’s the diff between a half and a full adder?
19. How to do the signed multiplication using an unsigned multiplier?
20. swap x and y.
x=x-y;
y=x+y;
x=y-x;
or
X = X ^ Y;
Y = Y ^ X;

X = X ^ Y;

21. Implement a divide by two circuit.

22. Grey to binary and binary to grey code conversion.
23. Transfer a signal of one clock from a slow clock to a fast clock.
24. Transfer a signal of one clock from a fast clock to a slow clock.
25. Divide by 3 clock generation with 50% duty cycle.
26. Divide by 1.5 and 2.5 clock generation.
27. AND, OR and XOR function using a MUX.
28. How to synchronize control signals and data between two different clock domains?
29. Design a logic circuit to compare a 4’bit wide signal to be greater than or equal to
4’h8.
30. The circle can rotate clockwise and back. Use minimum hardware to build a
circuit to indicate the direction of rotating.
31. Big benefit of XOR?(Data+ code word <=> Data)
32. Design a logic for glitch free clock mux.
33. Design a block which has 3 inputs as followed.
system clock of pretty high freq
asynch clock input P
asynch clock input Q
34. P and Q clocks have 50% duty cycle each. Their frequencies are close enough
and they have phase difference. Design the block to generate these outputs.
 PeqQ : goes high if periods of P and Q are same
PleQ : goes high if P's period is less than that of Q.
PgrQ : goes high if P's period is greater than that of Q.

35. Design a black box whose input clock and output relationship as shown in
diagram.

__ __ __ __ __ __ __ __ __
clk __| |__| |__| |__| |__| |__| |__| |__| |__| |__

__ __ __ __ __
Output __| |______| |______| |______| |______| |__

36. Design a digital circuit to delay the negative edge of the input
signal by 2 clock cycles.
__________
input ________| |_____________
_ _ _ _ _ _ _ _ _ _ _ _ _
clock _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
______________
output _________| |___________
37. Design a 4:1 mux using 2:1 mux.
38. Design a 2 bit comparator with GT, EQ and LT.
39. Design a Toggle flop using a D type flop.
40. F = wx’y’ + yw’z’ + yxz + yxw. Implement this function using a mux.
41. Design a JK flop using a Toggle flop.
42. Give two ways of converting a two input NAND gate to an inverter.
43. How do you detect if two 8-bit signals are same?
44. What is a carry save adder?
45. How do you design a carry select adder?
46. Design a logic for 15B/8.
47. Design AND, OR, NAND, NOR, NOT, XOR, XNOR gates using 2:1 MUX.
48. Frequency Dividers (1/2, 1/3, 1/5 etc.)
49. Frequency Multiplier.
50. Setup Time Calculagtion Questions.
51. Hold Time Calculagtion Questions.
52. Counters, Modulo-N Counters
53. Adders, Half Adders, Carry Save Adders, Look Ahead Carry Generator.
54. Multipliers.
55. How to achieve AB'+BA', Using NAND gates only.
56. Generate clock using:
-- T FF
-- D FF
57. If there is a data-write-read mismatch in FIFO (DWRITE Vs DREAD), what can be the
cause?
58. FIFO Depth questions.
59. Coverage is 60%. How will you improve functional coverage.
- Directed testcases
 - exclude option
- run more tests with different seeds
60. Why we avoid latches in the design:

Inferred Latches: Are result of incomplete if/case constructs etc. As such latches will
unnecessarily eat up Area… So to avoid this we try to avoid any code that would infer into
latches.
Latches in place of FFs: Can be used in asynchronous ckts.. that too with some extra logic to
suppress the glitch on enable. Smaller in size as compared to FFs(Master-Slave). We don’t have
Scanable Latches so not recommended for a design that require DFT support.

61. How Latch is level triggered and flop is edge triggered?

62. Implement a logic that would shift the given input value by the given shift value?
63. Barral Shifter??
64. 2-Way switch. (Reduced version of what you asked that day)
65. Half-Adder, truth table, implement using gates(Done).
66. Difference between T and D flip-flop(Told).
67. Mealy-Moory FSM (Told)
68. One question on Decoder(Told).
69. Sync-Asynch Reset(Told)
70. Identify the circuit below, and its limitation.

71. What is the current through the resistor R1 (Ic) ?

72. Referring to the diagram below, briefly explain what will happen if the propagation
delay of the clock signal in path B is much too high compared to path A. How do we
solve this problem if the propagation delay in path B can not be reduced ?
73. What is the function of a D flip-flop, whose inverted output is connected to its input ?
74. Design a circuit to divide input frequency by 2.
75. Design a divide-by-3 sequential circuit with 50 duty cycle.
76. Design a divide-by-5 sequential circuit with 50 duty cycle.
77. What are the different types of adder implementations ?
78. Draw a Transmission Gate-based D-Latch.
79. Give the truth table for a Half Adder. Give a gate level implementation of it.
80. What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a
buffer ?

81. What is the output of the circuit below, assuming that value of 'X' is not known ?

82. Consider a circular disk as shown in the figure below with two sensors mounted X, Y and
a blue shade painted on the disk for an angle of 45 degree. Design a circuit with minimum
number of gates to detect the direction of rotation.
83. Design an OR gate from 2:1 MUX.
84. Design an XOR gate from 2:1 MUX and a NOT gate

85. What is the difference between a LATCH and a FLIP-FLOP ?

• Latch is a level sensitive device while flip-flop is an edge sensitive device.
• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to
glitches.
• Latches take less gates (also less power) to implement than flip-flops.
• Latches are faster than flip-flops.
86. Design a D Flip-Flop from two latches.

87. Design a 2 bit counter using D Flip-Flop.

88. What are the two types of delays in any digital system ?
89. Design a Transparent Latch using a 2:1 Mux.

90. Design a 4:1 Mux using 2:1 Muxes and some combo logic.
91. What is metastable state ? How does it occur ?
92. What is metastability ?
93. Design a 3:8 decoder
94. Design a FSM to detect sequence "101" in input sequence.
95. Convert NAND gate into Inverter, in two different ways.
96. Design a D and T flip flop using 2:1 mux; use of other components not allowed, just the
mux.
97. Design a divide by two counter using D-Latch.
98. Design D Latch from SR flip-flop.
99. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
100. What is Race Condition ?
101. Design a 4 bit Gray Counter.
102. Design 4-bit Synchronous counter, Asynchronous counter.
103. Design a 16 byte Asynchronous FIFO.
104. What is the difference between an EEPROM and a FLASH ?
105. What is the difference between a NAND-based Flash and a NOR-based Flash ?
106. You are given a 100 MHz clock. Design a 33.3 MHz clock with and without 50%
duty cycle.
107. Design a Read on Reset System ?
108. Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.
109. Design a State machine for Traffic Control at a Four point Junction.
110. What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to
make it asynchronous FIFO ?
111. How can you generate random sequences in digital circuits?
112. assign out = sel?in1:in2; // How out will respond to sel = X? // I think out should go X
113. always@(sel or in1 or in2)

if(sel)

out = in1;

else
 out = in2;

//How out will respond to sel = X? Should go to else block!!!

114. What will happen if the select pin goes X in a Mux?

115. - 3 situations were given, one with if else conditions, one a ternary operator and
another a harware Mux with 2 i/ps and select pin..
116. What if 1 bit in the mux select is X?
117. Timing diagram of clk/enable and i/p. Draw the o/p of a latch and flop.
118. 4 NOT gates in parallel looped back from the last NOT gate. What is the value at the
o/p of last NOT gate
119. Draw the interior of a Mux? Find using truth table and K Map.
120. Draw the internal of latch. How does latch work? How is it different from the flop/
121. Write the truth table of latch and run the values to analyse the truth table.