ECE3004 Microprocessors and Microcontrollers

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8086 Memory Interfacing

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 8086 system configuration:
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 Memory chip:

WR RD
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ADDRESS PINS A0-An-1 In ROM chip

Memory •Read pin is OE’
RAM •No WR’ pin

CS
(Chip select) D0-D7

❖No. Address pins = n

Data Pins ❖No. of data pins = 8
❖Control signals=OE’, RD’ and WR’
❖Chip select signal = CS’
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 8086 Memory Interfacing:

➢ 8086 has 20 address lines, so a total of 1MB memory space can be

interfaced. Various types of memory chips such as RAM, ROM,
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EPROM, etc. may be connected within this space.

➢ The number of memory chips and the address space used will
depend on the application needs.

➢ It is not necessary that the address space of any

microprocessor system should start only from 00000.

➢ After reset processor starts from the address FFFF0H because

CS = FFFFH and IP=0000H. Hence this address must lie in the
address range of EPROM.

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 Hardware connection of the memory signals with the
system signals:

Memory signals System signals

Data pins Data bus (D0-D7) and (D8-D15)
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Read signal (RD’) Memory read control signal

Write signal (WR’) Memory write control signal
n no. of address pins of memory connected
Address pins with n no. of address pins of microprocessor
from LSB i.e from A1 address pins
Unused higher order address lines ,A0 and
Chip select signal (CS’) BHE’ signals of microprocessor decoded
externally to generate the chip select
signal
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 Assume starting
No. of address pins in No. of memory locations address zero and end
memory chip address for each are
FFH
1FFH
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3FFH
7FFH
FFFH
1FFFH
3FFFH
7FFFH
FFFFH
1FFFFH
3FFFFH
7FFFFH
FFFFFH
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 Interface two 4K X 8 EPROMS and two 4K X 8 RAMS chips with
8086 . Select suitable maps.

We know that, after reset , the IP and CS are initialized to form address
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FFFF0H. Hence this address must lie in the EPROM.

The address of RAM may be selected any where in the 1MB address space
of 8086.

In this case RAM address is select such that the address map of the system is
continuous.

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 A1-A12 of 8086
CS1’ CS2’

A0 A0
ROM1 ROM2
4K X 8 A11 A11 4K X 8
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OE’
MEMR’ OE’
MEMR’
D0-D7 D0-D7
D8-D15 D0-D7

DATA BUS (D0-D15)

D8-D15 D0-D7

D0-D7 D0-D7

A0 A0
RAM3 RAM4
4K X 8 A11 A11 4K X 8
MEMR’ RD’ RD’ MEMR’

A1-A12 of 8086
MEMW’ WR’ CS3’ CS4’ WR’ MEMW’

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 Unused address lines of the processor: A13 to A19
Memory bank enable signals: A0 and BHE’
Above signals will be decoded to generate chip select signals for the memory
chips. (CS1’, CS2’, CS3’ and CS4’)
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To design the chip select signal decoding circuit memory mapping address for
ROM and RAM chips are required.
❖ ROM chips must be mapped from the address FFFFFH.
❖ In this case select the RAM address in such that the address
map of the system is continuous.
MEMORY MAPPING ADDRESS CALCULATION FOR ROM AND RM CHIP
❖ If end address of ROM space is FFFFFH and since the size
of ROM space is 2X4KB = 8KB, so starting address of ROM
space is FFFFFH-1FFFH = FE000H
❖ So the end address of RAM space is FE000H – 1 =
FDFFFH and starting address is FDFFFH – 1FFFH =
FC000H.
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 MEMORY MAPPING TABLE
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❖1MB address space provided by the 8086 are 00000H to FFFFFH

❖Used address space by the memory system are FC000H to FFFFFH

Unused address lines are always fixed values

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 ADDRESS DECODING CKT OR CHIP SELECT SIGNAL
GENERATION CKT USING DECODER

This circuit can be design in different types.

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➢Using logic gates only

If no. of memory chips increased then no. of gates also increased.

➢Separate decoder for high- and low-order banks

➢Single decoder for both the banks

Using decoder more no. of memory chips can be interfaced easily.

Some logic gates are used along with decoder to design the circuit.

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 ADDRESS DECODING CKT OR CHIP SELECT SIGNAL
GENERATION CKT USING DECODER
A18 IC NO.74138
A19 IC NO.7432
1
A16 0 A0 CS4’
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A17 0
BHE’ CS3’
A13
A14 A0 CS2’
A 15

BHE’ CS1’
A19 A18 A17 A16 A15 A14 A13 DECODER A0 BHE’ ODD/
O/P EVEN CHIP
1 1 1 1 1 1 1 Y7=0 0 1 EVEN ROM /CS2’=0
1 1 1 1 1 1 1 Y7=0 1 0 ODD ROM/ CS1’=0
1 1 1 1 1 1 0 Y6=0 0 1 EVEN RAM/ CS4’=0
1 1 1 1 1 1 0 Y6=0 1 0 ODD RAM/ CS3’ = 0
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 ADDRESS DECODING CKT OR CHIP SELECT SIGNAL
GENERATION CKT USING gates only

0
A19 0 0 CS1’=0
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A13 0
For ROM chips 0 CS2’=0

0
0 CS4’=0
A19
0
A13 0
0 CS3’=0
For RAM chips

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 Refer ch-5 of the below textbook for some more memory
interfacing examples
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 VIT BHOPAL UNIVERSITY

You
Thank

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