Technical Article

How to Get the Best

Results Using LTspice for
EMC Simulation—Part 1
Richard Anslow, System Applications Engineer, Analog Devices
Sylvain Le Bras, Field Applications Engineer, Würth Elektronik

Abstract Solving Emissions and Immunity Problems

As technological innovations such as IoT connected devices and 5G con- Using LTspice
nectivity become part of our everyday lives, so too does the need to regulate After reading this article you should be able to answer the following key
the electromagnetic emissions from these devices and quantify their questions:
immunity to EMI. Meeting EMC compliance targets is often a complex task.
(a) Is my system likely to pass EMC testing? Shall I keep an extra footprint for
This article provides open-source LTspice® simulation circuits to answer
a common-mode inductor, a filter inductor, or a capacitor? After reading this
key questions: (a) will my system pass EMC testing, or do I need to add mitiga-
article you should be able to use LTspice to plot differential and common-mode
tion techniques? and (b) how immune is my design to noise from the external
noise in your buck converter power design and show how the circuit passes or
environment?
fails conducted emissions standard limits, as shown in Figure 1.

Why Should I Use LTspice for EMC Simulation? (b) Is a linear regulator needed to provide stable voltage to my sensitive load?
After reading this article you should be able to use LTspice to understand if an
Design for EMC should follow the product release schedule as closely as possible,
LDO regulator is required on the output of your buck converter based on the
but this is often not the case, as EMC problems and lab testing can delay product
buck output ripple voltage level tolerable in your design. In addition, this article
release for months.
provides a configurable power supply noise immunity, or PSRR, test circuit.
Usually, simulation focuses on the functional aspects of an electronic device; how-
500000*V(v1,v2) 500000*(V(v2)+V(v1))
ever, a simple and open-source tool such as LTspice can also be used to simulate 120 dB
the EMC behavior of any device. With many of us working from home, and EMC lab
costs at a premium (up to $2000 daily), accurate EMC simulation tools are even 100 dB
more useful. Spending a few hours simulating EMC failures and circuit fixes helps Common-Mode
to avoid multiple lab test iterations and expensive hardware redesigns. 80 dB Conducted
Emissions
Noise

Limit Line
To be useful, an EMC simulation tool needs to be as accurate as possible. This
60 dB
article series provides some guidelines and LTspice EMC circuit models that are
simulated and well matched to real lab measurements.
40 dB
This is Part 1 of a series of three articles that provide EMC simulation models
Differential-Mode
for an example sensor signal chain, with a MEMS vibration sensor at its core. 20 dB Noise
However, many of the components and EMC simulation techniques are not
unique to MEMS solutions and can be used across a broad range of applications. 0 dB
100 kHz 1 MHz 10 MHz
X Part 1: power supply components and conducted emissions and immunity. Figure 1. LTspice plot of differential and common-mode noise, with conducted emissions limit line.
X Part 2: signal integrity and transient robustness on cable drive transceiver links.
X Part 3: signal conditioning components and boosting immunity to exter-
nal noise.

VISIT ANALOG.COM
Buck Converter for Sensors LTspice Test Circuit with Würth
MEMS vibration sensors are typically housed in small metallic enclosures, REDEXPERT Data
usually 20 mm to 30 mm in diameter and 50 mm to 60 mm in height. Sensors The output ripple voltage of a buck converter is a function of the capacitor
with digital signal chains are typically supplied with 9 VDC to 30 VDC over long impedance and the inductor current. For better simulation accuracy, Würth
cables and consume less than 300 mW. Tiny power solutions are required to fit REDEXPERT can be used to choose a 4.7 µF output capacitor (885012208040) and
inside this small enclosure, with high efficiency and wide input range. extract the ESR and ESL over frequency. The ESL and ESR are sometimes loaded
into the LTspice capacitor model, but a quick check will demonstrate that ESL is
The LT8618, LT8618-3.3, and LT8604 are compact, high speed step-down switch-
often omitted in LTspice capacitor data. Figures 3a and 3b show two equivalent
ing regulators ideally suited to MEMS sensor applications. LTspice models
circuits: (a) with the 4.7 µF output capacitor, and discrete ESL and ESR values,
are already available for LT8618 and LT8618-3.3. The regulation of the LT8618
and (b) with the Würth capacitor that includes ESR and ESL parameters.
provides very low output ripple with less than 10 mV p-p. However, parasitic
resistance and inductance of the output capacitor bank can increase this ripple, R4
100 kΩ
resulting in unwanted conducted emissions from the buck circuit. Parasitics can IN
VIN PG
V1
occur due to capacitive load, buck regulator output switching parasitics, and U1
24 V EN/UV BST C3
coupling capacitance between the PCB design and the sensor enclosure. C2 47 nF
1 µF OUT
INTVCC SW
Extracting and Using Parasitic Values C1 L1 RLOAD
47 µH L2
10 nF 0.781 nH 200 Ω
TR/SS Bias R2
The next sections describe how an engineer can extract the ESL and ESR LT8618 1.62 MΩ
VESR
R5
Rt FB 3.82 mΩ
parasitic values from real capacitors using Würth REDEXPERT and simulate the R1 GND
VCAP
18.2 kΩ R3 C4
circuit using LTspice. At the input and output of many systems, capacitor and 301 kΩ 4.7 µF
inductor parasitics play a major role in EMI performance. Splitting the individual .tran 0 5m 4990 μs startup

parasitic contributions helps the user to make the best choice when it comes (a)

to reducing the system output ripple. R4

IN 100 kΩ
VIN PG
Conducted emissions simulation for a buck converter is discussed with an V1
U1
24 V
LTspice and Würth REDEXPERT process flow, as shown in Figure 2. Usually for C2
EN/UV BST C3
47 nF
a buck, output ripple is associated with signal-to-noise ratio (SNR), while input 1 µF
INTVCC SW
OUT
L1
ripple is tightly linked to EMC performance. C1
10 nF 47 µH C4 RLOAD
4.7 µF 200 Ω
TR/SS Bias R2
After the Figure 2 simulation approach is outlined, this article then provides LT8618 1.62 MΩ
Rt FB
real lab measurements and simulation correlation using the DC2822A LT8618 R1 GND
18.2 kΩ R3
demo board. 301 kΩ
.tran 0 5m 4990 μs startup

LTspice Buck Converter: Use Würth REDEXPERT: EMC Accurate Capacitor from Würth
LT8618 and Open To Get and Add Accurate ESL
Predrafted Test Circuit and ESR Values for Output
Capacitor (EMI Source) (b)

Figure 3. LTspice test circuits, (a) with the 4.7 μF output capacitor, and discrete ESL and ESR
Fix that Buck Converter: values and (b) with the Würth capacitor that includes ESR and ESL parameters.
Add Würth Common-Mode
Choke to LTspice
REDEXPERT displays the impedance over frequency of many components,
Match Simulation to Reality: LISN Circuit: enabling determination of the key parasitics of each passive device. These
Scale Plots to dBµV in LTspice, and Use Predrafted LTspice Model
Load EMC Limit Lines into LTspice, Provided in this Article to parasitic values can later be implemented in LTspice models, enabling individual
and Define a Frequency Range Measure Noise from the Circuit
evaluation of contribution to total voltage ripple.
Figure 2. Process flow for simulating conducted emissions using LTspice.

Figure 4. An FFT plot showing individual contribution to frequency spectrum due to pure capacitance, ESL and ESR of a 4.7 µF capacitor.

2 How to Get the Best Results Using LTspice for EMC Simulation—Part 1
As mentioned previously, the LT8618 provides very low output ripple with less DM noise is produced between the supply line and the return line, while CM noise is
than 10 mV p-p. However, when simulating the effects of capacitive load and produced between the supply lines and the ground reference plane (such as a
ESL, the output ripple voltage is 44 mV p-p. The capacitor ESL contributes copper test table) via stray capacitance, CSTRAY. CSTRAY in effect models the switching
significantly to noise over frequency, as is shown in the Figure 4 FFT plot. noise parasitics at the buck converter output.

Assessing EMI Compliance at Buck Input Using The LTspice LISN circuit corresponding to Figure 6 is shown in Figure 7. For
greater simulation accuracy the L5 and L6 inductors are used to model the
an LTspice LISN Circuit
inductance of LISN supply leads to the test circuit. Resistor R10 models the
To evaluate EMC compliance in conducted setups, most standards rely on a line impedance of the test board’s slotted ground plane. Figure 7 also includes the
impedance stabilization network (LISN) or artificial mains network (AMN). These capacitor C10 used to model CSTRAY. Capacitor C11 models parasitic capacitance
devices have a similar function and are placed between the circuit power supply between the sensor PCB and the sensor mechanical enclosure.
and device under test (DUT), here the buck converter. The LISN/AMN consists
of low-pass and high-pass filters. The low-pass filters provide a path for low When running simulations, LTspice should be set up to help your LISN circuit
frequency power (DC to a few hundred Hz) to the DUT. The high-pass filters reach steady state faster, as the wrong selection of start-up conditions can
are used to measure supply and return supply line noise. These voltages are lead to long lasting oscillations.
measured across 50 Ω resistors, as illustrated in Figure 5 and Figure 6.1 In Make sure that you untick Start External DC Supply Voltages at Zero and specify
a real lab, this voltage is measured using an EMI receiver. LTspice can be an Initial Condition (of voltage and current) of circuit elements if needed.
used to probe the noise voltages and plot over the conducted emissions test
frequency spectrum. L3
50 µH
L6
900 nH
IN1
2× Low-Pass C7 C5
Filters 8 µF 250 nF
V1
IN V2 R9
DUT R6
PULSE 5Ω 50 Ω
(0 24 1 µs C12
100 µs 0 1) 22 µF
R7
R8 50 Ω
5Ω V2
2× High-Pass
Filters C8 C6
8 µF 250 nF
A B
IN2
L4 L5 R10
EMI Receiver 50 µH 900 nH 1 mΩ

Figure 5. LISN placed between power supply and device under test (DUT). R4
100 kΩ
IN1 VIN PG
U1 C10
5 pF C11 Sensor to Enclosure Parasitics
EN/UV BST C10 CSTRAY from Buck Output
C2 C3
++ 1 µF 47 nF L1 Würth 744031330 33 µH
INTVCC SW
50 Ω V1 C1 L1
10 nF 33 µH L2
Power –– TR/SS Bias R2 0.781 nH
Supply 1.62 MΩ
–
– LT8618 VESR RLOAD1
Rt FB R5 200 Ω
50 Ω V2 R1 GND 3.82 mΩ
CSTRAY 18.2 kΩ R3 VCAP
+ 301 kΩ C4
4.7 µF
+ IN2
C11
LISN Buck Converter 100 pF
.tran 0 5000u 4900u startup uic

Figure 7. LTspice LISN circuit, LT8618 buck converter, and parasitic modeling.
CM Path Ground Plane in CE Test
DM Path Converter Reference Ground Figure 8 shows the CM and DM noise using an LTspice FTT plot measured from the
LISN terminals V1 and V2. To reproduce the arithmetic operations shown in
V1 = VCM + VDM V1 + V2 V1 – V2
VCM = ; VDM =
V2 = VCM – VDM 2 2 Figure 6, the V1 and V2 are subtracted and multiplied by 0.5 for the DM noise,
and V1 is added to V2 with the result multiplied by 0.5 for the CM noise.
Figure 6. Representation of common- and differential-mode interference inside an LISN.1
Typically conducted emissions in a lab are measured in dBµV, while the default
Conducted emissions can be classified as common-mode (CM) noise and
LTspice unit is 1 dbV. The relationship between the two is 1 dbV = 120 dBµV.
differential-mode (DM) noise. It is important to distinguish between CM and DM
noise, as EMI mitigation techniques may be effective for CM but not for DM noise The LTspice expression for DM noise in dBµV is thus
and vice versa. As both V1 and V2 voltages are outputted at the same time,
V(v1,v2)×0.5×1000000 (1)
an LISN can be used to separate out CM and DM noise in conducted emissions
testing, as shown in Figure 6.1 and the expression for CM noise is
(V(v2)+V(v1))×0.5×1000000 (2)

VISIT ANALOG.COM 3
 Figure 11 shows the conducted emissions limit line, and the DM and CM conducted
emissions from the buck circuit. The circuit fails emissions testing in the
500000*V(v1,v2) 500000*(V(v2)+V(v1))
120 dB 2.3 MHz to 30 MHz frequency band.
500000*V(v1,v2) 500000*(V(v2)+V(v1))
100 dB 120 dB

80 dB 100 dB

60 dB 80 dB

40 dB 60 dB

20 dB 40 dB

0 dB 20 dB
100 kHz 1 MHz 10 MHz
Figure 8. LTspice FFT plot for DM noise (black) and CM noise (blue).
0 dB
100 kHz 1 MHz 10 MHz
Adding Conducted Emissions Limit Lines Figure 11. LTspice FFT plot and EN 55022 conducted emissions limit line.
The LTspice FFT waveform viewing parameters can be edited using the plot
settings file. Using the LTspice FFT menu, navigate to Save Plot Settings and hit Fixing the Buck Converter EMI
save. The plot settings file can be opened using a text editor and manipulated To reduce the DM noise from the circuit, a very low ESL and ESR capacitor can be
to add the EN 55022 conducted emissions limit line as well as the relevant EMC placed at the input rail, such as the C12 22 µF Würth 885012209006, as shown in
frequency range (10 kHz to 30 MHz) and amplitude (0 dBµV to 120 dBµV). Figure 12.
The EN 55022 conducted emissions standard frequency and amplitude limits can To reduce CM noise, a Würth common-mode choke, such as the 250 µH 744235251
be manipulated using Excel to provide the correct syntax to copy and paste to the (WE-CNSW series), can be chosen from the LTspice library. The package size of
LTspice plot settings file, as shown in Figure 9. The line definition can be 4.5 mm × 3.2 mm × 2.8 mm is ideal for space constrained MEMS sensor enclosures.
pasted to the plot setting parameters as shown in Figure 10. Figure 10 also Figure 13 shows the FFT plot of the fixed buck.
shows the X frequency and Y amplitude parameters.
L3 L6
50 µH 900 nH
IN1
C7 C5
8 µF 250 nF L7
V1 1812_744235251
IN V2 R9 _10000ohm
R6
PULSE 5Ω 50 Ω
(0 24 1 µs C12
100 µs 0 1) 22 µF
R7
R8 50 Ω
Figure 9. Generating the right syntax to copy and paste to the LTspice plot settings file. 5Ω V2
C8 C6
8 µF 250 nF
IN2
L4 L5 R10
50 µH 900 nH 1 mΩ
R4
100 kΩ
IN1 VIN PG
U1 C10
5 pF C11 Sensor to Enclosure Parasitics
EN/UV BST C10 CSTRAY from Buck Output
C2 C3 L1 Würth 744031330 33 µH
1 µF 47 nF
INTVCC SW
C1 L1
10 nF 33 µH L2
TR/SS Bias R2 0.781 nH
1.62 MΩ
LT8618 VESR RLOAD1
Rt FB R5 200 Ω
R1 GND 3.82 mΩ
18.2 kΩ R3 VCAP
301 kΩ C4
4.7 µF
IN2
C11
100 pF
.tran 0 5000u 4900u startup uic

Figure 12. Fixing the buck converter emissions.

Figure 10. Adding the conducted emissions pass/fail line definition and frequency/
magnitude scales.

4 How to Get the Best Results Using LTspice for EMC Simulation—Part 1
 V(v1,v2)*500000 (V(v2)+V(v1))*500000 The DC2822A demo board includes two power inputs, VIN and VEMI. The VIN
120 dB
input power rail bypasses the ferrite bead used on the PCB. The Figure 15 LTspice
100 dB
model corresponds to the demo board VIN configuration. Figure 16 shows the
FFT of the LTspice simulation, with common-mode emissions narrowly failing the
80 dB
conducted emissions limit line at 2 MHz.
V(vanalyseur, (V(vanalyseur2)+
vanalyseur2)*500000 V(vanalyseur2))*500000
60 dB 120 dB

40 dB 100 dB

20 dB 80 dB

0 dB 60 dB
100 kHz 1 MHz 10 MHz
Figure 13. An FFT plot with buck converter fixed.
40 dB

Real Lab Measurements and Simulation

Correlation Using the DC2822A LT8618 20 dB

Demo Board
0 dB
This article has provided guidance for using LTspice for conducted emissions 100 kHz 1 MHz 10 MHz
simulation. The methods can be used for any buck converter circuit. Now we Figure 16. LTspice FFT plot corresponding to the DC2822A VIN configuration.
turn our attention to simulation and EMC lab correlation using the DC2822A
To reduce simulation time and to optimize matching the LTspice simulation to the
LT8618 demo board, shown in Figure 14. The DC2822A demo board includes
DC2822A demo board lab measurements, the following changes were made to
several input and output capacitors, which were not included in previous
Figure 15 compared to previous models (Figure 7 and Figure 12):
simulation models (for example, Figure 7 and Figure 12). The LTspice model
shown in Figure 15 includes these capacitors and the capacitor ESL and ESR X No need to model 100 pF capacitance between enclosure casing and PCB.
values obtained using Würth REDEXPERT. We are just modeling a DC2822A demo board.
X Assuming from the outset that the switching noise is negligible on this well-
designed PCB. Previously we estimated 5 pF for switching noise in Figure 7
and Figure 12.
X Ignoring the very small inductance of the wire leads between the LISN and
the DC2822A demo board.
X Adding 1 kΩ resistors in parallel with the 50 µH LISN inductors to reduce
simulation time (the LISN settling time is reduced).

With these changes in the Figure 15 circuit, Figure 17 shows a comparison of

the LTspice simulation and actual measurement of the DC2822A demo board
in an EMC lab. The LTspice simulation model predicts the actual lab emissions’
major peaks with excellent accuracy.

Figure 14. DC2822A LT8618 demo board.

L2
50 µH

Vanalyseur
CLISN3 R4
CLISN1 R5 250 nF 49.9 kΩ
8 µF 1500 Ω Vanalyseur VIN PG
L4 R12
1 MΩ U1
V2 R10 R6 C4
5Ω R11 R17 R16 R15 R14 R13 EN/UV BST 0.22 µF
IN 12.5 V 50 Ω 0.0001 Ω 25 mΩ 25 mΩ 0.754 Ω 25 mΩ 25 mΩ C2
1 µF OUT
INTVCC SW
C7 L1
R8 10 nF R18 R19
R9 50 Ω Vanalyseur2 L9 L8 L7 L6 L5 33 µH
6e-11 2.53e-10 1 nH 2.53e-10 6e -11 TR/SS Bias R2 7 mΩ 5 mΩ
5Ω 1 MΩ
R7
CLISN2 1500 Ω CLISN4 LT8618 L10 L11 RLOAD
8 µF Rt FB 1.5e-10 1.5e-10 50 Ω
250 nF C12 C3 C10 C1 C13 R1 GND
0.1 µF 1 µF 22 µF 1 µF 0.1 µF 18.2 kΩ R3
187 kΩ C9 C6
Vanalyseur2 4.7 µF 10 µF
L3
50 µH
.tran 0 4.5m 4.4m

Figure 15. LTspice model corresponding to the DC2822A demo board VIN configuration.

VISIT ANALOG.COM 5
 70 IEC 61000-4-6: Immunity to Conducted Disturbances,
LTspice Coupled to the Power Supply Cable
EMC Scan Frequency Range Sweep 10 kHz to 80 MHz
60
LT3042
50 SINE Input IN U1
(0 0.5 {freq}) V2
–
Amplitude (dBµV/m)

40 + Output
V3 EN/UV
OUT C2 RLOAD
5V R1
200 kΩ OUTS 4.7 µF 16.5 Ω
30
PG R2
SET GND ILIM PGFB 450 kΩ
20 C1 .tran 0 0.02 0.01
4.7 µF R4 R3
RPAR = 33.2 kΩ 499 Ω 50 kΩ
10

0 .meas TRAN Outripple PP V(output) from 0 s to 0.01 s

.meas TRAN Inripple PP V(input) from 0 s to 0.01 s
.meas TRAN PSRR PARAM 20*log10(Inripple/Outripple)
–10 .step dec param Freq 10 kHz 80Mega 6
1.00E+06 1.00E+07 Figure 18. Simulating the PSRR of the LT3042 LDO regulator over 10 kHz to 80 MHz.
Frequency (Hz)
Figure 17. DC2822A VIN configuration, comparison of LTspice and actual EMC lab emissions. Figure 18 contains several powerful statements. The combination of .meas and
.step statements enables the user to add a voltage noise source at the LDO
With the ferrite bead (EMI filter) VEMI rail measurement, the DC2822A demo board
input, and measure the LDO PSRR over a stepped change in voltage input
easily passes the conducted emissions limit line of 60 dBµV. In fact, at lower
over frequency.
frequencies the DC2822A demo board only has 30 dBµV to 35 dBµV of emissions.
.meas Statements
Conducted Immunity This allows the user to measure the peak-to-peak value of a signal over a time
Wired condition monitoring sensors have stringent noise immunity requirements. frame and output it to the SPICE Error Log. Figure 18 measures both input
For CbM of railway, automation, and heavy industry (for example, pulp and and output ripple, and calculates the PSRR of the measured data. All of this is
paper processing), vibration sensor solutions need to output less than 1 mV of outputted to the SPICE Error Log.
noise to avoid triggering a false vibration level at the data acquisition/controller.
This means that the power supply design needs to output very little noise (low .step Statements
output ripple) into the measurement circuit (MEMS signal chain). The power The .step command is useful for sweeping a variable across a range of values
supply design must also be immune to noise coupled to the power supply cable in a single simulation run. The .step statement in Figure 18 steps the V2 voltage
(high PSRR). source sine wave across a 50 Hz to 10 MHz range.
As shown previously, the LT8618 can have tens of millivolts of output ripple due to The C2 output capacitor initial voltage can be set to 3.3 V to speed up settling
nonideal capacitive loads and burst operation. For MEMS sensor applications, (and simulation) time. This is done by editing the capacitor properties, and it
the LT8618 requires an ultralow noise and high PSRR LDO regulator at its output, can be made even faster by disabling the Start External DC Supply Voltage at 0 V
such as the LT3042. option in LTspice.

Flexible Simulation Circuit for Noise Immunity Using the SPICE Error Log
(PSRR) Once the simulation completes, right-click one of the windows, select view and
The LTspice circuit shown in Figure 18 can be used to simulate the PSRR of the select SPICE Error Log (or use the Ctrl+L hotkey). The SPICE Error Log contains
LT3042. The time domain transient model shown in Figure 18 is an alternative data points for the .meas statements.
to the AC sweep method. This time domain model is more flexible than an AC
To plot the .meas data, right-click the error log and select the plot step’ed .meas
method, and even allows the user to simulate the PSRR of a switching regulator.
data, right-click on the blank screen to select Add Trace (or use Ctrl+A) and
The simulation circuit frequency sweeps changes in the voltage input rail and
select PSRR. Right-click the x-axis and check the radio button to display with
simulates the corresponding change in output voltage. In other words, the
logarithmic scale. This will display the PSRR over frequency, as shown in Figure 19.
simulation evaluates the equation: PSRRLT3042 = (change in VIN)/(change in VOUT)
over frequency.

6 How to Get the Best Results Using LTspice for EMC Simulation—Part 1
Some artifacts from the original LT3042 data sheet curve are not visible (about Summary
2 MHz), but the global shape and values are close to the data sheet.
This article provides LTspice simulation circuits and methods to plot differential
PSRR and common-mode noise in your buck converter power design. This article
108
enables the user to plot conducted emissions limit lines and helps to predict
105
EMC lab failures. The simulation approach is validated with lab measurements,
102
with close correlation to the LT8618 DC2822A demo board.
99
96 Using the LT3042 LDO regulator at the output of the LT8618 buck converter
93 provides an ultralow noise, high PSRR solution for MEMS sensor applications. A
90 flexible simulation circuit for PSRR shows good agreement with the LT3042 data
87 sheet. The LT3042 simulates with less than 200 µV output ripple over the 50 Hz to
84 10 MHz range, even in the presence of a large 1 V p-p input voltage noise.
81
78 Acknowledgements
75 The authors would like to thank the Analog Devices Power Products Group and
72 Würth Elektronik for their contributions to this article.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
Figure 19. Plotting the simulated PSRR of the LT3042 LDO regulator.
References
Figure 20 shows the output voltage ripple over frequency. This is less than 200 µV Ling Jiang, Frank Wang, Keith Szolusha, and Kurk Mathews. “A Practical Method
1

over the 50 Hz to 10 MHz range. The input voltage ripple is 1 V p-p over the same for Separating Common-Mode and Differential-Mode Emissions in Conducted
frequency range. The LT3042 provides an excellent PSRR and low noise supply for Emissions Testing.” Analog Dialogue, Vol. 55, No. 1, January 2021.
noise sensitive MEMS solutions.
2
Gabino Alonso. “LTspice: Using .MEAS and .STEP Commands to Calculate
220 µV
Output Ripple Efficiency.” Analog Devices, Inc.
200 µV

180 µV
About the Authors
160 µV
Richard Anslow is a system applications engineer with the Connected Motion
140 µV
and Robotics Team within the Automation and Energy Business Unit at
120 µV
Analog Devices. His areas of expertise are condition-based monitoring
100 µV
and industrial communication design. He received his B.Eng. and M.Eng.
80 µV degrees from the University of Limerick, Limerick, Ireland. He can be reached
60 µV at [email protected].
40 µV
Sylvain Le Bras is a field applications engineer at Würth Elektronik who
20 µV
specializes in power and electromagnetic compatibility. Prior to joining
0 µV
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
Würth Elektronik, Sylvain held various positions in research and development
Figure 20. Plotting the LT3042 simulated output voltage ripple over frequency. at ABB and in technology transfer laboratories. He received his M.Sc.Eng.
from the Polytechnic School of the University of Nantes, France.
The .meas approach using the SPICE Error Log can be used to simulate many
other parameters, including:
X PSRR of a switching regulator Engage with the ADI technology experts in our online support community.
X PSRR vs. dropout voltage vs. frequency Ask your tough design questions, browse FAQs, or join a conversation.
X PSRR vs. bypass network
X RMS output ripple vs. DC input
X Efficiency vs. component value Visit ez.analog.com

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