Technical Article

How to Get the Best

Results Using LTspice for
EMC Simulation—Part 2:
Improving Signal Integrity
Richard Anslow, System Applications Manager, and
Sylvain Le Bras, Field Applications Engineer

Using LTspice for EMC and Signal Integrity Why Should Designers Care about
This is Part 2 of a series of three articles that provide LTspice EMC and signal integrity
® Signal Integrity?
simulation models. In “How to Get the Best Results Using LTspice for EMC Simulation— Signal integrity1 is much more than just having a working link for your prototype.
Part 1”, we provided LTspice simulation tools for power supply components, conducted Even if your link seems to be working, it’s advisable to perform an in-depth check
emissions, and immunity. of your signal quality, for the following reasons:
In Part 2, we will present a combination of LTspice and C-based programs to help the X Reliability: Distance, throughput, and environment might increase the binary
designer understand and improve wired network signal integrity. These tools will help error rate, reaching unacceptable values for the error correction mechanisms
the designer avoid multiple lab test iterations and expensive hardware redesigns. of your system.
Simulation models are provided for compliance with fieldbus communications (RS- X IEEE standard compliance: Compliance with the IEEE recommendations
485, RS-232), high speed backplane (LVDS), the ubiquitous USB standard, and the new ensures seamless interactions between members of the network.
single-pair Ethernet (SPE) enabling power delivery over data line (PoDL).
X EMC directives compliance: High slew rates and overshoots are often the
cause of noncompliance as they carry high harmonic content.

Figure 1. An example of analysis performed with LTspice.

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Solving Signal Integrity Problems Using LTspice Some nonconformities will show up in very specific situations such as:
This article will help you to answer key questions such as: X Long sequences of consecutive bits
X Is my system likely to have adequate signal integrity? X Nonzero balanced sequences
X Which signal aspect should I improve first? Should I improve the signal slew X Crosstalk from other nearby transmission channels
rate, rigging, jitter, or matching? This means, for example, that if the data is generated using a random function you
X My system is working, but will it work reliably over time, temperature, and might have to use thousands of symbols to make sure you encounter a specific
component tolerances? 11 consecutive high level.
After reading this article, you should be able to: The PWL data format that LTspice expects is shown in Figure 2.
X Implement signal integrity analysis within LTspice
X Generate, import, and use representative test vectors and produce similar
analysis and output as shown in Figure 1
X Perform a statistical validation of your system over several randomized
parameters

Performing an Eye Diagram Simulation

The eye diagram provides a convenient way to assess the conformity of a signal
on either the transmitter or receiver side. The eye diagram is a time-based rep-
resentation of the signal.
This representation uses persistence to analyze a large number of symbols and
make sure that signal levels, jitter, and rise time are appropriate.
Figure 2. The file format of a PWL test vector.
LTspice features some of the tools required for an eye diagram analysis, but to
perform a full featured analysis there are extra steps to implement. Where:
X The first value is time
Generating a PWL File with Your Test Vector
X The second value is output (voltage, current, temperature, etc.)
LTspice provides an efficient way to play a test vector in your simulation. Playing
a large amount of data is mandatory to provide good coverage of a situation that
X -> is the tabulation character (Ascii code #09)
can lead to nonconformities. X CR is the carriage return character (Ascii code #13)
X LF is the line feed character (Ascii code #10)
// initialize
fprintf (pFile,"%dn\t0\n",0,initialVoltage);
fprintf (pFile,"%dn\t0\n",DELAY,initialVoltage);

// loop for every sample

for (sample = 0 ; sample < NUMBER_OF_SAMPLES ; sample++)
{
// Compute a sample
logicLevel = rand() % 2;

// print sample
if (logicLevel == 0)
{
fprintf (pFile,"%fn\t%5.2f\n",(sample*symbolTime)+DELAY+transitionTime,voltageLow);
fprintf (pFile,"%fn\t%5.2f\n",((sample+1)*symbolTime)+DELAY-transitionTime,voltageLow);
printf ("%fn\t%5.2f\n",(sample*symbolTime)+DELAY,voltageLow);
}
else
{
fprintf (pFile,"%fn\t%5.2f\n",(sample*symbolTime)+DELAY+transitionTime,voltageHigh);
fprintf (pFile,"%fn\t%5.2f\n",((sample+1)*symbolTime)+DELAY-transitionTime,voltageHigh);
printf ("%fn\t%5.2f\n",(sample*symbolTime)+DELAY,voltageHigh);
}
}
Figure 3. An extract of the code used to generate a test vector.

2 How to Get the Best Results Using LTspice for EMC Simulation—Part 2: Improving Signal Integrity
There are many options to generate test vectors. For our simulations we picked
the C programming language.
With a few lines of code, you can easily generate large test vectors ready to inject
into your simulation. Figure 3 presents an extract of the code used to generate
the test vector and Figure 4 presents the waveform generated by the C program.

Figure 4. A generated test vector using C program. Figure 6. A USB signal captured using laboratory equipment.

Concepts used in wired communications, such as bit stuffing, can be imple- Figure 7 is a typical example of a dataset saved by an oscilloscope (the exact for-
mented with a few lines of code as illustrated in Figure 5. mat might differ but the given rules to import the data to LTspice will still apply).

// Max consecutive identical symbol (for droop)

#define MAX_CONSECUTIVE_0 7
#define MAX_CONSECUTIVE_1 10 1

[...]

if (consecutiveHigh > MAX_CONSECUTIVE_1)

3 2
{
printf("Hit Max 1 limit - Bit stuffing a Zero\n");
logicLevel = 0;
consecutiveHigh = 0;
}
if (consecutiveLow > MAX_CONSECUTIVE_0) Figure 7. Raw data of the captured USB signal.
{
printf("Hit Max 0 limit - Bit stuffing a One\n"); To use this data set in an LTspice simulation, a few modifications are needed:
logicLevel = 1;
consecutiveLow = 0; 1. The header line must be removed
}
2. Only one column of data must be present in the PWL file provided to LTspice
Figure 5. Code is provided in the links of this article.P1
3. Time values must be positive only
Generating a PWL file with a Captured Test Vector
Then your data is ready for use within LTspice.
Using real-world data and importing the data into LTspice is also possible. Once
the data is acquired with your regular laboratory equipment you can import it with
only a few steps.
For example, Figure 6 is a capture of a USB 1.0 communication performed with
an oscilloscope.

Figure 8. A USB signal imported in LTspice.

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Using a Test Vector PWL File Once the simulation is finished and your signals are displayed, right click on the
To use your generated PWL file you can add a voltage source and file path to your horizontal (time) axis.
design, as shown in Figure 9. A dialog will pop up, displaying an eye diagram button as shown in Figure 12.

Figure 12. The location of the eye diagram option.

This pop-up window allows you to enable and tune the eye diagram display, with
self-explanatory parameters.

Figure 9. A PWL option for the voltage source.

Both absolute and relative file paths will work, however, usage of relative paths
is advisable as this makes your simulation portable and ready to share with
your colleagues.

Figure 13. A setup of the eye diagram.

Upon validation your display will look like Figure 14.

Figure 10. An example of a relative path.

Enabling and Tuning of the Eye Diagram Feature

To benefit from the full potential of this well-hidden feature of LTspice, you’ll first
have to run your simulation.

Figure 14. An eye diagram display.

Computing and Displaying an Eye Diagram Mask

To simplify the assessment of signal integrity, the eye diagram can be associated
with an eye diagram mask. An eye diagram mask is not a standard LTspice func-
Figure 11. Right click in this area to enable eye horizontal axis properties. tion, however, it is still possible to implement it (like the EMC limit line in Article 1).
The specification of the eye diagram is a standard, so most of the mask can be
assessed from a reduced set of variables as described in Figure 15.

4 How to Get the Best Results Using LTspice for EMC Simulation—Part 2: Improving Signal Integrity
 Fine tuning or implementation of your eye definition is also possible using the
provided fields.
A

B C

Figure 15. An eye diagram and an eye diagram mask.

Figure 17. Eye mask input fields.
The following list defines the letters A to E in the eye diagram mask:
Corresponding plot setting commands are generated as you click on the update
X A: Eye flat width, this can be as low as zero in some mask definitions.
button. These lines are ready to be added to your plot settings file, following the
X B: Eye width, this is key for assessing several parameters such as maximum method described in Part 1 of this article series.
jitter, slew rate, and baud rate.
X C: Eye height, this might differ depending on if you are assessing this param-
eter at the near or the far end of your cable.
X D: Eye center, this defines the center voltage of the eye.
X E: Delay, this is used only in LTspice to move your signal within the plot window.

Generating an Eye Diagram Mask

In Part 1 of this article series, we described how to use drawing elements to dis-
play EMC limit lines over an FFT spectrum. In this article we show how to use the
same tools to draw an eye diagram mask. Figure 18. Plot settings generated by the webpage.
The generation of the eye diagram is more complex compared to generating and Adjustments to the number of eyes to draw and the LTspice delay setting might be
adding an EMC limit line. For eye diagrams, we use a webpage with JavaScriptP2 to necessary to get the best display, as shown in Figure 19.
generate the eye diagram definition, which can then be pasted into the plot set-
ting file (*.plt) of your LTspice signal display. This JavaScript program, as shown
in Figure 16 is available for the engineer to complete their design.
Eye diagram definitions for common wired interface standards are already
provided as presets. By clicking on each radio button, the fields are filled auto-
matically with typical values.

Figure 19. Plot settings generated by the webpage applied to waveforms.

Assessing Conformity over Tolerance Range

The components we use in our designs include wide tolerances, and by calcula-
tion, we can check whether or not these tolerances will be problematic. But when
designs include hundreds of components, pen and paper or spreadsheet manual
approaches are time consuming and may not capture important parameters.
Using a narrower tolerance is possible for some devices, but picking the whole bill
of materials in low tolerance components will cause price and availability issues,
and will not account for the effects of aging or temperature dependency.
Figure 16. Presets of the eye diagram generator.

VISIT ANALOG.COM 5
For the purpose of validating a design over its tolerances, spice and by extension Monte Carlo Simulation
LTspice feature several amazing tools. A Monte Carlo simulation takes a random value from the tolerance range of each
The following sections present techniques for tolerance analysis using Monte specified component in your simulation circuit. All values within the component
Carlo and Gaussian distributions as well as the worst-case analysis within LTspice. tolerance range have an equal probability for circuit simulation.
LTspice includes a convenient built-in Monte Carlo function with a simple syntax.
For example, to create a 100 Ω resistor with 10% tolerance, you need to use the
following syntax:
{mc(100R, ToIA)}
.param ToIA = 0.10

Table 1. Definition of Component Values and Tolerances

with Monte Carlo Method

Figure 20. Distribution of randomized values for the three main methods. Designator Range Syntax of Component Value (Monte Carlo)

R1 90 Ω to 110 Ω {mc(100, ToIA)}

Common Test Circuit for Gaussian, Worst-Case, and
Monte Carlo C2, C3 200 nF to 600 nF {mc(400 nF, ToIB)}
To compare the relevance and exhaustivity in a real use case we picked the L1 500 μH to 1500 µH {mc(1000 µH, ToIC)}
following example, based on the work of Graber4 this setup shows a simulation
L2, L3 0 nH to 500 nH {mc(250 nH, ToID)}
circuit for the SPE 10Base-T1L standard (10SPE) physical layer or MDI.
C6 0 pF to 200pF {mc(100 pF, ToIE)}
The simulation circuit shown in Figure 21 includes termination resistance of 100 Ω
±10% for Analog Devices’ ADIN1110 or ADIN1100 10BASE-T1L Ethernet PHY/MAC-PHY. The circuit described in Figure 214 can be used to simulate return loss, which is a
Signal coupling capacitance, power coupling inductors, common mode choke, and measure of all signal reflections likely to occur.
other EMC protection components are modeled. For some components, the rec- Return loss is caused by impedance mismatches at all locations along a cable link.
ommended component value and tolerance range are added. Return loss is expressed in decibels and is of particular concern for high data rate
Syntax for the return loss plot is: or long cable reach (1700 m) communications used in 10BASE-T1L.

(100+1/I(V1))/(100-1/I(V1))

PHY IC and Termination Inductive Power Clamping Common-Mode Choke Parasitic Capacitance of Signal Injection
Capacitive Signal Coupling Coupling Diodes Leakage Inductance EMC and Surge Protection Circuitry
C2 L2

V1
C1 R1 L1 C4 C5 C6
5 pF 25 pF 5 pF
AC 1 0

C3
L3

Figure 21. Common test circuit for Gaussian, worst case, and Monte Carlo–based on reference.4

6 How to Get the Best Results Using LTspice for EMC Simulation—Part 2: Improving Signal Integrity
To add the MDI return loss limit line to your plot (red line shown in Figure 23), from Where:
the Plot Settings Menu hit Save Plot Settings.
X 100R is the nominal value
Open the .PLT file using a standard text editor. Copy and paste the line definition X 0.1 is the tolerance (+ or – 10% here)
syntax as shown in the Excel file (Figure 22).
X 0 is the index of the parameter to vary, next component to vary will take index 1

Run the simulation circuit shown in Figure 21 with the expressions from the
following table instead of static component values:

Table 2. Definition of Component Values and Tolerances

Figure 22. Line definition for LTspice plot settings file. with Worst-Case Method
To obtain identical figures in your simulations please ensure that you right click Designator Range Syntax of Component Value (Worst Case)
the waveform, and then click the Don’t Plot Phase button.
R1 90 Ω to 110 Ω {wc(100, TolA, 0)}
Conclusion on the Monte Carlo Simulation C2 200 nF to 600 nF {wc(400 nF, TolB, 1)}
The Monte Carlo simulation is a relevant way to assess the compliance of an elec-
C3 200 nF to 600 nF {wc(400 nF, TolB, 2)}
tronic design over its tolerance range, it is very likely to suit the needs of most
designers while keeping the number of simulations runs reasonable. L1 500 μH to 1500 µH {wc(1000 µH , TolC, 3)}

L2 0 nH to 500 nH {wc(250 nH, TolD, 4)}

L2 0 nH to 500 nH {wc(250 nH, TolD, 5)}

C6 0 pF to 200 pF {wc(100 pF, TolE, 6)}

Results are displayed in the waveform plot Figure 24.

The MDI return loss mask limit line is added by editing the plot settings file as
described previously.

Conclusion on the Worst-Case Analysis

Steve Knudtsen provides a concise overview3 of the benefits and limitations of
Figure 23. Differential return losses of a SPE termination—128 runs of Monte Carlo dis-
using worst-case analysis for system design.
tributed parameters. The worst-case analysis is a common approach where component parameters
are adjusted to their maximum tolerance limit.
Worst-Case Simulation
The worst-case simulation function is not a built-in function of LTspice. However, Limitations of a worst-case approach include results that do not match commonly
you can implement functions to simulate worst case, as detailed in the work of observed results: to observe a system exhibiting worst-case performance would
Joseph Spencer and Gabino Alonso.2 require the assembly of a very large number of systems.

Both .func binary(run,index) and .func wc(nom,tol,index) functions are needed If systems are designed for worst-case conditions, then components selection
to perform simulations according to the worst-case scenario, you need to place can be expensive.
them on your LTspice schematic sheet as a SPICE directive. However, using both worst case in conjunction with Monte Carlo or Gaussian simu-
.func binary(run,index) floor(run/(2**index))-2*floor(run/(2**(index+1))) lation can yield valuable system insights.

.func wc(nom,tol,index) if(run==numruns,nom,if(binary(run,index),nom*(1+

tol),nom*(1-tol)))
In order to use these functions, you need to:
X Declare the number of simulation runs required to cover the maximum,
minimum, and nominal for each component subject to worst-case analysis
specified using numruns. The number of runs is determined by 2N +1, where N
equals the number of different indexes linked to component tolerances. For
Figure 21 this is 129 runs (taking run “0” into account), so the syntax is:

.param numruns = 129

X Instead of regular value of component you must declare the Figure 24. Differential return losses of a SPE termination: 128 runs of worst-case distrib-
following expression: uted parameters.

{wc(100R, 0.1, 0)} Worst-case analysis is best suited for a gross validation of behavior when simula-
tions are very long and when nominal behavior is already validated.

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Gaussian Simulation Conclusion on the Gaussian
LTspice includes a built-in Gaussian function, where the centered values have a The Gaussian distribution is very often the most relevant way to simulate the
higher probability of occurring, this Gaussian function has a simple syntax. variations of an electronic design.
{nominal_value*(1+gauss(tolerance/σ))} The Gaussian distribution of parameters around a nominal value remains the
most natural way to study the impact of tolerances.
Adjustments according to the standard deviation parameter σ of the Gaussian
distribution can be performed using the following expressions in Table 3. Unfortunately, this comes at a price. To be exhaustive, you will need a large num-
ber of simulation runs.
Table 3. Definition of Component Values and Tolerances
in with Gaussian Distribution Method This distribution will also pick values outside of the tolerance range, omitting the
sorting and binning operations performed by component manufacturers.
Expression Used Fraction of Samples within Tolerance

{nom*(1+gauss(tol/1))} 68.2% (1σ) Application to the Analysis of 10BASE-T1L link

Replacement of several field buses is possible using the 10BASE-T1L Ethernet
{nom*(1+gauss(tol/2))} 95.4% (2σ)
standard. The same cable can be used for both traditional fieldbus and 10BASE-
{nom*(1+gauss(tol/3))} 99.7% (3σ) T1L, which is a simple balanced copper pair used for full duplex communication
{nom*(1+gauss(tol/4))} 99.99% (4σ) and for powering the end-powered device (PD). While the same cable can be
reused, the physical layer communication transceiver (PHY) and passive compo-
Or using a more graphical representation: nents must change to meet the 10BASE-T1L standard.
Most validation of 10BASE-T1L signal integrity within LTspice can be performed
with a similarly shaped signal.

Table 4. Range of Single-Pair Ethernet Depending on

Transmit Signal Amplitude
Transmit Signal Amplitude5 Estimated Range

2.4 VPP 1000 m to 1700 m

1.0 VPP 200 m

Figure 25. Gaussian distribution of samples vs. σ. The encoding used is PAM36, for pulse amplitude modulation 3 levels. Depending
on the desired reach and capabilities of the endpoints, the transmit signal ampli-
For example, to create a 100 Ω resistor with 10% tolerance, and 4σ probability of
tude can be adjusted to either 1 V or 2.4 V.
value within tolerance you need to use the following syntax:
On the cable side, the signal rise is 53.33 ns for a –1 to +1 transition, and the fall
{100R*(1+gauss(ToIA/4))}
time is the same.
.param ToIA = 0.10
Slew rate is deemed constant so 0 to 1,1 to 0, –1 to 0 and 0 to –1 should have a
Figure 26 provides the result of 128 runs of the simulation provided in Figure 19, nominal transition time of 26.66 ns.
with Gaussian simulation provided in Figure 19, with Gaussian distributed param-
To generate such a test vector, we will use the code in Figure 27.P3
eters using 4σ.
That will output a test vector of 5000 PAM3 symbols in a PWL format.
By feeding this test vector to our schematic, we are able to validate the various
parameters such as minimal coupling, interwinding capacitance, and many more.
Figures 28, 29, and 30 show the transformer-based termination for a 10BASE-T1L
link, the output of a PWL source voltage file, and an eye diagram display of the
PWL voltage source and cable side differential voltage. This can be used for con-
formance testing to the 10BASE-T1L standard.

Figure 26. Differential return losses of a SPE termination: 128 runs of Gaussian distributed
parameters.

8 How to Get the Best Results Using LTspice for EMC Simulation—Part 2: Improving Signal Integrity
 // loop for every sample
for (sample = DELAY ; sample < (NUMBER_OF_SAMPLES+DELAY) ; sample++)
{
// Compute a sample
previousLogicLevel = logicLevel;
logicLevel = (rand() % 3) ;
transition = abs((previousLogicLevel - logicLevel));

switch (transition)
{
case 2 : // +1 to -1 transition or +1 to -1 transition
fprintf (pfile,"%E\t%5.2f\n",(sample*M_G_PERIOD),busvoltage[previousLogicLevel]);
fprintf (pfile,"%E\t%5.2f\n",(sample*M_G_PERIOD)+(M_G_RISE),busvoltage[logicLevel]);

break;

case 1 : // transition to nearby state ( -1 <-> 0 <-> 1 )

fprintf (pfile,"%E\t%5.2f\n",(sample*M_G_PERIOD)+((1.0*M_G_RISE)/4.0),
busvoltage[previousLogicLevel]);
fprintf (pfile,"%E\t%5.2f\n",(sample*M_G_PERIOD)+((3.0*M_G_RISE)/4.0),
busvoltage[logicLevel]);
break;

case 0 : // no change in value

fprintf (pfile,"%E\t%5.2f\n",(sample*M_G_PERIOD),busvoltage[logicLevel]);
break;

default :
break;
}
}
Figure 27. An extract of the code used to generate PAM3 test vector.

CWW1

VIN+ C4 VBUS+

470 nF
C2
150 pF L1 L2
C1 CWW2 C6 R1
V1 R2
100 R
100 nF 1000 pF 100 R
C3 L4 L3
150 pF
VIN– C5 VBUS–
CWW3
470 nF
PWL file = SPE-Testvector.txt .param CWW = 1 pF Lnom = 350 μH
.tran 0.2 ms k L1 L2 L3 L4 0.998

Figure 28. Transformer-based termination with PAM3 PWL test vector.

VISIT ANALOG.COM 9
 3
Steve Knudtsen. “How to Model Statistical Tolerance Analysis for Complex Circuits
Using LTspice.” Analog Devices, Inc., August 2021.
4
Steffen Graber. “10 Mb/s Single Twisted Pair Ethernet.” IEEE, May 2017.
5
IEEE802.3-2022 clause 146 + annex 146
6
IEEE802.3-2022 annex 146A

Programs:
P1
C program generating simple randomized bitstream with limited consecutive
0 and 1

Figure 29. An output of the PWL voltage source.

P2
HTML + Javascript generating eye diagram mask code for LTspice plot files
P3
C program generating randomized PAM3 bitstream

About the Authors

Richard Anslow is a senior manager, working in the field of software sys-
tems design engineering within the Industrial Automation Business Unit
at Analog Devices. His areas of expertise are condition-based monitor-
ing, motor control, and industrial communication design. He received
his B.Eng. and M.Eng. degrees from the University of Limerick, Limerick,
Ireland. Recently, he completed a postgraduate program in AI and ML with
PWL Voltage Source Purdue University.
Cable Side Differential Voltage

Figure 30. Eye diagram display of the PWL voltage source and cable side differential voltage. Sylvain Le Bras is a field applications engineer at Würth Elektronik special-
izing in power and electromagnetic compatibility. Prior to joining Würth
Conclusion Elektronik, Sylvain held various positions in research and development at
LTspice is a powerful and free simulation tool, which can be used in conjunction ABB and in Technology Transfer Laboratories. He received his M.Sc.Eng.
with waveform generators using standard C and JavaScript code. The end result degree from the Polytechnic School of the University of Nantes, France.
is a powerful wired communication signal integrity tool that can be used to save
time with lab experiments, guide end product design, and reduce time to market
for product developments. ADI and Würth Elektronik will provide this tool for engi-
Engage with the ADI technology experts in our online support community.
neers to design their wired links and help with understanding new standards such
Ask your tough design questions, browse FAQs, or join a conversation.
as 10BASE-T1L SPE.

References
1
“Signal Integrity Basics.” Signal Integrity White Paper. Anritsu, 2009.
Visit ez.analog.com
2
Joseph Spencer and Gabino Alonso. “LTspice: Worst-Case Circuit Analysis with
Minimal Simulations Runs.” Analog Devices, Inc.

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