Unit -6

TTL-74xx Series ICs:

Combinational and sequential
Contents:
1. Decoders (74LS138)
2. Priority Encoders(74XX148)
3. Multiplexers (74XX151)
4. Arithmetic Circuit IC –Parallel Binary Adder (74LS283)
5. Flip Flops- D Flip Flop (74XX74)
6. JK Flip Flop(74XX73/74XX109/74XX112)
7. T Flip Flop
8. Master Slave JK Flip Flop
9. Synchronous and asynchronous counters
10. Decade counters (74XX90)
11. Universal Shift Register (74LS194)
 1. Decoders

• A decoder is a multiple-input, multiple-output logic circuit

which converts coded inputs into coded outputs, where the
input and output codes are different.

• The input code generally has fewer bits than the output code,

• Each input code word produces a different output code word.

 General structure of a decoder

n : 2n
n data
Decoder
inputs
Possible 2n
outputs

Enable
inputs

Usually, a decoder is provided with enable inputs to activate

decoded output based on data inputs. When any one enable input
is unasserted, all outputs of decoder are disabled.
 Binary decoder

• A decoder which has an n-bit binary input code and a one

activated output out of 2 n output code is called binary
decoder.

• A binary decoder is used when it is necessary to

activate exactly one of 2n output based on an n-bit input
value.
Truth table for 2 to 4 decoder

En A B Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
2 to 4 Decoder
 Truth table for 3 to 8 decoder

EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Logic diagram for 3 to 8 decoder
IC 74X138 3 to 8 Decoder

Y0
15
1
A Y1 14
2
B
3
Y2 13
C
Y3
12
74X138 11
Y4
10
Y5
G1
9
6 Y6
5 G2A 7
4 G2B Y7
 IC 74X138 3 to 8 Decoder

• The 74X138 is a commercially available 3 to 8 decoder.

• It accepts three binary inputs (A,B,C) and when enabled,

provides eight active low outputs (Y0-Y7).

• The device has three enable inputs : two active low (G2A’,
G2B’) and one active high G1.
 Truth table for 74X138 IC

G2B G2A
G1 C B A Y7’ Y6’ Y5’ Y4’ Y3’ Y2’ Y1’ Y0’

1 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 0 X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1 1 0
0 0 1 0 0 1 1 1 1 1 1 1 0 1
0 0 1 0 1 0 1 1 1 1 1 0 1 1
0 0 1 0 1 1 1 1 1 1 0 1 1 1
0 0 1 1 0 0 1 1 1 0 1 1 1 1
0 0 1 1 0 1 1 1 0 1 1 1 1 1
0 0 1 1 1 0 1 0 1 1 1 1 1 1
0 0 1 1 1 1 0 1 1 1 1 1 1 1
74x139 Dual 2 to 4 decoder
4
1
1Y0 5
1G
2 1Y1 6
3
1A
1Y2 7
1B
1Y3
74X139
12
2Y0
11
6
2G 2Y1
5 10
2A 2Y2
4 9
2B 2Y3
 Realization of Multiple output function
using binary decoder

• The combination of decoder and external logic gates can be

used to implement single or multiple output functions.

• A decoder can have one of the two output states, either

active low or active high.
 For active high output

• SOP function implementation

• POS function implementation
 SOP function implementation

When decoder output is active high, it generates minterms (product

terms) for input variables I.e. it makes selected output logic 1. In
such a case to implement SOP function we have to take sum of
selected product terms generated by decoder. This can be
implemented by ORing the selected decoder outputs.
POS function implementation
 For active low output

• SOP function implementation

• POS function implementation
 POS function implementation

W h e n d e c o d e r o u t p u t i s a c t i v e l o w, t h e o u t p u t i s i n
complemented form, I.e., it generates maxterms for input
variables. It makes selected output logic 0. In such a case to
implement POS function we have to take product of selected sum
terms generated by decoder. This can be achieved by ANDing
the selected decoder outputs.
SOP function implementation
Cascading of Decoders
 2. Priority encoder

Encoder

2n inputs
n data
2n:n ouputs

Encoder
Enable
inputs

• A decoder’s output code normally has more bits than its input code. If the device’s
output code has fewer its than the input code, the device is called an encoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generate
binary code corresponding to the input value.
 Priority encoder

A Priority encoder is an encoder circuit that includes the priority

function. In priority encoder, if two or more inputs are equal to 1
at the same time, the input having the highest priority will take
precedence.
Truth table for priority encoder

Inputs Outputs
D0 D1 D2 D3 Y1 Y0 V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
Priority encoder IC 74xx148
Truth table for priority encoder 74xx148
Inputs Outputs
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO

1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X X X 0 0 0 0 0 1
 Priority Encoder

!The Group Select Output is asserted if when the device is

enabled and one or more of the request inputs are asserted.
!It is easy to remember Group Select as Got Something.
!The EO signal is the enable output designed to be connected to
the EI of another ‘148 that handles lower-priority requests.
!EO is asserted if EI is asserted but no request input is asserted;
thus a lower priority ‘148 may be enabled.
 3. Multiplexer

• Multiplexer is a digital switch. It allows digital information

from several sources to be routed onto a single output line.

• The selection of a particular input line is controlled by a set of

selection lines.

• Normally, there are 2n input lines and n selection lines whose

bit combinations determine which input is selected.
4 to 1 line multiplexer
74xx151 8 to 1 multiplexer
Truth table for 74xx151 8 to 1 multiplexer
74xx157 quad 2 input multiplexer
74xx153 dual 4 to 1 multiplexer
Expanding
multiplexers
 Implementation of combinational logic using Mux
• A multiplexer consists of a set of AND gates whose outputs are connected to
single OR gate. Because of this construction any boolean function in a SOP
form can be easily realized using multiplexer.

• Each AND gate in a multiplexer represents a min term.

• In 8 to 1 mux, there are 3 select inputs and 23 minterms.

• By connecting the function variables directly to the select inputs, a multiplexer

can be made to select the AND gate that corresponds to the minterm of the
function.

• If a minterm exists in a function, we have to connect the AND gate data input to
logic 1; otherwise we have to connect it to logic 0.
 4. Binary / Parallel Adder

Bn An B2 A2 B1 A1 B0 A0

Cout
Cout
FA FA FA FA
Cin

Cin
Sn S2 S1 S0
 Logic diagram for 4 bit parallel adder

B3 B2 B1 B0 A3 A2 A1 A0
Cout Cin
IC 74LS83 / 74LS283
S3 S2 S1 S0

The 74283 is a 4 bit binary adder that forms its sum and carry
outputs with just a few levels of logic, using the carry lookahead
technique.
Group-ripple carry adder
Sequential Circuits
The Sequential Circuit Model
Models for Sequential Circuits
" Block diagram representation

" State Tables and Diagrams: the functional relationship that

exists among the input, output, present state, and next state is
illustrated by either the state table or the state diagram.

" The state diagram is a graphical representation of a sequential

circuit in which the states are represented by circles and the
state transitions (the transfer from the present state y to the next
state Y) are shown by arrows.

" The state table lists the inputs across the top, the outputs along
the left side, with the entries in the table being the next state and

output for each input and present state.

Memory Devices

" Memory elements exist indefinitely in one of two possible states, 0 and 1.

" Binary data are stored in a memory element by placing the element into the 0
state to store a 0 and into the 1 state to store a 1.

" The output Q of the circuit indicates the present state of the memory.

" The two memory element types most commonly used in switching circuits are
latches and flip-flops.

" Latches are devices whose excitation inputs control the state of the device.

" A flip-flop differs from a latch in that it has a control switch called a clock. This
means a flip-flop waits for its clock signal before changing states. The final state
of a flip-flop is determined by its excitation values at the time the clock signal
occurs.
 TTL Memory Elements

Number of
Device Elements Element Description
74LS73A 2 Negative-edge triggered flip-flop with clear
7474 2 Positive-edge triggered D flip-flop with preset and clear
74LS75 4 D latch with enable
7476 2 Pulse-triggered JK flip-flop with preset and clear
74111 2 Master-slave JK flip-flop with preset, clear, data lockout
74116 2 4-Bit hazard-free D latch with clear and dual enable
74175 4 Positive-edge triggered D flip-flop with clear
74273 8 Positive-edge triggered D flip-flop with clear
74276 4 Negative-edge triggered JK flip-flop with preset, clear
74279 4 SR latch with active-low inputs
SR Latch

Traditional view of SR latch Logic symbol of SR latch

 Delay Latch

" When storing data, a memory element’s excitation input is

simply the data to be stored.

" A device (which is called a delay latch or D latch) is needed that

transfers a logic value on its excitation input D into the cross-
coupled storage cell of a latch.

" The logic symbol of the D latch is can be created from a gated
SR latch, by assigning S = D and R = D.
 Delay Latch (D latch)

Logic symbol
NAND implementation

NOR implementation
Flip-Flops

" The latch circuits presented thus far are not appropriate for use
in synchronous sequential logic circuits.

" The possibility of two cascaded combinational circuits feeding

each other, generating oscillations and unstable transient
behavior can be controlled by using a special timing control
signal called a clock.

" The clock can then be used to restrict the times at which the
states of the memory elements may change thus preventing the
unstable behavior just described.
 5. D - Flip Flop

The D flip-flop has the following state table

Note that changes on clock edge are always assumed

D Q(t+1) D 0 1
Q
0 0
0 0 1
1 1
1 0 1

Q(t+1) = D
characteristic equation
 5. D - Flip Flop

#A flip-flop stores one

bit of information.
#7474 is a positive edge
triggered D flip-flop
#A c t i v e l o w P r e s e t
(PRN) and Clear (CLRN)
Edge-triggered D Flip-Flops

" All the pulse-triggered flip-flops require both a rising and falling edge on
the clock for proper operation.

" Another approach is to design the flip-flop circuitry so that it is sensitive

to its excitation inputs only during rising or falling transitions of the
clock.

" A circuit with this design is called positive edge triggered if it responds
to a 0 to 1 clock transition, or negative edge triggered if it responds to a
1 to 0 clock transition.

" The edge-sensitive feature eliminates unstable transients by drastically

reducing the period during which the input excitation signals are applied
to the internal latches.
7474 Dual Positive-edge-triggered D Flip-Flop
Module

" Fig presents the logic symbol for the 7474. It is important to note
that the small triangle at the C1 input to the device is the
standard notation to indicate that it is positive edge triggered.

" Note that the asynchronous preset and clear signals override
the clocked operation of the circuit.

" When both CLR and PRE are inactive (high), the clock, CLK,
takes control of the device.

" While CLK is low, the flip-flop is in the hold mode. However, on
a 0 to 1 transition of the clock the data input D is transferred to
the flip-flop output Q.
 SN7474 dual positive-edge-triggered D Flip-Flop

Logic diagram IEEE standard logic symbol

7474 Excitation Table
 6. JK Flip Flop

J K Q(t+1)
JK 00 01 11 10
0 0 Q(t) Q
0 1 0 0 0 0 1 1

1 0 1 1 1 0 0 1
1 1 Q(t)'

Q(t+1) = J Q(t)' + K' Q(t), or

Q(t+1) = J Q(t)' + K' Q(t) + J K'

characteristic equation
Dual JK - FF
Pulse-Triggered JK Flip-Flop Realization

Logic symbol
Logic diagram
7476 Dual Pulse-triggered JK Flip-Flop Module

" shows the logic symbol of the 7476. This device packages two
flip-flops that operate in the manner displayed

" Included in the configuration are asynchronous set signals PRE

and reset signals CLR. The PRE and CLR signals override the
operation of the pulse-triggered inputs J, K and CLK.

" This means that if CLR = 0 then the state Q* goes to 0, or if

PRE = 0 the state Q* sets to 1, independent of the values of the
clock and the excitation inputs.
The SN7476 Dual Pulse-Triggered JK Flip-Flop
JK Flip Flop
 7. T Flip Flop

T 0 1
Q
T Q(t+1)
0 0 1
0 Q(t)
1 1 0
1 Q(t)'
Q(t+1) = TQ(t)' + T'Q(t) = T Q(t)

characteristic equation
Clocked T Flip-Flop

Functional equivalent
Logic symbol
 Excitation Table for Clocked T Flip-Flops

Q* = TQ + TQ

Figure 6.36
 8. Master Slave JK Flip Flop

! 7473a is a negative edge triggered JK flop-flop

! 7473 is the master-slave version
! positive edge triggered
Master-Slave JK Flip-Flops

" The JK operates as an SR flip-flop whose inputs are assigned J

= S and K = R.

" However, whereas the S = R = 1 combination is not allowed, the

JK uses this special case to incorporate a very useful mode of
operation.

" The additional feature of the JK device is that it state toggles,

that is changes from 0 to 1 or from 1 to 0 when J = K = 1.
Characteristic Equations

Flip-flop Characteristic Equation

D Q(t+1) = D

T Q(t+1) = T Q(t)

SR Q(t+1) = S + R' Q(t)

JK Q(t+1) = J Q(t)' + K' Q(t)

Excitation Tables

Q(t) Q(t+1) D T SR JK

0 0 0 0 0x 0x

0 1 1 1 10 1x

1 0 0 1 01 x1

1 1 1 0 x0 x0
9. Synchronous and Asynchronous Counters

A synchronous counter connects all of its flip-flop clock inputs

to the same common CLK signal, so that all of the flip-flop
outputs change at the same time after only tTQ ns of delay.
" Asynchronous Counters

" Up counter using T flip-flops

" Count clock pulses

1 T Q T Q T Q
Clock MSB of count
Q Q Q

Q0 Q1 Q2
" Q0 toggles on every 0 $ 1 clock edge
" Q1 toggles on every 1 $ 0 transition of Q0
" Q2 toggles on every 1 $ 0 transition of Q1
" Synchronous Counters

" Asynchronous counters are slow due to propagation

delays
" Synchronous counters share the clock among all flip-flops

clock cycle Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0 T0 = 1 always toggle
3 0 1 1 T1 = Q0 toggle when Q0 = 1
T2 = Q1Q0 toggle when Q1Q0 = 1
4 1 0 0
T3 = Q2Q1Q0 toggle when Q2Q1Q0 = 1
5 1 0 1 …
6 1 1 0
7 1 1 1
8 0 0 0
Binary Synchronous Counter
Mod-11 Counter using 74x163
Decade Counter

" IC 74LS90 monolithic counters contains four master slave flip-flops

and additional gating to provide a divide-by two counter and a three-
stage binary counter for which the count cycle length is divide-by-five.
All of these counters have a gated zero reset and also has gated set-
to-nine inputs for use in BCD nine’s complement applications. To use
their maximum count length (decade or four bit binary), the B input is
connected to the QA output. The input count pulses are applied to
input A and the outputs are as described in the appropriate truth table.
A symmetrical divide-by-ten count can be obtained from the 74LS90
counters by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square wave at
output QA.
10. Decade Counter
Decade Counter
Decade Counter
 11. Universal Shift Register

" Simple 4 Bit Register

" A standard 4 bit register using D flip flops

Parallel output
Q3 Q2 Q1 Q0

D Q D Q D Q D Q
Q Q Q Q

Parallel input
Clock
serial in/out access
Shift Registers-Types
Shift Registers-Types
Shift Registers-MSI circuits
" 74194 Bi-Directional Shifter

" 4 bit bi-directional shifter with parallel load

" Active low asynchronous clear
" Shift Left Serial In (SLSI)
" Shift Right Serial In (SRSI)
" Positive edge-triggered
Universal shift Register-Functional Table