2013 International Conference on Machine Intelligence and

Research
Research
and Advancement

Design of Low power and high speed 4-bit Comparator using

Transmission Gate
Govind Prajapat Akhilesh Joshi Aman Jain Kumkum Verma Sanjay Kr. Jaiswal
B.Tech EC B.Tech EC B.Tech EC ECE Deptt. ECE Deptt.
ITM College ITM College ITM College ITM College ITM College
Bhilwara (Raj.) India Bhilwara (Raj.) India Bhilwara (Raj.) India Bhilwara (Raj.) India Bhilwara (Raj.)India
[email protected] [email protected] [email protected] [email protected] [email protected]

Abstract— This paper present two different designs for 4-bit A is less than the second number B and output Z becomes to 1
comparator, one is using CMOS technology and another is when the first number A becomes larger than the second
designed using Transmission Gate. Firstly we have designed number B. Our method is to design various logic gate using
various CMOS devices and generate its symbol and using this 4 CMOS technology and transmission gate. After that, design
bit CMOS comparator is implemented. The comparator circuit CMOS and transmission gate comparator by connecting
produce 3 outputs X, Y and Z. X is active when A=B, Y is active various logic gates. Then we extract the T- spice file in tanner
when A<B and Z is active when A>B. Our approach to design EDA and run under W-edit to get the simulation.
comparator is by connecting desired symbol and design for 4-bit
comparator. After that all the logic gates are designed by
transmission gate and connect it to design Comparator. From the II. IMPLEMENTATION OF COMPARATOR
given comparison table we see that power dissipation and delay TRANSMISSION GATE DESIGN
is reduced up to 65% and 50% respectively in Transmission gate
comparator in Comparison with CMOS comparator. All the First of all we need to design the basic logic gate. All logic
simulations are performed using tanner EDA software at TSMC gates are designed by transmission gate. To implement the 4-
180 nm technology. bit comparator required logic gates are connected in the 4 – bit
comparator circuit.
Keywords: Transmission gate, low power, high speed, VLSI, A/D
converters, 180 nm CMOS technology
A. TRANSMISSION GATE DESIGN
Firstly we need to design a transmission gate by the
I. INTRODUCTION parallel connection of NMOS and PMOS transistor. Basically
the transmission gate works as AND gate. The output of
Comparison between two binary numbers is widely used Transmission gate is not stable so a resistor is connected at
in computer systems and device interfaces for equality. A output terminal. Control signal A is apply at the gate terminal
circuit that compares two binary numbers and decides whether of NMOS and PMOS which is complement of each other. If
they are equal or not is called comparator [2]. control signal is logic ‘1’ and the input is logic
The CMOS technology produce degraded output in the
circuit. As NMOS transistor pass strong logic 0 and weak 1
pass but PMOS transistor is strong 1 pass and weak 1 pass. It
is possible to combine NMOS and a PMOS transistor into a
single switch that is capable of driving its output terminal
either to a low or high voltage equally well.[8] With
increasing demand of high speed and low power application
the transmission gate can preferred over the CMOS transistor.
Transmission gate comparator design has required less
number of MOSFETS comparison then CMOS. So the feature
size and cost of device can be reduced. It is used in analog to
digital converters, oscillators, current to frequency converters,
VLSI neural network, sensor circuit and portable wireless
communication etc. H. Traff [1] proposed the first high speed,
low input impedance current comparator using a simple
inverter. Tarff’s approach has been modified by a number of
designs, A. T. K. Tang et al. [2] and L. Ravezzi et al. [3],
where speed increases have been attained at the cost of
increasing power consumption.
It is desirable that comparators must provide high speed
and low power consumption. Here we need to design such
kind of a comparator which compares the value of two 4-bit
numbers and output X becomes to 1 when the two numbers A
and B are equal, output Y becomes to 1 when the first number Fig. 2.1. Schematic of transmission gate (proposed)

978-0-7695-5013-8/13 $31.00 © 2013 IEEE 379

DOI 10.1109/ICMIRA.2013.80
‘1’ then PMOS is ON and NMOS is OFF but when input is
logic ‘0’ then PMOS is OFF and CMOS is ON. If control
signal is logic ‘0’ then Output equal will be to a control signal
or vice versa.
In above circuit diagram when the control signal is logic
‘1’ then the NMOS is ON and the PMOS is OFF so the output
current flow through the NMOS transistor. When the control
signal is logic ‘0’ then the NMOS is OFF and the PMOS is
ON so the output current flow through these PMOS transistor.
But also when input is logic ‘0’ then PMOS is OFF and
CMOS is ON. If control signal is logic ‘0’ then Output equal
to a control or vice versa.

B. AND GATE DESIGN

The circuit diagram of transmission gate is shown in
fig.2.1, which consists of one PMOS, one NMOS, one
resistor, one inverter and one control input. It works as AND
gate required less number of component compared to CMOS
and gate. 3 input AND gate is designed by 2 input AND gate. .
In the in the same way 4 input and 5 input AND gate can be Fig. 2.3. Circuit diagram of XOR gate
designed
III.4-BIT-COMPARATOR
C. OR GATE DESIGN The comparator circuit requires 4 x-nor gate, 5 and gate, 3
Low power dissipation OR gate is designed by using or gate and 5 inverters. In the beginning all the logic gates are
transmission gate. In this design the numbers of MOSFETs implemented by transmission gate and generates block
are reduced. So it has better results than CMOS OR gate. Four diagram. The 4-bit comparator is implemented by serial
input OR gate is designed by serial connection of 2 input OR connection of these blocks. It has three outputs X, Y and Z.
gate. Output X becomes high when both inputs are equal, output Y
becomes high when input A is less than B (Where A and B is
the input), output Z becomes high when A>B.

Fig. 2.2. Circuit Diagram of OR gate

D. XOR GATE DESIGN

The extended design of XOR gate using the
Fig. 3.1. Schematic of 4-Bit Transmission gate
transmission gate is show in fig. 2.3. It consists of two Comparator (proposed)
inverters, two PMOS transistors and two NMOS transistors.

380
 The Schematic diagram of CMOS transmission gate is circuit. Waveform of power dissipation in CMOS comparator
similar to the Transmission gate comparator. The measure is shown in fig. 4.1. This waveform show the power dissipated
differences between them are the technology used to design by the comparator circuit. The power source in the circuit is
logic gate. In CMOS comparator, the logic gates are designed vdd and the waveform taken out at vdd equal to 5 volt.
by CMOS technology and in transmission gate comparator,
logic gates are designed by transmission gate. The power dissipated by transmission gate comparator
waveform is shown in fig. 4.2
IV. ANALYSIS
When simulate T-spice file then it gives output waveform. B. PROPAGATION DELAY.
This paper described two types of parameter. Propagation delay insures the speed of the device. Delay
of Transmission gate comparator becomes less than CMOS
A. POWER DISSIPATION. comparator so the transmission gate comparator faster in
Transmission gate comparator required 134 MOSFETs response. The simulated transient time waveform of 4-bit
and CMOS comparator required 164 MOSFETs. comparator is shown in fig. 4.3.
Transmission gate comparator required less number of co mp

MOSFETS than CMOS comparator. So power dissipation in 5 .0

4 .5
v( a1)

Voltage ( V)
4 .0
3 .5

CMOS circuit is greater than transmission gate 3 .0

2 .5

2 .0

CMOS
1 .5
1 .0
0 .5

0 .0
0 10 20 30 40 50 60 70 80 90

Ti me ( ns )

p(vdd) co mp

100
5 .0 v( a0)

4 .5

Voltage ( V)
4 .0

90 3 .5
3 .0
2 .5
2 .0
1 .5

80 1 .0

0 .5
0 .0
0 10 20 30 40 50 60 70 80 90

70 Ti me ( ns )
Power (mW)

co mp

60 v(X)

3 .5

Voltage ( V)
3 .0

50 2 .5

2 .0

1 .5

1 .0

40 0 .5

0 .0
0 10 20 30 40 50 60 70 80 90

30 Ti me ( ns )

co mp

20 5 .0
4 .5
v(Y)
Voltage ( V)

4 .0
3 .5

10 3 .0
2 .5
2 .0

1 .5
1 .0

0 0 .5

0 .0
0 10 20 30 40 50 60 70 80 90

0 10 20 30 40 50 60 70 80 90 Ti me ( ns )

Time (ns) co mp

5 .0 v(Z)

Fig . 4.1. Waveform of power dissipation in

4 .5
Voltage ( V)

4 .0
3 .5

CMOS comparator
3 .0
2 .5
2 .0
1 .5
1 .0
0 .5

0 .0
0 10 20 30 40 50 60 70 80 90

Ti me (ns )

Fig . 4.3. Output Waveform of 4 – Bit comparator

Tx gate
80 p(vdd) V. RESULTS
70
The Propagation Delay and Power dissipated by
transmission gate comparator circuit shown in table 5.1
60
Table. 5.1 Simulation Result for Comparator designed by
50 transmission gate
Power (mW)

40
Parameters
30 S.No. Voltage Power Power delay
Delay
20 (Vdd) dissipation Product

10 1. 4.4v 430ps 52.00mw 22.36pws

2. 5.0v 460ps 65.85mw 30.29pws
0
3. 5.6v 540ps 78.88mw 42.60pws
0 10 20 30 40 50 60 70 80 90 4. 6.0v 550ps 94.85mw 52.17pws
Time (ns)
Fig . 4.2. Waveform of power dissipation in transmission
Gate comparator
The Propagation Delay and Power dissipated by CMOS
comparator circuit shown in table 5.2

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 VI. CONCLUSION
Table. 5.2 Simulation Result for Comparator using
CMOS technology
Parameters This paper has described two different designs for binary
S.No. Voltage Power Power delay comparator; one is low power efficient, and other is more power.
Delay CMOS and transmission gate circuits are used to construct the
(Vdd) dissipation Product
1. 4.4v 545ps 84.45mw 46.02pws
comparator by using the logic relation between different input and
output. A Karnaugh map is used to minimize the representation of
2. 5.0v 700ps 108.96mw 76.27pws function. From the comparison table we see that power and area is
3. 5.6v 760ps 147.28mw 111.93pws reduced upto 65% and 50% in transmission gate comparator in
comparison with CMOS comparator.
4. 6.0v 850ps 163.69mw 139.14pws
ACKNOWLEDGEMENT
Authors would like to thank to Miss Kumkum Verma and all
This proved that the comparator designed by transmission ITM Bhilwara staff for their support during the course of this work.
gate gives batter results (faster in response and power
consumption) then CMOS technology.
REFERENCES
[1] H. Traff, “Noval approach to high speed CMOS current comparator”,
Electron. Letter, vol. 28, no. 3, pp. 310- 312, Jan.1992.
[2] A.T K. Tang and C. Toumazou, “High performance CMOS current
comparator”, Electron. Letter, vol. 30, pp. 5-6, 1994.
[3] L. Ravezzi, D. Stoppa and G. F. Dalla Betta, “Simple High speed
CMOS current comparator”, Electron. Letter, vol.33, pp.1829- 1830,
1997.
[4] Lu Chen, Bingxue Shi and Chun Lu, “A Robust High-Speed and Low-
power CMOS Current Comparator Circuit,” IEEE Asia- Pacific Conf.
On Circuits and Systems, pp. 174-177, 2000.
[5] R.Choudhary, M. Bharadwaj, B.P. Singh and K.Gupta, “Design of
Low Power Low Input Impedance CMOS Current Comparator” ,
Second International Conference on Advanced Computing &
Communication Technologies 2012, (ACCT), pp378 – 382, Print
ISBN:978-1-4673-0471-9.
Fig . 5.1. Comparison of Power Dissipation between Transmission [6] Sanjay Kumar Jaiswal and Kumkum Verma” Design of CMOS 8-BIT
Gate technology and CMOS technology Comparator for Low Power Application” IEEE ,Fourth International
Conference on Computational Intelligence and Communication
Networks (CICN 2012),pp 480-482, ISBN:978-1-4673-2981-1.
Delay is related to the speed of the circuit. Minimum delay
means high speed. It depends upon the transition region of the [7] S. Rahul, F. L. Richard and M. Carver, “A Low Power Wide Dynamic-
Range Analog VLSI Cochlea,” Analog Integral Circuits Signal Process,
input and output waveforms. It also depends upon power vol. 16, pp. 245– 274, 1998.
supply voltage i.e.; vdd. Graph of delay between CMOS [8] P. F. Ruedi, P. Heim, F. Kaese, E. Grenet, F. Heitger, P. Y. Burgi,
comparator and Transmission gate comparator is shown below S.Gyger and P. Nussbaum, “A 128X128 pixel 120 dB dynamic range
in fig.5.2 vision-sensor chip for image contrast and orientation extraction, ” IEEE
Journal Solid-State Circuits, vol. 38,pp. 2325- 2333, 2003.
[9] Niels van Bakel, Jo van den Brand, “Design of a comparat 
CMOS technology”
[10] VLSI design by K. Lal Kishore, V. S. V. Prabhakar I. K. International
Pvt Ltd, 01-Jan-2009.
[11] Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits
Analysis and Design”, Tata McGraw-Hill third edition.
[12] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital
Integrated Circuit”, Pearson Education Electronics and VLSI series,
second edition.

Fig . 5.2. Delay between CMOS and

transmission gate comparator

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