Chapter-5-

Sequential Digital
Circuits
◼ Sequential circuits are digital circuits in
which the outputs depend not only on the
current inputs, but also on the previous
state of the output.
▪ There are two types of sequential circuits:
❖synchronous: outputs change only at
specific time
❖asynchronous: outputs change at any
time
▪ Multivibrator: a class of sequential circuits.
They can be:
❖bistable (2 stable states)
❖monostable or one-shot (1 stable state)
❖astable (no stable state)
▪ Bistable logic devices: latches and flip-flops.
▪ Latches and flip-flops differ in the method
used for changing their state.
 S-R Latch
◼ The block diagram for the S-R Latch
is shown below:

SET S Q Q output
INPUT

RESET Q output
R Q
INPUT
▪ The truth table for the S-R Latch is
listed below:

inputs output
S R Q
0 0 Q No change
0 1 0 Latch RESET
1 0 1 Latch SET
1 1 ? Invalid Condition
▪ An active-HIGH input S-R latch is formed
with two cross-coupled NOR gates.

S
Q

Q
R
◼ The block diagram for the S-R Latch
is shown below:
SET Q Q output
S
INPUT

RESET
R Q Q output
INPUT
▪ The truth table for the S-R Latch is
listed below:
inputs output

S R Q
1 1 Q No change
1 0 0 Latch RESET
0 1 1 Latch SET
0 0 ? Invalid Condition
▪ An active-LOW input S-R latch is formed with
two cross-coupled NAND gates.

S
Q

Q
R
S-R Latch with Enable (EN) Input
To be able to control when the S and R
inputs of the SR latch can be applied to
the latch and thus change the outputs, an
extra input is used. This input is called
the Enable. If the Enable is 0 then the S
and R inputs have no effect on the
outputs of the SR latch. If the Enable is 1
then the Gated SR latch behaves as a
normal SR latch.
◼ The block diagram for the S-R Latch
with Enable (EN) Input is shown
below:
S Q
EN

R Q
 inputs output
EN S R Q
0 0 0 Q
0 0 1 Q
No Change
0 1 0 Q
0 1 1 Q
1 0 0 Q
1 0 1 0 Like a Truth
1 1 0 1 Table
1 1 1 ?
A gated S-R Latch with Enable (EN) Input

S S
Q

EN

R Q
R
The Data (D) Latch
A problem with the SR latch is that the S
and R inputs can not be at logic 1 at the
same time. To ensure that this can not
happen, the S and R inputs can by
connected through an inverter. In this
case the Q output is always the same as
the input, and the latch is called the Data
or D latch. The D latch is used in
Registers and memory devices.
◼ The block diagram for the D Latch is
shown below:

D S Q Q D Q Q
EN EN

R Q Q Q Q
▪ The truth table for the D Latch is listed
below:
inputs output
D EN Q
1 1 1 SET
0 1 0 RESET
X 0 Q No change
A gated D Latch

D S
Q

EN

Q
R
 ◼ Latch Circuits: Not Suitable
▪ Latch circuits are not suitable in synchronous
logic circuits.
▪ When the enable signal is active, the excitation
inputs are gated directly to the output Q. Thus,
any change in the excitation input immediately
causes a change in the latch output.
▪ The problem is solved by using a special timing
control signal called a clock to restrict the times at
which the states of the memory elements may
change.
▪ This leads us to the edge-triggered memory
elements called flip-flops.
Clocked S-R Flip-Flop

S Q Q S Q Q
CK CK

R Q Q R Q Q

Positive Edge Trigger Negative Edge Trigger

S S
Q

CK

R Q
R
▪ A truth table for a positive edge-triggered
S-R flip-flop
inputs Output
S R CK Q
0 0 X Q
0 1 0
1 0 1
1 1 ?
D-Type Flip-Flop
◼ The block diagram for the D-Type
Flip-Flop is shown below:

D S Q Q D Q Q
CK CK

R Q Q Q Q
A logic diagram for a positive edge-
triggered D flip-flop
D S
Q

CK

Q
R
▪ A truth table for a D-Type flip-flop

inputs output
D CK Q
1 1
0 0
The JK Edge Triggered Flip Flop
The functioning of the J-K flip-flop is
identical to that of the S-R flip-flop in
the set, RESET, and no-change
conditions of operation. The
difference is that the J-K flip-flop has
no invalid state as does the S-R flip-
flop.
J-K Flip-Flop
◼ The block diagram for the J-K
Flip-Flop is shown below:
J Q Q

CK

K Q Q
A logic diagram for a J-K flip-flop

J
Q

CK

Q
K
▪ A truth table for a J-K flip-flop

inputs output
J K CK Q
0 0 Q
0 1 0
1 0 1
1 1 Q
EXAMPLE
Determine the Q output waveforms
of the clocked J-K flip-flop for the J,
K, and CLK inputs in the following
figure. Assume that the positive
edge-triggered flip-flop is initially
RESET.
Solution:

CK

× × ×
J × × ×
× ×
K × × × ×

0
Q
T Flip-flop
▪T flip-flop: single-input version of the J-K flip
flop, formed by tying both inputs together.
The block diagram for the J-K Flip-Flop is
shown below:

T J Q Q

CK

K Q Q
▪ A truth table for a T-Type flip-flop

inputs output
T CK Q(t+1)
0 Q(t) No change
1 Q(t) Toggel
A logic diagram for a positive edge-
triggered T flip-flop

T
Q

CK