Chapter-7-

Binary Counters
 •Counters
◼ Counters are sequential circuits which "count" through a
specific state sequence. They can count up, count down, or
count through other fixed sequences. Two distinct types are
in common usage:
◼ Asynchronous (Ripple) Counters
• Clock connected to the flip-flop clock input on the LSB
bit flip-flop
• For all other bits, a flip-flop output is connected to the
clock input, thus circuit is not truly synchronous!

▪Synchronous Counters
• Clock is directly connected to the flip-flop clock inputs
• Logic is used to implement the desired state sequencing
 Asynchronous Counters
Asynchronous Up-Counter
High (1)
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CK (
CK CK CK CK

K0 K1 K2 K3

Clock
Input
Q0 Q1 Q2 Q3

outputs
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CK

Q0 0

Q1 0

Q2 0

Q3 0

Timing diagram for a 4-bit Asynchronous Up-Counter

 Output of counter Decimal
Q3 Q2 Q1 Q0 number

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3

Repetition cycle
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Maximum Count (N) of a Counter
N = 2 −1
n

where
N Maximum Count of a Counter

n Number of flip-flops of a counter

Modulus (MOD) of a Counter

MOD = 2n
Number of binary combinations of a counter output
Asynchronous Down-Counter
outputs

Q0 Q1 Q2 Q3

High (1)
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CK (
CK CK CK CK

K0 Q0 K1 Q1 K2 Q2 K3 Q3

Clock Input
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CK

Q0 0

Q1 0

Q2 0

Q3 0

Timing diagram for a 4-bit Asynchronous Down-Counter

 Output of counter Decimal
Q3 Q2 Q1 Q0 number

1 1 1 1 15
1 1 1 0 14
1 1 0 1 13

Repetition cycle
1 1 0 0 12
1 0 1 1 11
1 0 1 0 10
1 0 0 1 9
1 0 0 0 8
0 1 1 1 7
0 1 1 0 6
0 1 0 1 5
0 1 0 0 4
0 0 1 1 3
0 0 1 0 2
0 0 0 1 1
0 0 0 0 0
Asynchronous Up-Down Counter
Output of counter

High (1) Q0 Q1

FF0 FF1
J0 Q0 J1 Q1

CK CK

K0 Q0 K1 Q1
UP/ DOWN
Asynchronous Decade (MOD-10) Counter
High (1)
FF0 FF1 FF2 FF3
J0 Q0 J1 Q1 J2 Q2 J3 Q3
CK (
CK CK CK CK
K0 Q0 K1 Q1 K2 Q2 K3 Q3
C LR C LR C LR C LR

Q0 Q1 Q2 Q3

Output of counter
 1 2 3 4 5 6 7 8 9 10
Ck
0
Q0
Glitch
0
Q1
0
Q2
0
Q3
C LR

Timing diagram for a 4-bit Asynchronous Decade Counter

 Output of counter Decimal
number
Q3 Q2 Q1 Q0
0 0 0 0 0
0 0 0 1 1

Repetition cycle
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
b) Design asynchronous counter circuit to achieve the following counts by T-type flip-flops:
(3 to 12)10

Preset Preset CLR CLR