Scribd
Upload
16 views3 pages

Question HDL

HDL questions

Uploaded by

ramthaku18
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
16 views3 pages

Question HDL

HDL questions

Uploaded by

ramthaku18
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 3

Verilog:

1. What will be the equivalent code of the following Verilog code using blocking statements? No
temporary variable.
Initial
Begin
A = 10;
A <= 25;
B <= A;
End
2. Difference between a task and a function.
3. Write a Verilog code for a simple one hot state machine?
4. What will be the logic implementation using a case statement and an if-else statement?
5. How to model inertial and transport delay using Verilog?
6. always clock = #2.5 clock; delayed_clock = #7 clock. What will be the simulation result?
7. Write a Verilog code for a single clock FIFO.
8. Difference between $display and $monitor
9. Difference between compiled code and normal simulator. A compiled code simulator compiles all
the files(design and verification) and writes out an executable(similar to a.out, for people familiar
with C language). The engineer then needs to run this executable in order to perform the
simulation. This simulator will speed up the simulation since it need not compile each and every
file for every simulation run. It will detect the files that are modified and compile those files and
files that depend on those modified files. A normal simulator performs compilation and execution
in the same step. So it has to compile each and every file whenever a simulation is performed.
10. Blocking and Non-blocking assignments*
Case I: Blocking Procedural Assignments
Initial begin
#1 a=b;
#1 c=d;
#1 e=f;
end
In this case, as soon as the initial block is entered, we wait for 1time unit and then sample the
value of b and assign that value of b to a. Then wait for 1 more time unit, sample the value of d
and assign that value of d to c and so on.
Case II: Blocking Intra-procedural assignment
Initial begin
a= #1 b;
c= #1 d;
e= #1 f;
end
In this case, as soon as the initial block is entered, we sample the value of b, then wait for 1 time
unit and assign that value of b to a. Then sample the value of d, wait for 1 more time unit, and
assign that value of d to c and so on.
Case III: Non-Blocking procedural assignment
Initial begin
#1 a <= b;
#1 c <= d;
#1 e <= f;
end
In this case, as soon as the initial block is entered, we wait for 1time unit and then sample the
value of b and assign that value of b to a. Then wait for 1 more time unit, sample the value of d
and assign that value of d to c and so on. Because its non-blocking assignment, the assignment
is made at the END of the timestep.
Case IV: Non-Blocking Intra-procedural assignment
Initial begin
a<= #1 b;
c<= #1 d;
e<= #1 f;
end
In this case, as soon as the initial block is entered, we sample the value of b,d and f, then wait for
1 time unit and assign that value of b to a, value of d to c and the value of f to e.
11. Difference between casex and case statements
12. What is defparam used for? Defparam is used to override the parameter declarations during run-
time
13. What's the difference between a latch and a flip-flop? Write Verilog RTL code for each.
14. assign #4 out = in; in the above statement if the signal in changes with in 4 units of time what will
be the value of out after 4 units?
15. Task Vs Functions.
16. Whatever a function does, a task can also do! Why do we still use functions!!
17. How to override parameters? Defparam
18. $display Vs $monitor
19. 2:1 MUX Code:
--- Tertiary Operator X = S?b:a
--- Using Case (in always block)
20. Four-Types of coding:
a) behavioral (comes in always/initial blocks)
b) structural (netlist)
c) dataflow (in terms of expression)
d) switch level (FET/BJT Level, similar to spice netlists)
21. Various verilog data types!!
22. Non/Synthesizable constructs
23. Inertial/Transport delays - Write codes.
24. What are the various timing violations:
setup, hold, width, recovery, removal!!!
25. Describe non/blocking assignments.
26. Race condition in the given code! Give Example.
27. Multiple drivers. Give Example Code
28. Learn writing codes for State Machines (FSM).
29. Draw Timing Diagrams for given code/ckt.
30. Inferrence of design blocks (latches, ff etc)
31. timescale.
32. Automatic task/functions -- What are?
task m;
--
--
endtask;

module mdl;
--
--
fork
m;
m;
m;
join

1 module re_entrant_task();
2
3 task automatic print_value;
4 input [7:0] value;
5 input [7:0] delay;
6 begin
7 #(delay) $display("%g Passed Value %d Delay %d", $time, value,
delay);
8 end
9 endtask
10
11 initial begin
12 fork
13 #1 print_value (10,7);
14 #1 print_value (8,5);
15 #1 print_value (4,2);
16 join
17 #1 $finish;
18 end
19
20 endmodule

33. Tertiary operator, how will it look after synthesis(2x1 Mux).


34. Verilog code for clock generation(wrote).
35. What is initial block, Whether it can be kept in designs(No, cauz can not be synthesized).
36. assign out = sel?in1:in2; // How out will respond to sel = X? // I think out should go X
37. always@(sel or in1 or in2)
38. if(sel)
out = in1;
else
out = in2;
//How out will respond to sel = X? Should go to else block!!!

You might also like