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Module 5 Pentium Processor

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Shreeyash Jadhav
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19 views14 pages

Module 5 Pentium Processor

Uploaded by

Shreeyash Jadhav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 5

Pentium Processor
➢Wider Data Bus
➢Dedicated Instruction Cache
➢Dedicated Data Cache
➢Parallel Integer Execution
➢Floating Point Unit
➢Branch Prediction
➢New Instructions
➢Speed
Pentium performs integer instructions in a five-stage pipeline.
➢PF - Prefetching
➢D1 – Instruction Decoding
➢D2 – Address Generation
➢EX – Execution
➢WB – Write Back
➢Prefetch
➢Instruction Decode 1
➢Instruction Decode 2
➢Execution
➢FP Execution 1
➢FP Execution 2
➢Write FP Result
➢Error Reporting
Two basics cache architectures are –
1. Look-through cache design
2. Look-aside cache design
1. Reduces the system and memory bus utilization.
2. Allows bus concurrency.
3. Complete write operations in zero wait states using posted writes.
1. Cache miss cycles complete faster
2. Simplicity of designs
3. Implementation cost is lower
➢Write-through Cache Designs
➢Buffered or Posted Write-through Designs
➢Write-back Cache Designs

➢Separated code and data cache each of 8 Kbytes


➢Line size is 32-bytes.
➢Write-back Cache Designs
➢Each cache is organized as 2-way set-associative.
➢The data cache follows the MESI protocol
➢The cache can be enabled or disabled by software or hardware.
➢The MESI protocol provides a method to maintain cache coherency.
➢The MESI protocol is only for the data cache and the SI protocol for
the code cache.
➢Each line in data cache can be in one of the four MESI states and is
indicated by two bits stored along with the tag address.
• Modified
• Exclusive
• Shared
• Invalid
Total size of cache = 8 KB
Size of each way = 4 KB
Cache Line size = 32 bytes
Number of Lines in one way = 128
Attribute 8085 8086 80286 80386 80486 Pentium
Processor Size 8-bit 16-bit 16-bit 32-bit 32-bit 32-bit

Data Bus 8-bit 16-bit 16-bit 32-bit 32-bit 64-bit

Memory Banks NA 2 banks 2 banks 4 banks 4 banks 8 banks

Address Bus 16-bit 20-bit 24-bit 32-bit 32-bit 32-bit

Memory Size 64KB 1MB 16MB 4GB 4GB 4GB

Pipeline Stages NA 2 3 3 5 5

ALU Size 8-bit 16-bit 16-bit 32-bit 32-bit 32-bit

No. of Transistors 6,500 29,000 1,34,000 2,75,000 11,80,235 31,00,000

Year of Release 1976 1978 1982 1985 1989 1993

Operating Frequency 3 MHz 6 MHz 12 MHz 33 MHz 60 MHz 100 MHz

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