UNIT -04

Computer Arithmetic
Integer Representation
Integer arithmetic
Unsigned binary addition and subtraction
Unsigned binary multiplication algorithm
Booth algorithm
Unsigned binary division algorithm
Floating points representation
BCD arithmetic
 BCD adder
Arithmetic pipelining

1.1 Integer Representation

Integer Representation and Arithmetic

Integer Representation
Bit-- Binary Digit
 1 byte = 8 bits
 1 word = 2 bytes
Properties of integer representation
 Only one bit pattern per value
 Equal no of +ve and –ve value
 Max. range of value
 No gap in the range

Integer takes up two bytes; can be signed or unsigned

.
1. Unsigned Integers
 It is an integer without sign.
 Range between 0 and +veinfinity.
 can contain only magnitude of the number

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 1

Example-1: Represent decimal number 92 in unsigned binary number.
Simply convert it into Binary number, it contains only magnitude of the given number.
= (92)10
= (1x26+0x25+1x24+1x23+1x22+0x21+0x20)10
= (1011100)2
It’s 7 bit binary magnitude of the decimal number 92.
Example-2: Find range of 5 bit unsigned binary numbers. Also, find minimum and maximum
value in this range.
Therefore, range of 5 bit unsigned binary number is from 0 to (25-1) which is equal from
minimum value 0 (i.e., 00000) to maximum value 31 (i.e., 11111).
Example – 3
Store 7 in an 8–bit memory location.
Solution ,
Change the no in binary = 111
Add 5 0’s to make total no 8 bit = 00000111 (memory location)

Example – 4
Store 258 in an 16–bit memory location.
Solution ,
Change the no in binary = 10000010
Add 7 0’s to make total no 16 bit = 0000000100000010 (memory location)

Decimal 8-bit 16- bit allocation

allocation
7 00000111 0000000000000111
258 Overflow 0000000100000010
1245678 Overflow Overflow

2. Signed Integers
 Signed numbers contain sign flag, this representation distinguish positive and
negative numbers.

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  This technique contains both sign bit and magnitude of a number.
 For example, in representation of negative decimal numbers, we need to put
negative symbol in front of given decimal number.
Three ways:
 Sign-Magnitude
 1's Complement
 2's Complement

Sign-Magnitude

 Uses most significant bit of the word to represent the sign.

o 0 - Positive
o 1 - Negative.
 Rest of the number is encoded in magnitude part

Example

+37 = 00000000 00100101

-37 = 10000000 00100101
+6712 = 00011010 00111000
-6712 = 10011010 00111000
No. of bit required to represent any number in sign magnitude

If n = 4 then , Range = -7 to +7
If n = 5 then , Range = -15 to +15
If n = 6 then , Range = -31 to +31

Example +12 --------- 01100

-12 --------- 11100

1.2 Integer arithmetic

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1's Complement

 No change for positive number.

 Negative number is stored as bit-wise complement of corresponding positive number.
 Leftmost bit of positive number is 0. That of negative number is 1.

Example +12-------- 01100

-12 -------- 01100

10011 (1’s Complements)

196 = 00000000 11000100

-196 = 11111111 00111011

No. of bit required to represent any number in 1’s Complements

If n = 3 bits , -3 to +3
If n = 5 bits , -15 to +15

2's Complement

 Modern Method
 Positive number represented in same way as other two methods
 Negative number obtained by taking 1's Complement of positive number and adding 1.

Example -01
-6713 = 00011000 00011101
1's Comp = 11100111 11100010
Adding -----------------------------+1

2's Comp =11100111 11100011

Example -02
-15 = 00001111
1's Comp = 11110000
Adding ----- -------+1

2's Comp = 11110001

Example -03
-12 = 00001100
1's Comp = 11110011
Adding -----------+1

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 4

 2's Comp = 11110100

Example -Let take 8 bits register.

-4 ----- 00000100
1’s com. 11111011
Adding ------------+1
11111100

+4 0 0 0 0 0 1 0 0

 Word integer (16 bit) can represent numbers from -32,768 to 32,767.
 -215 .. 215-1
 Byte (8 bit) integer can represent numbers from -128 to 127.
 -27 .. 27-1

Example 8-bit representations of +12 and -12

Solution , +12
+12 -----00001100

1. Signed magnitude
2. Signed 1s complements
3. Signed 2s complements

0 0 0 0 1 1 0 0
0 0 0 0 1 1 0 0
0 0 0 0 1 1 0 0

Solution , -12
-12 -----00001100

1. Signed magnitude
2. Signed 1s complements
3. Signed 2s complements

1 0 0 0 1 1 0 0
1 1 1 1 0 0 1 1
1 1 1 1 0 1 0 0

1.3 Unsigned binary addition and subtraction

Binary Arithmetic

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Binary Addition
It is a key for binarysubtraction, multiplication, division. There are four rules of binary addition.

In fourth case, a binary addition is creating a sum of (1 + 1 = 10) i.e. 0 is written in the given
column and a carry of 1 over to the next column.

Example − Addition

Binary Subtraction
Subtraction and Borrow, these two words will be used very frequently for the binary subtraction.
There are four rules of binary subtraction.

Example − Subtraction

Binary Multiplication
Binary multiplication is similar to decimal multiplication. It is simpler than decimal multiplication
because only 0s and 1s are involved. There are four rules of binary multiplication.

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 6

Example − Multiplication

Binary Division
Binary division is similar to decimal division. It is called as the long division procedure.

Example − Division

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1.3 Unsigned binary multiplication algorithm

Example -Multiple the number 11 x 13 using unsigned binary multiplication algorithm.

 M = 1011 (4 bit) as also A should be 4 bit
 Q= 1101 (4 bit) count should be n=4.
 Carry (C) should be one bit.

C A Q OPERATION N0. OF
COUNT
0 0000 1101 Initially N= 4
0 1011 1101 C,A=A+M

0 0101 1110 LOGICAL SHIFT COUNT 3

RIGHT
0 0010 1111 LOGICAL RIGHT
SHIFT COUNT 2
0 1101 1111 C,A=A+M
0 0110 1111 LOGICAL SHIFT COUNT 1
RIGHT
1 0001 1111 C,A=A+M
0 1000 1111 LOGICAL SHIFT COUNT 0
RIGHT

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 8

1.4 Booth's Multiplication Algorithm

Following is the pictorial representation of the Booth's Algorithm:

In the above flowchart, initially, AC and Q-1 bits are set to 0, and the SC is a sequence counter that
represents the total bits set n, which is equal to the number of bits in the multiplier. There
are M that represent the multiplicand bits, and Q represents the multiplier bits. After that, we
encountered two bits of the multiplier as Q0 and Q- 1,

Working on the Booth Algorithm

1. Set the Multiplicand and Multiplier binary bits as M and Q, respectively.
2. Initially, we set the AC and Q -1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a sequence counter that is
continuously decremented till equal to the number of bits (n) or reached to 0.
4. A Q0 represents the last bit of the Q.
5. On each cycle of the booth algorithm, Q 0 and Q -1 bits will be checked on the following
parameters as follows:

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 9

 i. When two bits Q0 and Q -1 are 00 or 11, we simply perform the arithmetic shift right
operation (ashr) to the partial product AC. And the bits of Qn and Qn + 1 is
incremented by 1 bit.
ii. If the bits of Q0 and Q -1 is shows to 01, the multiplicand bits (M) will be added to the
AC (Accumulator register). After that, we perform the right shift operation to the AC
and Q bits by 1.
iii. If the bits of Q0 and Q -1 is shows to 10, the multiplicand bits (M) will be subtracted
from the AC (Accumulator register). After that, we perform the right shift operation
to the AC and Q bits by 1.
6. The operation continuously works till we reached n - 1 bit in the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the AC and QR registers.

Hardware Implementation of Booths Algorithm

The hardware implementation of the booth algorithm requires the register configuration shown in
the figure below.

Booth’s Algorithm Flowchart

We name the register as A, B and Q, AC, BR and QR respectively. Qn designates the least
significant bit of multiplier in the register QR. An extra flip-flop Qn+1is appended to QR to
facilitate a double inspection of the multiplier. Qn+1 is appended to QR to facilitate a double
inspection of the multiplier.

Example: Multiply the two numbers 7 and 3 by using the Booth's multiplication algorithm.

Ans. we need to convert 7 and 3 into binary numbers like 7 = (0111) and 3 = (0011).
M = 0111
Q=0011
Register size = 4 so SC = 4
- M = 1001 (2’S Complements of M)

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Now set 7 (in binary 0111) as multiplicand (M) and 3 (in binary 0011) as a multiplier (Q). And SC
(Sequence Count) represents the number of bits, and here we have 4 bits, so set the SC = 4. Also, it
shows the number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

AC Q Q-1 M = (0111) Operation SC

0000 0011 0 Initial

1001 0011 0 AC= AC-M 4
1100 1001 1 Arithmetic Right Shift
operations (ashr)
1110 0100 1 Arithmetic Right Shift 3
operations (ashr)

0101 0100 1 AC= A + M 2

0010 1010 0 Arithmetic right shift
operation
0001 0101 0 Arithmetic right shift 1
operation

The numerical example of the Booth's Multiplication Algorithm is 7 x 3 = 21 and the binary
representation of 21 is 10101. Here, we get the resultant in binary 00010101. Now we convert it
into decimal, as (000010101) 10 = 2*4 + 2*3 + 2*2 + 2*1 + 2*0 => 21.

Example: Multiply the two numbers -7 and 3 by using the Booth's multiplication
algorithm.

Ans. we need to convert 7 and 3 into binary numbers like 7 = (0111) and 3 = (0011).

M = -7 = 11001
Q=00011
Register size = 5
- M = 00111 (2’S Complements of M)

Now set 7 (in binary 0111) as multiplicand (M) and 3 (in binary 0011) as a multiplier (Q). And SC
(Sequence Count) represents the number of bits, and here we have 5 bits, so set the SC = 5. Also, it
shows the number of iteration cycles of the booth's algorithms and then cycles run SC = SC - 1 time.

AC Q Q-1 M = (11001) Operation SC

00000 00011 0 Initial

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00111 00011 0 AC= AC-M 5
00011 10001 1 Arithmetic Right Shift
operations (ashr)
00001 11000 1 Arithmetic Right Shift 4
operations (ashr)

11010 11000 1 AC= AC + M 3

11101 01100 0 Arithmetic right shift
operation
11110 10110 0 Arithmetic right shift 2
operation
11111 01011 0 Arithmetic right shift 1
operation

Here, (1111101011)

2s complements 0f (1111101011) is (0000010101)

Example: Multiply the two numbers -7 and -3 by using the Booth's multiplication
algorithm.

Ans. we need to convert -7 and -3 into binary numbers

M = -7 = 1001
Q=-3 = 1101
Register size = 4
- M = 00111 (2’S Complements of M)

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 12

Unsigned binary division algorithm

Let’s pick the step involved:

 Step-1: First the registers are initialized with corresponding values (Q = Dividend,
M = Divisor, A = 0, n = number of bits in dividend)
 Step-2: Then the content of register A and Q is shifted left as if they are a single
unit
 Step-3: Then content of register M is subtracted from A and result is stored in A
 Step-4: Then the most significant bit of the A is checked if it is 0 the least
significant bit of Q is set to 1 otherwise if it is 1 the least significant bit of Q is set to
0 and value of register A is restored i.e the value of A before the subtraction with M
 Step-5: The value of counter n is decremented
 Step-6: If the value of n becomes zero we get of the loop otherwise we repeat from
step 2
 Step-7: Finally, the register Q contain the quotient and A contain remainder

Examples:
Perform Division Restoring Algorithm

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 13

Dividend(Q)=11 = (1011)
No. of count = 4
Divisor(M)=3= (00011), MSB bit add as a borrow.
-M = 11101 (2S Compl. Of 00011)

n M A Q Operation

4 00011 00000 1011 Initialize

00011 00001 011_ shift left AQ

00011 11110 011_ A=A-M

00011 00001 0110 Q[0]=0 And restore A

3 00011 00010 110_ shift left AQ

00011 11111 110_ A=A-M

00011 00010 1100 Q[0]=0 and restore A

2 00011 00101 100_ shift left AQ

00011 00010 100_ A=A-M

00011 00010 1001 Q[0]=1

1 00011 00101 001_ shift left AQ

00011 00010 001_ A=A-M

00011 00010 0011 Q[0]=1

Remember to restore the value of A most significant bit of A is 1. As that register Q contain
the quotient, i.e. 3 and register A contain remainder 2

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 14

Binary Coded Decimal (BCD) code
In this code each decimal digit is represented by a 4-bit binary number. BCD is a way to express
each of the decimal digits with a binary code. In the BCD, with four bits we can represent sixteen
numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). The
remaining six code combinations i.e. 1010 to 1111 are invalid in BCD.

Advantages of BCD Codes

 It is very similar to decimal system.
 We need to remember binary equivalent of decimal numbers 0 to 9 only.
Disadvantages of BCD Codes
 The addition and subtraction of BCD have different rules.
 The BCD arithmetic is little more complicated.
 BCD needs more number of bits than binary to represent the decimal number. So BCD is less
efficient than binary.
Decimal or BCD Adder

The BCD-Adder is used in the computers and the calculators that perform arithmetic operation
directly in the decimal number system. The BCD-Adder accepts the binary-coded form of decimal
numbers. The Decimal-Adder requires a minimum of nine inputs and five outputs.

There is the following table used in designing of BCD-Adder.

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From the above table, it is clear that if the produced sum is between 1 to 9, the Binary and the BCD
code is the same. But for 10 to 19 decimal numbers, both the codes are different. In the above table,
the binary sum combinations from 10 to 19 give invalid BCD. There are the following points that
help the circuit to identify the invalid BCD.

1. It is obvious from the table that a correction is needed when the 'Binary Sum' has an output
carry K=1.
2. The other six combinations from 10 to 15 need correction in which the bit on the Z 8 position
is 1.
3. In the Binary sum of 8 and 9, the bit on the Z 8 position is also 1. So, the second step fails, and
we need to modify it.
4. To distinguish these two numbers, we specify that the bit on the Z4 or Z2 position also needs
to be 1 with the bit of Z8
5. The condition for a correction and an output carry can be expressed by the Boolean
function:C=K+Z8.Z4+Z8.Z2

Once the circuit found the invalid BCD, the circuit adds the binary number of 6 into the invalid BCD
code to make it valid.

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In the above diagram,

1. We take a 4-bit Binary-Adder, which takes addend and augend bits as an input with an input
carry 'Carry in'.
2. The Binary-Adder produces five outputs, i.e., Z8, Z4, Z2, Z1, and an output carry K.
3. With the help of the output carry K and Z8, Z4, Z2, Z1 outputs, the logical circuit is designed
to identify the Cout
4. The Z8, Z4, Z2, and Z1 outputs of the binary adder are passed into the 2 nd 4-bit binary adder
as an Augend.
5. The addend bit of the 2nd 4-bit binary adder is designed in such a way that the 1st and the
4th bit of the addend number are 0 and the 2nd and the 3rd bit are the same as Cout. When the
value of Cout is 0, the addend number will be 0000, which produce the same result as the
1st 4-bit binary number. But when the value of the Cout is 1, the addend bit will be 0110, i.e.,
6, which adds with the augent to get the valid BCD number.

Example: 1001+1000

1. First, add both the numbers using a 4-bit binary adder and pass the input carry to 0.
2. The binary adder produced the result 0001 and carried output 'K' 1.

Then, find the Cout value to identify that the produced BCD is invalid or valid using the expression
Cout=K+Z8.Z4+Z8.Z2.

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K=1
Z8 = 0
Z4 = 0
Z2 = 0
Cout = 1+0*0+0*0
Cout = 1+0+0
Cout = 1

The value of Cout is 1, which expresses that the produced BCD code is invalid. Then, add the output of the
1st 4-bit binary adder with 0110.
= 0001+0110
= 0111
The BCD is represented by the carry output as:
BCD=Cout Z8 Z4 Z2 Z1=1 0 1 1 1

Note - To understand the logic

Sum Equals 9 or less with carry 0

Let us consider additions of 3 and 6 in BCD.

The addition is carried out as in normal binary addition and the sum is 1 0 0 1, which is BCD
code for 9.

Sum greater than 9 with carry 0

After addition of 6 carry is produced into the second decimal position.

Sum equals 9 or less with carry 1

Er. Manish Kr.Yadav(Com.Arithmetic, Unit-4) 18

Pipeline
Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is
divided into stages and these stages are connected with one another to form a pipe like structure.
Instructions enter from one end and exit from another end.

Types of Pipeline
It is divided into 2 categories:
1. Arithmetic Pipeline
2. Instruction Pipeline

Arithmetic Pipeline

Arithmetic Pipelines are mostly used in high-speed computers. They are used to implement floating-point
operations, multiplication of fixed-point numbers, and similar computations encountered in scientific
problems.

To understand the concepts of arithmetic pipeline in a more convenient way, let us consider an example
of a pipeline unit for floating-point addition and subtraction.

The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers defined
as:

X = A * 2a = 0.9504 * 103
Y = B * 2b = 0.8200 * 102

Where A and B are two fractions that represent the mantissa and a and b are the exponents.

The combined operation of floating-point addition and subtraction is divided into four segments. Each
segment contains the corresponding suboperation to be performed in the given pipeline. The
suboperations that are shown in the four segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

We will discuss each suboperation in a more detailed manner later in this section.

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The following block diagram represents the suboperations performed in each segment of the pipeline.

Note: Registers are placed after each suboperation to store the intermediate results.

1. Compare exponents by subtraction:

The exponents are compared by subtracting them to determine their difference. The larger exponent is
chosen as the exponent of the result.

The difference of the exponents, i.e., 3 - 2 = 1 determines how many times the mantissa associated with
the smaller exponent must be shifted to the right.

2. Align the mantissas:

The mantissa associated with the smaller exponent is shifted according to the difference of exponents
determined in segment one.

X = 0.9504 * 103
Y = 0.08200 * 103

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3. Add mantissas:

The two mantissas are added in segment three.

Z = X + Y = 1.0324 * 103

4. Normalize the result:

After normalization, the result is written as:

Z = 0.1324 * 104

Example:
Let us consider two numbers,
X=0.3214*10^3 and Y=0.4500*10^2

Explanation:
First of all the two exponents are subtracted to give 3-2=1. Thus 3 becomes the exponent of result and the
smaller exponent is shifted 1 times to the right to give

Y=0.0450*10^3

Finally the two numbers are added to produce

Z=0.3664*10^3

As the result is already normalized the result remains the same.

Advantages of Pipelining

1. The cycle time of the processor is reduced.

2. It increases the throughput of the system
3. It makes the system reliable.

Disadvantages of Pipelining

1. The design of pipelined processor is complex and costly to manufacture.

2. The instruction latency is more.

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Floating-Point Representation
The floating number representation of a number has two part: the first part represents a
signed fixed point number called mantissa. The second part of designates the position
of the decimal (or binary) point and is called the exponent. The fixed-point mantissa
may be fraction or an integer.
Floating point is always interpreted to represent a number in the following form:

= ±mxr ±e
Only the mantissa m and the exponent e are physically represented in the register
(including their sign). A floating-point binary number is represented in a similar manner
except that is uses base 2 for the exponent. A floating-point number is said to be
normalized if the most significant digit of the mantissa is 1.

Example −Suppose number is using 32-bit format: the 1 bit sign bit, 8 bits for signed
exponent, and 23 bits for the fractional part. The leading bit 1 is not stored (as it is
always 1 for a normalized number) and is referred to as a “hidden bit”.
Then −53.5 is normalized as -53.5=(-110101.1)2=(-1.101011)x25 , which is represented
as following below,

Where 00000101 is the 8-bit binary value of exponent value +5.

These numbers are represented as following below,

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Example
1) 215.37 = 0.21537 x 10 +3

Sign Mantissa Base exponential

2) 1000.110 = 0.1000110 X 2+4

IEEE Floating point Number Representation

IEEE (Institute of Electrical and Electronics Engineers) has standardized Floating-Point
Representation as following diagram.

According to IEEE 754 standard, the floating-point number is represented in following

ways:

 Half Precision (16 bit): 1 sign bit, 5 bit exponent, and 10 bit mantissa
 Single Precision (32 bit): 1 sign bit, 8 bit exponent, and 23 bit mantissa
 Double Precision (64 bit): 1 sign bit, 11 bit exponent, and 52 bit mantissa
 Quadruple Precision (128 bit): 1 sign bit, 15 bit exponent, and 112 bit mantissa

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