Microprocessors Microprocessors Lec. No.

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Introduction
A Microprocessor incorporates most or all of the functions of a computer's
central processing unit (CPU) on a single integrated circuit. It is the part of
the microcomputer that executes instructions of the program and processes
data. It is responsible for performing all arithmetic operations and making the
logical decisions initiated by the computer’s program. In addition to
arithmetic and logic functions, the MPU controls overall system operation.

Figure 1 Microprocessor Based Microcomputer System

The hardware of a microcomputer system can be divided into four

functional sections: the Input unit, Microprocessing Unit, Memory Unit,
and Output Unit. Input and Output units are the means by which the MPU
communicates with the outside world. Input unit can be: keyboard, mouse,
scanner, etc. Output unit can be: monitor, printer, etc. Memory unit can be
divided into two types Primary which is normally smaller in size and is
used for temporary storage of active information (typically ROM, RAM).
And Secondary which is normally larger in size and used for long-term
storage of information (like Hard disk, Floppy, CD, etc.).

Memory Unit
Primary Storage Unit
Program Data Secondary
Storage Storage Storage Unit
Memory Memory

Input Output
Unit MPU Unit

Figure 2 General Architecture of a Microcomputer System

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Basic Definitions
o A bit or binary digit is the basic unit of information in computing and
telecommunications; it is the amount of information that can be stored
by a digital device.

o The byte is an ordered collection of bits, in which each bit denotes the
binary value of 1 or 0. The size of a byte is typically hardware
dependent, but the modern de facto standard is 8 bits, as this is a
convenient power of 2. Most of the numeric values used by many
applications are representable in 8 bits and processor designers
optimize for this common usage.

History of Microprocessors
Microprocessors generally are categorized in terms of the maximum number
of binary bits in the data they process – that is, their word length. Over time,
five standard data widths have evolved for microprocessors: 4-bit, 8-bit, 16-
bit, 32-bit, 64-bit.
There are so many manufacturers of Microprocessors, but only two
companies have been producing popular microprocessors: Intel and Motorola.
Table 1 lists some of types that belong to these companies (families) of
microprocessors.

The 8086 has data bus width of 16-bit, and is able to address 1Megabyte of
memory.
It is important to note that 80286, 80386, 80486, and Pentium-Pentium4
microprocessors are upward compatible with the 8086 Architecture. This
means that 8086 code will run on the 80286, 80386, 80486, and Pentium
Processors, but the reverse is not true if any of the new instructions are in use.
Beside to the general-purpose microprocessors, these families involve
another type called special-purpose microprocessors that used in embedded
control applications. This type of embedded microprocessors is called
microcontroller. The 8080, 8051, 8048, 80186, 80C186XL are some
examples of microcontroller.

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Table 1 Some Types of Microprocessors

Type Data bus width Memory size

Intel family:
8085 8 64K
8086 16 1M
8088 8 1M
80186 16 1M
80188 8 1M
80286 16 16M
80386SX 16 16M
80386DX 32 4G
80386EX 16 64M
80486 32 4G + 8 (16 in later models)K cache
Pentium 64 4G + 16K cache
PentiumIII , Pentium4 64 64G +32K L1 cache +256 L2 cache
Motorola family:
6800 8 64K
68060 64 4G + 16K cache

Numbers System
For microprocessors and microcomputers, information such as instructions,
data, and addresses are described with numbers. The types of numbers used
are not normally the decimal numbers we are familiar with; instead, binary
and hexadecimal numbers are used.

a) Decimal Number System

Ten different symbols are used (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). These make up
the decimal number system.

MSD LSD
10+3 10+2 10+1 100 . 10-1 10-2 10-3
weights 1000 100 10 1 . 1/10 1/100 1/1000

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b) Binary Number System

The digital electronic devices and circuits in a microcomputer system operate
only in one of two states, on or off. For this reason, binary numbers instead of
decimal numbers are used to describe their operation. Two symbols (0, and 1)
are used to form all numbers.

MSD LSD
2+3 2+2 2+1 20 . 2-1 2-2 2-3
weights 8 4 2 1 . 1/2 1/4 1/8

c) Hexadecimal Number System

Machine language programs, addresses, and data, which are actually binary
information, are normally expressed as hexadecimal numbers because they
offer a more compact notation for representing this type of information.
Symbols of the hexadecimal number system are (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A,
B, C, D, E, and F).

MSD LSD

16+3 16+2 16+1 160 . 16-1 16-2

weights 4096 256 16 1 . 1/16 1/256

Software Architecture
The 8086 microprocessor employs parallel processing – that is, it is
implemented with several simultaneously operating processing units. It
contains two processing units: the Bus Interface Unit (BIU) and the
Execution Unit (EU). Each unit has dedicated functions and both operate at
the same time. This parallel processing makes the fetch and execution of

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instructions independent operations. This results in efficient use of the system

bus and higher performance for the microcomputer system.

Figure 1 Execution & Bus Interface Units

The BIU is responsible for performing all external bus operations, such as
instruction fetching, reading and writing of data operands for memory,
address generating, and inputting or outputting data for input/output
peripherals. These operations take place over the system bus. This bus
includes 16-bit bidirectional data bus, a 20-bit address bus, and the signals
needed to control transfer over the bus. It is also responsible for instruction
queuing.

Software Model
Software architecture of 8086 includes 13 16-bit internal registers: the
instruction pointer, four data registers, two pointer registers, two index
registers, and four segment registers. In addition, there is status register with
nine of its bits implemented as status & control flags.

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Figure 2 Software Model of 8086

As can be shown in Figure above, the 8086 architecture implements
independent memory and input/output spaces; the memory address space is
1048576 bytes (1Mbyte) in length and I/O address space is 65536 bytes
(64Kbyte) in length.

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Memory Address Space and Data Organization

The 8086 supports 1Mbyte of external memory organized as individual bytes
of data stored at consecutive addresses over the address range 00000 16 to
FFFFF16. Therefore, the memory is actually organized as 8-bit bytes. Any two
consecutive bytes can be accessed as a word of data (the lower-addressed byte
is the least significant byte of the word, and the higher- addressed byte is its
most significant byte).

Memory Address Memory Content

0072416 0216
0072516 5516

Figure 3 Storing a Word of Data in Memory

The storage location at the lower address 0072416 contains the value 0216. The
content of the next higher address storage location 0072516 is 5516. These two
bytes represent the word 550216. This word has its least significant byte
stored at even address 0072416 so it is called aligned word, otherwise if the
least significant byte is stored at odd address, it is called misaligned word.
Figure 4 shows some aligned and misaligned words of data, words 0, 2, 4, and
6 are aligned words, while words 1 and 5 are misaligned words. A double
word corresponds to four consecutive bytes of data stored in memory.

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Figure 4 Examples of Aligned & Misaligned Data Words

Memory Segmentation
Even though the 8086 has a 1Mbyte address space, not all this memory is
active at one time. Actually, the 1Mbytes of memory are partitioned into
64Kbyte (65,536) segments. A segment represents an independently
addressable unit of memory consisting of 64 K consecutive byte-wide storage
locations. Each segment is assigned a base address that identifies its starting
point (its lowest address byte-storage location). Only four of these 64 Kbytes
segments are active at a time: the code segment, stack segment, data segment,
and extra segment.

Internal Registers
o Segment Registers The segments of memory that are active are
identified by the values of addresses held in 8086’s four internal
segment registers: CS (code segment), SS (stack segment), DS (data
segment), and ES (extra segment). Each of these registers contains a
16-bit base address that points to the lowest addressed byte of the
segment in memory.
o Instruction Pointer Register It is also 16-bit in length and identifies the
location of the next word of instruction code to be fetched from the
current code segment of memory. It contains the offset of the next word
of instruction code instead of its actual address. Every time a word of

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code is fetched from memory, the 8086 updates the value in IP such
that it points to the first byte of the next sequential word of code (IP
incremented by 2).
o Data Registers The 8086 has four general purpose data registers: the
accumulator register (A), the base register (B), the count register (C),
and the data register (D). These names imply special functions they are
meant to perform.

Figure 5 General Purpose Data Registers

During program execution they hold temporary values of frequently used

intermediate results. The advantage of storing these data in internal registers
instead of memory during processing is that they can be accessed much faster.
Each of these registers can be accessed either as a whole 16-bit (for word data
operations) or as two 8-bit registers (for byte wide data operations). When
software places a new value in one byte of a register, for instance AL, the
value in the other byte (AH), does not change.

Table 1 Dedicated Registers Functions

Register operation
AX Word multiply, word divide, word I/O
AL Byte multiply, byte divide, byte I/O, translate, decimal arithmetic
AH Byte multiply, byte divide
BX Translate
CX String operations, loops
CL Variable shift and rotate
DX Word multiply, word divide, indirect I/O

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o Pointer Registers They store offset addresses (the displacement of a

storage location in memory from the segment base address in a segment
register). Software uses the value held in a pointer register to access
memory locations relative to the stack segment register. They are only
accessed as words. The two pointer registers are: the stack pointer (SP)
and base pointer (BP). The value in SP always represents the offset of
the next stack location that is to be accessed (Top of Stack). BP also
represents an offset relative to the SS. One common use of BP is to
reference parameters that are passed to a subroutine by way of the
stack.
o Indexed Registers They also store offset addresses from the data
segment or extra segment registers. They are only accessed as words.
For some operations, an operand that is to be processed may be located
in memory instead of the internal registers. In this case, an index
address is used to identify the location of the operand in memory. The
source index (SI) register holds an offset address that identifies the
location of a source operand, and the destination index (DI) register
holds an offset for a destination operand.
o Status Register (flag register) Is 16-bit register in which only nine of its
bits are implemented. Six of these bits represent status flags: the carry
flag (CF), parity flag (PF), auxiliary flag (AF), zero flag (ZF), sign flag
(SF), and overflow flag (OF). The logic state of these status flags
indicate conditions that are produced as the result of executing an
instruction. The other three flags that provide control functions are: the
direction flag (DF), interrupt flag (IF), and trap flag (TF). The
instruction set of the 8086 includes instructions for saving, loading, or
manipulation the flags.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF

Figure 6 Status Register

The status flags:

1. The carry flag: CF is set if there is a carry-out or a borrow-in for the
most significant bit of the result during the execution of an instruction.
Otherwise CF is reset.

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2. The parity flag: PF is set if the result produced by the instruction has
even parity (if it contains an even number of bits at the 1 logic level). If
parity is odd, PF is reset.
3. The auxiliary flag: AF is set if there is a carry-out from the low nibble
into the high nibble or a borrow-in from the high nibble into the low
nibble of the lower byte in a 16-bit word. Otherwise, AF is reset.
4. The zero flag: ZF is set if the result produced by an instruction is zero.
Otherwise, ZF is reset.
5. The sign flag: The MSB of the result is copied into SF. Thus, SF is set
if the result is a negative number or reset if it is positive.
6. The overflow flag: When OF is set, it indicates that the signed result is
out of range. If the result is not out of range, OF remains reset.

The control flags:

1. The trap flag: If TF is set, the 8086 goes into the single-step mode of
operation. When in the single-step mode, it executes an instruction and
then jumps to a special service routine that may determine the effect of
executing the instruction. This type of operation is very useful for
debugging programs.
2. The interrupt flag: For the 8086 to recognize maskable interrupt
requests at its interrupt (INT) input, the IF flag must be set. When IF is
reset, requests at INT are ignored and the maskable interrupt interface
is disabled.
3. The direction flag: The logic level of DF determines the direction in
which string operations will occur. When set, the string instructions
automatically decrement the address; therefore the string data transfers
proceed from high address to low address. On the other hand, resetting
DF causes the string address to be incremented (data transfers proceed
from low address to high address).

Generating a Memory Address

A segment base and an offset describe a logical address; both are 16-bit
quantities. However, the physical address that is used to access memory is 20-
bits in length. The generation of the physical address involves combining a
16-bit offset value (located in IP, BX, SI, DI, SP, or BP) and a 16-bit segment
base value (located in CS, DS, SS, or ES).
The segment base address represents the starting location of the 64 Kbyte
segment in memory – that is, the lowest address byte in the segment. The
offset identifies the distance in bytes that the storage location of interest
resides from this starting address. Therefore, the lowest address byte in a

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segment has an offset of 000016, and the highest address byte has an offset of
FFFF16.
To obtain the physical address, the value in the segment register is shifted left
by four bits (with its LSBs filled with zeros). The offset value is then added.
The result of this addition is 20-bit physical address.

Figure 7 Generating a Physical Address

Many different logical addresses map to the same physical address location in
memory. If a segment register contains 002B16 with offset 001316, it will map
to the same physical address in the above example. Try base segment 002C 16
with a new offset of 000316.

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The Stack

The stack is used for temporary storage of information such as data or

address. It is 64 Kbytes long and is organized as 32 Kwords.

Figure 8 Stack segment of memory

The address obtained from the contents of SS and SP (SS:SP) is the address
of the last storage location in the stack to which data were pushed, it is called
top of the stack. The highest-addressed word location in the stack
(SS:FFFE16) is called bottom of the stack. The lowest-addressed word
location in the stack (SS:000016) is called end of the stack.
When a call instruction is executed, the 8086 automatically pushes the current
values in CS and IP onto the stack. As part of the subroutine, the contents of
other registers may also be saved on the stack by executing push instructions.
Near the end of the subroutine, pop instructions are included to pop values
from the stack back into their corresponding internal registers. At the end of
the subroutine, a return instruction causes the values of CS and IP to be
popped off the stack and put back into the internal register where they
originally resided.
Data transferred to and from the stack are word wide (not byte-wide). Each
time a word is to be pushed onto the top of stack, the value in SP is first
automatically decremented by two, and then the content of the register is
written into the stack.

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When a value is popped from the top of stack, the reverse occurs. Its content
is first popped off the stack and put into the specific register, and then SP is
automatically incremented by two.

Software
A microcomputer does not know how to process data, it must be told where to
get data, what to do with the data, and where to put the results when it is done.
These are the jobs of the software. The sequence of commands to tell a
microcomputer what to do is called a program. Each command in a program
is an instruction.
Programs must always be coded in machine language before they can be
executed by the microprocessor. A program written in machine language is
often referred to as machine code (instruction is encoded using 0s and 1s). It
is almost impossible to write programs directly in machine language. For this
reason, programs are normally written in 8086 assembly language or a high-
level language such as C. In assembly language, each of the operations is
described with alphanumeric symbols instead of 0s and 1s.
An instruction can be divided into two parts: operation code (opcode) and
operands. The opcode is the part of instruction that identifies the operation
that is to be performed (add, subtract, move, …). Each opcode is assigned a
unique letter combination called a mnemonic (ADD, SUB, MOV, …).
Operands describe the data are to be processed as the microprocessor carries
out the operation specified by the opcode. They identify whether the source
and destination of the data are registers within the MPU or storage locations
in data memory.
The assembler is the program that translates the assembly language programs
to an equivalent machine language program for execution by microprocessor.
The compiler is the program that converts high-level language statements to
machine code instructions.

Addressing modes
An addressing mode is a method of specifying an operand. The 8086 is
provided with various addressing modes to access operands. The data may be
part of the instruction, may reside in one of the internal registers, may be
stored in memory, or may be held at an I/O port. The addressing modes are
categorized as following:
1- Register operand addressing mode.
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2- Immediate operand addressing mode.

3- Memory operand addressing modes;
a- Direct addressing mode.
b- Register indirect addressing mode.
c- Based addressing mode.
d- Indexed addressing mode.
e- Based-indexed addressing mode.

o Register operand addressing mode the operand to be accessed is

specified as residing in an internal register. For example:
MOV AX, BX
This stands for “move the content of BX (source operand) to AX (destination
operand)”. Both operands have been specified as the word content of internal
registers.

o Immediate operand addressing mode the operand to be accessed is

part of instruction instead of the content of a register or memory
location. It can be 8-bit or 16-bit in length. This addressing mode can
only be used to specify a source operand. For example:
MOV AL, 15H
o Memory operand addressing modes to reference an operand in
memory, the 8086 must calculate the physical address of the operand
and then initiate a read or write operation of this storage location. 8086
is provided with group of memory addressing modes:

a- Direct addressing mode the instruction op-code is followed by effective

address. For example:
MOV CX, [1234H]

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This stands for “move the content of memory location with offset 1234H in
the current data segment to CX”.

b- Register indirect addressing mode the effective address resides in either a

base register (BX or BP) or an index register (SI or DI). For example:
MOV AX, [SI]

c- Based addressing mode the effective address of the operand is obtained by

adding a direct displacement to the content of either BX or BP register. For
example:
MOV [BX] + 1234H, AL

d- Indexed addressing mode the physical address is obtained from the value
in a segment register, an index register (SI or DI), and a displacement. For
example:
MOV AL, [SI] + 1234H

e- Based-indexed addressing mode combines the based and indexed

addressing modes. For example:
MOV AH, [BX] [SI] + 1234H

The 8086 Instruction Set

The microprocessor’s instruction set defines the basic operations that a
programmer can specify to the device to perform. The instructions are
organized into groups of functionality related instructions. The instruction set
is categorized as following

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8086 Instruction Set

Integer instructions Control flow instructions

1- Data transfer instructions 1- Flag-control instructions

2- Arithmetic instructions 2- Compare instruction

3- Logic instructions 3- Jump instructions

4- Shift instructions 4- Subroutine-handling instructions

5- Rotate instructions 5- Loop-handling instructions

6- String-handling instructions

Integer Instructions

1- Data Transfer Instructions

The 8086 has group of data-transfer instructions provided to move data either
between its internal registers or between an internal register and a storage
location in memory. This group includes:

o MOV Instruction transfers data from a source operand to a destination

operand. It cannot transfer data directly between a source and a
destination which both reside in memory; instead, the data must first be
moved from memory into an internal register with one MOV
instruction and then moved to the new location in memory with a
second MOV instruction. The fact that the instruction corresponds to
byte or word data is designated by the way in which operands are
specified.

Mnemonic Meaning Format Operation Flags affected

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MOV Move MOV D, S (S) (D) None

The immediate data cannot be directly loaded into a segment register; it must
be first loaded to AX then copied into the appropriate segment register.

Examples on MOV instruction:

MOV DX, CS it stands for “move the content of CS into DX”.

Assume CS= 0100H, execution of this instruction

makes DX= CS= 0100H

MOV [1212H], AX it stands for “move the content of AX to the memory

location whose offset is 1212H from the starting of

the current data segment”. Assume DS= 0200H, then

the effect of this instruction is:

(AL) (Memory location 03212H) and

(AH) (Memory location 03213H)

o XCHG Instruction is used to exchange the contents of two registers or

register with storage location in memory (this can also be done using
multiple MOV instructions). It is used to swap data between source and
destination operands.

Mnemonic Meaning Format Operation Flags affected

XCHG Exchange XCHG D, S (S) (D) None

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o XLAT Instruction the translate instruction is provided to simplify

implementation of the look-up table operation. When using XLAT, the
content of BX represents the offset of the starting address of the look-
up table from the beginning of the current data segment. The content of
AL represents the offset of the element to be accessed from the
beginning of the look-up table. This 8-bit element address permits a
table with up to 256 elements. The values in both registers must be
initialized prior to execution of XLAT instruction.

Mnemonic Meaning Format Operation Flags affected

XLAT Translate XLAT ((AL) + (BX) + (DS)0) (AL) None

Execution of XLAT replaces the content of AL by the content of the accessed

look-up table location. It is used for code conversions.

o LEA, LDS, LES Instructions these instructions give the programmer

the ability to load a segment and general purpose register with an
address directly from memory. They are: load register with effective
address (LEA), load register and data segment register (LDS), and load
register and extra segment register (LES). They either load a 16-bit
offset address into general purpose register or a 16-bit offset address
into general purpose register together with a 16-bit segment address
into either DS or ES.

Flags
Mnemonic Meaning Format Operation
affected
Load effective
LEA address
LEA reg16, EA EA (Reg16) None
EA (Reg16)
LDS Load register & DS LDS reg16, EA
EA + 2 (DS)
None
EA (Reg16)
LES Load register & ES LES reg16, EA
EA + 2 (ES)
None

LDS and LES are able to load a complete address pointer that is stored in
memory (executing them can activate a new data segment and extra segment).

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2- Arithmetic Instructions

The instruction set of 8086 contains a variety of arithmetic instructions; they

include instructions for addition, subtraction, multiplication, and division
operations.

Addition Instructions

Mnemonic Meaning Format Operation Flags affected

(S) + (D) (D) OF, SF, ZF,
ADD Addition ADD D, S
Carry (CF) AF,PF, CF
Add with (S) + (D) + (CF) (D) OF, SF, ZF,
ADC ADC D, S
carry Carry (CF) AF,PF, CF
Increment OF, SF, ZF,
INC INC D (D) + 1 (D)
by 1 AF,PF
ASCII AF, CF
AAA adjust for AAA (OF, SF, ZF,
addition PFundefined)
Decimal (SF, ZF, AF,
DAA adjust for DAA PF, CF, OF
addition undefined)

o ADD Instruction used to add an immediate operand to the content of

the accumulator, the content of another register, or the content of a
storage location in memory. It also allows addition of the content of
two registers or the content of a register and a storage location in
memory.

o ADC Instruction works similarly to the ADD instruction, but in this

case, the content of the carry flag is also added. It is primarily used for
multiword add operations.

(S) + (D) + (CF) (D)

o INC Instruction adds 1 to the specified operand. It is typically used to

increment the values of a count or address. Its operands can be the
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content of a 16-bit register or 8-bit register or a storage location in

memory. For example

INC AH

o AAA Instruction the previous addition instructions can also be used to

add numbers expressed in ASCII code, provided the binary result that
is produced is converted back to its equivalent ASCII representation.
The AAA instruction should be executed immediately after the ADD
instruction that adds ASCII data. AAA can adjust only data that are in
AL, therefore; the destination register for ADD instructions that
process ASCII numbers should be AL. Executing AAA instruction
causes the content of AL to be replaced by its equivalent decimal value.
It can affect the AF and CF.

o DAA Instruction used to perform an adjust operation similar to AAA

but for the addition of packed BCD numbers instead of ASCII
numbers. The adjustment is performed on the value in AL. For example

ADD AL, BL

DAA

The contents of AL and BL must be packed BCD numbers (two BCD digits
packed into a byte). The adjusted result in AL is again a packed BCD byte.

Subtraction Instructions

Mnemonic Meaning Format Operation Flags affected

(D) - (S) (D) OF, SF, ZF,
SUB Subtract SUB D, S
Borrow (CF) AF,PF, CF
Subtract
(D) - (S) - (CF) (D) OF, SF, ZF,
SBB with SBB D, S
borrow
Borrow (CF) AF,PF, CF
Decrement OF, SF, ZF,
DEC DEC D (D) - 1 (D)
by 1 AF,PF

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0 – (D) (D) OF, SF, ZF,

NEG Negate NEG D
1 (CF) AF,PF, CF
SF, ZF,AF,
Decimal
PF, CF
DAS adjust for DAS
subtraction
(OF
undefined)
AF, CF
ASCII
(OF, SF, ZF,
AAS adjust for AAS
subtraction PF
undefined)

o SUB Instruction used to subtract the value of a source operand from a

destination operand. The borrow-in that may occur from the most
significant bit is reflected in the carry flag.

o SBB Instruction it is similar to the SUB (subtracts source operand

from destination operand), it also subtract the carry flag from the
destination. SBB is primarily used for multiword subtract operations.

o DEC Instruction used to subtract 1 from its operand.

o NEG Instruction it causes the value of its operand to be replaced by its

negative (the operand is subtracted from zero). The subtraction is
performed by the processor hardware using 2’s-complement arithmetic.
To obtain the correct value of the carry flag that results from a NEG
operation, the carry flag generated by the add operation used in the 2’s-
complement subtraction must be complemented. NEG instruction can
work on operands in general-purpose register or a storage location in
memory.

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o DAS Instruction used to adjust the result of subtracting two packed

BCD numbers to produce the corresponding decimal number. The
result of subtraction must be stored in AL register.

o AAS Instruction used to adjust the result of subtracting two ASCII

numbers to produce the corresponding decimal number. The result of
subtraction must be stored in AL register.

Multiplication and Division Instructions

Mnemonic Meaning Format Operation Flags affected
OF, CF
Multiplication (AL).(S8) (AX)
MUL (unsigned)
MUL S (SF, ZF, AF,
(AX).(S16) (DX),(AX)
PF undefined)
(1) Q((AX)/(S8)) (AL)
R((AX)/(S8)) (AH)
(2) Q((DX,AX)/(S16)) (AX) (OF, SF, ZF,
Division
DIV (unsigned)
DIV S R((DX,AX)/(S16) (DX) AF, PF, CF
If Q exceeds FFH in case (1) or undefined)
FFFFH in case (2), then type0
interrupt occurs
Integer OF, CF
(AL).(S8) (AX)
IMUL multiplication IMUL S (SF, ZF, AF,
(signed) (AX).(S16) (DX),(AX)
PF undefined)
(1) Q((AX)/(S8)) (AL)
R((AX)/(S8)) (AH)
(2) Q((DX,AX)/(S16)) (AX) (OF, SF, ZF,
Integer
R((DX,AX)/(S16) (DX)
IDIV division IDIV S If Q is positive and exceeds AF, PF, CF
(signed) 7FFFH or if Q is negative and undefined)
becomes less than 8001H, then
type0 interrupt occurs
SF, ZF, PF
Adjust AL for Q((AL)/10) (AH)
AAM multiplication
AAM (OF, AF, CF
R((AL)/10) (AL)
undefined)
SF, ZF, PF
Adjust AX for (AH).10 + (AL) (AL)
AAD division
AAD (OF, AF, CF
00 (AH)
undefined)
Convert byte
CBW to word
CBW (MSBit of AL) (All bits of AH) None
Convert word
CWD to double word
CWD (MSBit of AX) (All bits of DX) None

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o MUL Instruction used to multiply unsigned numbers. A single byte-

wide or word-wide source operand is specified in a multiplication
instruction, the other operand (destination) is already assumed to be in
AL for 8-bit multiplication or AX for 16-bit multiplication. The result
is stored in AX for 8-bit multiplication, and in DX, AX for 16-bit
multiplication. The source operand can be register or content of
memory location.

o IMUL Instruction same as MUL instruction but used to multiply

signed numbers.

o DIV Instruction used to divide unsigned numbers. Again just the

source operand is specified. The other operand is either AX for 16-bit
dividends or both DX and AX for 32-bit dividends. The quotient of
dividing 16-bit dividend by 8-bit divisor is stored in AL and the
remainder stored in AH. The quotient of dividing 32-bit dividend by
16-bit divisor is stored in AX and the remainder stored in DX. The
source operand can be register or content of memory location.

o IDIV Instruction same as DIV instruction but used to divide signed

numbers.

o AAM Instruction adjusts AL after multiplying unpacked BCD

numbers. It must be included directly after the multiply instruction of
BCD numbers.

o AAD Instruction adjusts AX before dividing unpacked BCD numbers.

It must be included directly before the divide instruction of BCD
numbers.

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o CBW Instruction extends the sign of the dividend to fill AX register

(the sign extension does not change the value for the data).

o CWD Instruction extends the sign of the dividend to fill DX register

(the sign extension does not change the value for the data).

The last two instructions are used to allow division of 8-bit dividend in AL by
8-bit divisor and 16-bit dividend in AX by 16-bit divisor

3- Logic Instructions

The 8086 has instructions for performing the logic operations AND, OR,
exclusive-OR, and NOT bit-wise on byte-wide and word-wide data.

Mnemonic Meaning Format Operation Flags affected

OF, SF, ZF, PF, CF
AND Logical AND AND D, S (S) . (D) (D) (AF undefined)
OF, SF, ZF, PF, CF
OR Logical OR OR D, S (S) + (D) (D) (AF undefined)
Logical OF, SF, ZF, PF, CF
XOR XOR D, S (S) (D) (D) (AF undefined)
Exclusive-OR
NOT Logical NOT NOT D None
(D) (D)

o AND Instruction causes the content of source operand to be ANDed

with the contents of destination operand. The result is reflected by the
new content of destination. AND instruction is used to clear certain
bit(s) of a byte or word.

o OR Instruction used to set bit(s) in register or a storage location in

memory.

o XOR Instruction used to reverse the logic level of bit(s) in register or a

storage location in memory (toggling the bit).

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o NOT Instruction used to obtain the 1’s complement of destination

operand (internal register or a location in memory).

4- Shift Instructions

The four shift instructions of 8086 can perform two basic types of shift
operations; the logical and arithmetic shifts. Each of these operations can be
performed to the right or to the left. These instructions are used to align data,
isolate bits of a byte or word so that it can be tested, and to perform simple
multiply and divide computations.

Mnemonic Meaning Format Operation Flags affected

Shift the (D) left by
Shift the number of bit CF, PF, SF, ZF
arithmetic left/ positions equal to (AF undefined)
SAL/SHL Shift logical
SAL/SHL D, Count
Count and fill the (OF undefined
left vacated bits positions if count ≠ 1)
on the right with zeros
Shift the (D) right by
the number of bit CF, PF, SF, ZF
Shift logical positions equal to (AF undefined)
SHR right
SHR D, Count
Count and fill the (OF undefined
vacated bits positions if count ≠ 1)
on the left with zeros
Shift the (D) right by
the number of bit
CF, PF, SF, ZF
Shift positions equal to
(AF undefined)
SAR arithmetic SAR D, Count Count and fill the
(OF undefined
right vacated bits positions
if count ≠ 1)
on the left with the
original MSBit

o SAL/SHL Instruction shifts the destination operand (register or storage

location in memory) to the left by number of bits specified by count.
The count can be either 1 for 1-bit shift, or the value in CL for more
than 1-bit shift. The vacated LSBit locations is filled with zero and the
last bit shifted out of the MSBit is saved in CF.

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o SHR Instruction shifts the destination operand (register or storage

location in memory) to the right by number of bits specified by count.
The vacated MSBit locations is filled with zero and the last bit shifted
out of the LSBit is saved in CF.

o SAR Instruction shifts the destination operand (register or storage

location in memory) to the right by number of bits specified by count.
The vacated MSBit locations is filled with the original MSBit and the
last bit shifted out of the LSBit is saved in CF.

Note that shifting to the right is equivalent to division by the powers of 2.

A frequent need in programming is to isolate the value of one of the bits of a

byte or word of data by shifting it into the carry flag, shift instructions may
perform this operation. Once the bit is in CF it can be tested by other
instructions and based on this value initiate another software operation.

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5- Rotate Instructions

The rotate instructions are similar to the shift instructions; they perform many
of the same programming functions such as alignment of data and isolation of
a bit of data.

Mnemonic Meaning Format Operation Flags affected

Rotate the (D) left by the
number of bit positions equal
CF
to Count. Each bit shifted out
ROL Rotate left ROL D, Count
from the left most bit goes
(OF undefined
if count ≠ 1)
back into the right most bit
position
Rotate the (D) right by the
number of bit positions equal CF
ROR Rotate right ROR D, Count to Count. Each bit shifted out (OF undefined
from the right most bit goes if count ≠ 1)
into the left most bit position
CF
Rotate left
Same as ROL except carry is (OF undefined
RCL through RCL D, Count
attached to (D) for rotation if count ≠ 1)
carry
Rotate right CF
Same as ROR except carry is
RCR through RCR D, Count
attached to (D) for rotation
(OF undefined
carry if count ≠ 1)

o ROL Instruction rotates the destination operand (register or storage

location in memory) to the left by number of bits specified by count.
The bits moved out at MSBit are not lost; instead they are reloaded at
the other end.

o ROR Instruction rotates the destination operand (register or storage

location in memory) to the right by number of bits specified by count.
The bits moved out at LSBit are reloaded at the other end.

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o RCL Instruction rotates the destination operand (register or storage

location in memory) to the left through the carry flag by number of bits
specified by count. The bits moved out at MSBit are reloaded at the
other end.

o RCR Instruction rotates the destination operand (register or storage

location in memory) to the right by number of bits specified by count.
The bits moved out at MSBit are reloaded at the other end.

An example of a software operation that can be performed with the rotate

instructions is the disassembly of the two hexadecimal digits in a byte of data
so that they can be added.

Control Flow Instructions

The control flow instructions give the ability to alter the sequence in which
instructions of a program execute.

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1- Flag-Control Instructions

The instruction set includes a group of instructions that, when executed,

directly affect the state of the flags.

Mnemonic Meaning Operation Flags affected

LAHF Load AH from flags (AH) (Flags) None
SAHF Store AH into flags (Flags) (AH) SF, ZF, AF, PF, CF
CLC Clear carry flag (CF) 0 CF
STC Set carry flag (CF) 1 CF
CMC Complement carry flag (CF) (CF) CF
CLI Clear interrupt flag (IF) 0 IF
STI Set interrupt flag (IF) 1 IF

o LAHF Instruction loads the flags into AH to read them. The format of
the flags information in AH is as shown below (bits 1, 3, and 5) are not
used.

AH

SF ZF x AF x PF x CF
b7 b0

o SAHF Instruction stores AH into flags to change them, used to start an

operation with certain flags set or reset. The format in AH is same as
above.

o CLC, STC, CMC Instructions used to manipulate the carry flag, they
permit CF to be cleared, set, or complemented, respectively.

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o CLI, STI Instructions used to manipulate the interrupt flag. CLI

instruction clears the interrupt flag (IF = 0, disables the interrupt
interface). STI instruction sets the interrupt flag (IF = 1, microprocessor
is enabled to accept interrupts).

2- Compare Instruction

Mnemonic Meaning Format Operation Flags affected

(D) - (S) is used in setting CF, AF, OF,
CMP Compare CMP D, S or resetting the flags PF,SF, ZF

o CMP Instruction used to compare two 8-bit or 16-bit numbers. It gives

the ability to determine the relationship between two numbers; whether
they are equal or unequal, and when they are unequal, which one is
larger. The operands can reside in a storage location in memory, a
register, or be part of the instruction (immediate value). The process of
comparison is basically subtraction operation. The result of subtraction
is not saved, instead based on the result of subtraction; the appropriate
flags are set or reset. The new logic state of flags can be used by the
instructions that follow to make a decision whether or not to alter the
sequence in which the program executes.

3- Jump Instructions

In the 8086, the code segment register and instruction pointer keep track of
the next instruction to be fetched for execution. Thus to initiate a change in
control flow, a jump instruction must change the content of these registers. In
this way, execution continues at an address other than that of the next
sequential instruction. There are two types of jump operations; conditional
and unconditional jump.

a- Unconditional Jump

In an unconditional jump, no status requirements are imposed for the jump to

occur.

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Figure 1 Execution Sequencing of Program with Unconditional Jump

Instruction

Mnemonic Meaning Format Operation Flags affected

Jump is initiated
Unconditional to the address
JMP JMP Operand specified by the
None
jump
operand

There are two basic kinds of unconditional jumps:

1- Intrasegment jump limited to addresses within the current code segment

(just modifying IP). The operands can be Short-label, Near-label, Memptr
16, or Regptr 16.

 Short-label the jump-to address is specified by an 8-bit number

(immediate operand). JMP 12H
 Near-label the jump-to address is specified by an 16-bit number
(immediate operand). JMP 1234H
 Memptr 16 the jump-to address is specified indirectly by the content of
a memory location. JMP [BX]
 Regptr 16 the jump-to address is specified indirectly by the content of a
register. JMP BX

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2- Intersegment jump permits jumps from one code segment to another

(modifies both CS and IP). The operands can be Far-label, Memptr 32.

 Far-label uses a 32-bit immediate operand to specify the jump-to

address, the least significant 16 bits are loaded into IP and the most
significant 16 bits are loaded into CS. JMP 1234:5678H
 Memptr 32 four consecutive memory bytes starting at the specified
address contain the offset and new code segment addresses. The first
word of memory is loaded into IP; the second word of memory is
loaded into CS. JMP DWORD PTR [DI]

b- Conditional Jump

For a conditional jump, status conditions that exist at the time the jump
instruction is executed decide whether or not the jump will occur. If the
conditions are met, the jump takes place; otherwise, execution continues with
the next sequential instruction. The conditions that can be referenced by a
conditional jump instruction are status flags.

Table 1 shows the conditional jump instruction set. Each of these instructions
tests for the presence or absence of certain status conditions. For some of the
instructions, two different mnemonics can be used (this improves the program
readability).

Table 1 Conditional Jump Instructions

Mnemonic Meaning Condition

JA Above CF = 0 and ZF = 0
JAE Above or equal CF = 0
JB Below CF = 1
JBE Below or equal CF = 1 or ZF = 1
JC Carry CF = 1
JCXZ CX register is zero (CF or ZF) = 0
JE Equal ZF = 1
JG Greater ZF = 0 and SF= OF
JGE Greater or equal SF = OF
JL Less (SF xor OF) = 1
JLE Less or equal ((SF xor OF)or ZF) = 1

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JNA Not above CF = 1 or ZF = 1

JNAE Not above nor equal CF = 1
JNB Not below CF = 0
JNBE Not below nor equal CF = 0 and ZF = 0
JNC Not carry CF = 0
JNE Not equal ZF = 0
JNG Not greater ((SF xor OF)or ZF) = 1
JNGE Not greater nor equal (SF xor OF) = 1
JNL Not less SF = OF
JNLE Not less nor equal ZF = 0 and SF= OF
JNO Not overflow OF = 0
JNP Not parity PF = 0
JNS Not sign SF = 0
JNZ Not zero ZF = 0
JO Overflow OF = 1
JP Parity PF = 1
JPE Parity even PF = 1
JPO Parity odd PF = 0
JS Sign SF = 1
JZ Zero ZF = 1

Above and below are used to describe the comparison of unsigned numbers;
while less and greater to describe comparison of signed numbers. For
example, the number ABCDH is above the number 1234H if they are
considered to be unsigned numbers. On the other hand, ABCDH is less than
1234H if they are treated as signed numbers.

When signed numbers are compared, use the JG, JL, JGE, JLE, JE, and JNE
instructions. When unsigned numbers are compared, use the JA, JB, JAE,
JBE, JE, and JNE instructions.

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Figure 1 Execution Sequencing of Program with Conditional Jump Instruction

4- Subroutines Instructions

A subroutine is a special segment of program that can be called for execution

from any point in a program. The subroutine is written to provide a function
that must be performed at various points in the main program.

Main program Subroutine A

. First instruction
. .
. .
Call subroutine A .
Next instruction
. Return
.
.
Call subroutine A
Next instruction
.
.
.

Figure 1 Execution Sequencing of a Program That Includes Subroutine

Calling

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There are instructions provided to transfer control from the main program to a
subroutine and return control back to the main program.

Mnemonic Meaning Format Operation Flags affected

Execution continues
from the address of the
subroutine specified by
Subroutine the operand.
CALL call
CALL operand
Information required to
None
return back to the main
program such as IP and
CS are saved to stack.
Return to the main
program by restoring IP
RET
(and CS for far-proc). If
RET Return or
operand is present, it is
None
RET operand
added to the contents of
SP.
Push word ((SP)) (S)
PUSH onto stack
PUSH S
(SP) (SP)-2
None

Pop word (D) ((SP))

POP off stack
POP D
(SP) (SP)+2
None

Push flags ((SP) (Flags)

PUSHF onto stack
PUSHF
(SP) (SP)-2
None
OF, DF, IF, TF,
Pop flags (Flags) ((SP))
POPF off stack
POPF
(SP) (SP)+2
SF, ZF, AF, PF,
CF

o CALL Instruction provides the mechanism to call a subroutine into

operation by modifying either the value of IP or IP and CS to branch to
a subroutine. The operand initiates either an intrasegment or
intersegment call.

1- Intrasegment call causes the content of IP to be saved on the stack and a

new 16-bit value to be loaded into IP. The operands can be Near-proc,
Memptr 16, or Regptr 16.

 Near-proc the 16-bit immediate operand is loaded to IP. CALL 1234H

 Memptr 16 the content of a memory location (word) specified by the
operand is loaded into IP. CALL [BX]
 Regptr 16 the content of a register is loaded into IP. CALL BX

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2- Intersegment call permits the subroutine to reside in another code segment.

The contents of CS and IP are saved on the stack, and then new values are
loaded to them. The operands can be Far-proc, Memptr 32.

 Far-proc a 32-bit immediate operand is loaded into IP and CS.

CALL 1234:5678H

 Memptr 32 the pointer for the subroutine is stored as four consecutive

bytes in data memory. The first word of memory is loaded into IP; the
second word of memory is loaded into CS. CALL DWORD PTR [DI]

o RET Instruction returns control to the main program. It causes the

value of IP or both IP and CS that were saved on the stack to be
returned back to their corresponding registers. Program control is
returned to the instruction that immediately follows the call instruction.

o PUSH Instruction used to save parameters on the stack. These data

correspond to registers and memory locations that are used by the
subroutine. In this way, their original contents are kept intact in the
stack segment during the execution of the subroutine.

o POP Instruction used to retrieve parameters from the stack. Before a

return to the main program takes place, the parameters are restored.

The operands for push and pop instructions can be a general-purpose

register, a segment register (excluding CS), or a storage location in
memory.

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Since AX will be used as destination of multiplication operation in the

subroutine; its original content (from the main program) must be saved in
the stack. AL should be loaded with the content of BL (for multiplication).
The result is produced in AX so it should be moved to BX. Before
returning to the main program, the original content of AX is restored from
stack. Finally, a return instruction is used to pass control back to the main
program.

o PUSHF Instruction saves the content of flag register on the top of

stack.

o POPF Instruction returns the flags from the top of stack to the flag
register.

5- Loops Instructions

The 8086 microprocessor has instructions specifically designed for

implementing loop operations. These instructions can be used in place of
certain conditional jump instructions and give the programmer a simpler way
of writing loop sequences.

Mnemonic Meaning Format Operation

(CX) (CX) - 1
Jump is initiated to
location defined by
LOOP Loop LOOP short-label
short-label if (CX) ≠ 0;
otherwise, execute next
sequential instruction
(CX) (CX) - 1
Jump to location
Loop while
LOOPE/ defined by short-label
equal/ Loop LOOPE/ LOOPZ short-label
LOOPZ if (CX) ≠ 0 and ZF = 1;
while zero
otherwise, execute next
sequential instruction
(CX) (CX) - 1
Loop while Jump to location
LOOPNE/ not equal/ defined by short-label
LOOPNE/ LOOPNZ short-label
LOOPNZ Loop while if (CX) ≠ 0 and ZF = 0;
not zero otherwise, execute next
sequential instruction
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o LOOP Instruction works with respect to the content of CX register.

CX must be preloaded with a count that represents the number of times
the loop is to repeat. Whenever LOOP is executed, the content of CX is
first decremented by 1 and then checked to determine if they are equal
to zero. If equal to zero, the loop is complete and the instruction
following LOOP is executed; otherwise, control is returned to the
instruction at the label specified. (LOOP is a single instruction that
functions the same as DEC CX instruction followed by JNZ
instruction).

o LOOPE/ LOOPZ Instructions check the contents of both CX and ZF.

Each time the loop instruction is executed, CX decrements by 1 without
affecting the flags. ZF that results from execution of the previous
instruction is tested. If CX is not 0 and ZF is 1, a jump is initiated to the
location specified with the short-label operand and the loop continues.
If either CX or ZF is 0, the loop is complete and the instruction
following the loop instruction is executed.

o LOOPNE/ LOOPNZ Instructions work similarly as above, the

difference is that it checks that ZF is 0 and CX is not 0. If these
conditions are met, the loop continues; otherwise it ends.

6- Strings Instructions

A string is a series of data words (or bytes) that reside in consecutive memory
locations. The string instructions of 8086 permit programmer to implement
operations such as to move data from one block of memory to a block
elsewhere in memory, scanning a string of data elements stored in memory to
look for a specific value, comparing the elements of two strings in order to
determine whether they are the same or different, and initializing a group of
consecutive memory locations. These operations must be repeated to handle a
string of more than one element.

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Mnemonic Meaning Format Operation Flags affected

((ES)0+(DI)) ((DS)0+(SI))
Move MOVSB/
MOVS string MOVSW
(SI) (SI) ± 1 or 2 None
(DI) (DI) ± 1 or 2
Set flags as per
Compare CMPSB/ ((DS)0+(SI)) - ((ES)0+(DI)) CF, PF, AF, ZF,
CMPS string CMPSW (SI) (SI) ± 1 or 2 SF, OF
(DI) (DI) ± 1 or 2
Set flags as per
Scan SCASB/ CF, PF, AF, ZF,
SCAS string SCASW
(AL or AX) - ((ES)0+(DI))
SF, OF
(DI) (DI) ± 1 or 2
Load LODSB/ (AL or AX) ((DS)0+(SI))
LODS string LODSW (SI) (SI) ± 1 or 2
None

Store STOSB/ ((ES)0+(DI)) (AL or AX)

STOS string STOSW (DI) (DI) ± 1 or 2
None

CLD Clear DF CLD (DF) 0 DF

STD Set DF STD (DF) 1 DF

o MOVSB/ MOVSW Instructions an element of the string specified by

SI register with respect to DS is moved to the location specified by DI
register with respect to ES. The move can be performed on a byte or a
word of data. After the move is complete, the content of both SI and DI
are automatically incremented or decremented by 1 for a byte move and
by two for a word move. The address pointers in SI and DI increment
or decrement depending on how the direction flag (DF) is set.

o CMPSB/ CMPSW Instructions subtracts the destination string operand

from the source string operand and adjusts the flags accordingly. The
result of subtraction is not saved. When these instructions are executed
the operands are compared, the flags are adjusted, and both SI and DI
are updated so that they point to the next elements in their respective
strings.
o SCASB/ SCASW Instructions compares the byte or word element of
the destination string at the physical address derived from DI and ES to
the content of AL or AX, respectively. The flags are adjusted based on
this result and DI is incremented or decremented.

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o LODSB/ LODSW Instructions LODSB loads a byte from a string in

memory into AL. The address in SI is used relative to DS to determine
the address of the memory location of the string element; SI is
incremented or decremented by 1 after loading. LODSW indicates that
the word-string element at physical address derived from DS and SI is
to be loaded into AX. Then the index in SI is automatically
incremented or decremented by 2.

o STOSB/ STOSW Instructions stores a byte from AL or a word from

AX into a string location in memory. ES and DI are used to form the
address of storage location in memory.

o CLD Instruction clears DF, this selects auto-increment mode in string

operations so that each time a string operation is performed, SI and/ or
DI are incremented by 1 if byte data are processed and by 2 if word
data are processed.

o STD Instruction sets DF, this selects auto-decrement mode in string

operations so that each time a string operation is performed, SI and/ or
DI are decremented by 1 if byte data are processed and by 2 if word
data are processed.

String Prefixes

In most applications, the basic string operations must be repeated in order to

process arrays of data. Inserting a repeat prefix before the instruction that is to
be repeated does this.

 REP Prefix causes the basic string operation to be repeated until the
contents of CX become = 0. Each time the instruction is executed, it
causes CX to be tested for 0. If CX is found ≠ 0, it is decremented by 1
and the basic string operation is repeated. On the other hand, if it is 0,

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the repeat string operation is done and the next instruction in the
program is executed. The repeat count must be loaded into CX prior to
executing the repeat string instruction. The REP prefix is used with the
MOVS and STOS instructions.

 REPE/ REPZ Prefixes the basic compare or scan operation repeats as

long as both the count in CX ≠ 0 and ZF = 1. The first condition, CX ≠
0, indicates that the end of the string has not yet been reached and the
second condition, ZF = 1, indicates that the elements that were
compared are equal. The REPE and REPZ prefixes are used with the
CMPS and SCAS instructions.

 REPNE/ REPNZ Prefixes works similarly as the REPE/REPZ, except

that now the operation is reached as long as CX ≠ 0 and ZF = 0. That is,
the comparison or scanning is performed as long as the string elements
are unequal and the end of the string is not yet reached. The REPNE
and REPNZ prefixes are used with the CMPS and SCAS instructions.

The 8085 Description

The 8085 has simple architecture and it is easy to use. It operates with a
power supply of +5 volts and GND. It uses approximately 6500 transistors. It
has 8-bit data and uses 16-bit address to access the memory. With the help of
16-bit address, 8085 can access 216 = 65536 = 64K memory locations. The 8-
bit data bus is multiplexed with the lower part of the 16-bit address bus to
limit the number of pins to 40.

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Figure 1 8085 Pin Diagram

The pins can be grouped into 6 categories:

1- Address Bus (16 pins) The 8085 has 16 signal lines that are used as the
address bus, so address ranges from 0000H to FFFFH. These lines are split
into 2 groups, AD0 – AD7 and A8 – A15. The 8 signal lines, A8 – A15, are
unidirectional and used for the most significant address bits. The signal lines
AD0 – AD7 are used for a dual purpose; as a lower-order address lines and
also as a data bus. The demultiplexing of AD0 – AD7 is determined by ALE
(Address Latch Enable) signal. When this control signal goes high, the
content of the address bus is address bits. When ALE is low, data is placed on
the bus.

Question Calculate the address lines required for an 8 Kbytes memory chip.

2- Data Bus (8 pins) The signal lines AD0 – AD7 are bidirectional. They are
used as the low-order address bus as well as the data bus. The data flows both
ways between the microprocessor and memory or I/O. The 8 data lines enable
the 8085 to manipulate 8 bits data only at a time, ranging from 00H to FFH.

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3- Control & Status Bus (6 pins) This group of signals is used to identify the
nature of operation. It is responsible for overall control and synchronization of
the system. This group of signals includes: two control signals (RD and WR),
three status signals (IO/M, S0 and S1) and one special signal (ALE).

4- Power Supply & Frequency (5 pins) These signals are: Vcc (+5 V power
supply), Vss (Ground Reference), X1, X2 (A crystal or RC, LC network) is
connected at these pins, and CLK OUT (Clock Output). This signal can be
used as the system clock for other devices.

5- Externally Initiated & Acknowledgement Signals (11 pins) The 8085 has
5 interrupt signal that can be used to interrupt a program execution. (INTR,
RST7.5, RST 6.5, RST 5.5, TRAP). Restart interrupts (RST5.5, RST 6.5,
RST 7.5) are vectored interrupts that transfer the program control to specific
memory locations. They have higher priorities than the INTR interrupt.
Among these three, the priority order is 7.5, 6.5, 5.5. TRAP is a nonmaskable
interrupt and has the highest priority. INTA is used to acknowledge an
interrupt. HOLD indicates that a peripheral is requesting the use of the
address and data buses. HLDA acknowledges the HOLD request. READY is
used to delay the 8085 Read or Write cycles until a slow responding
peripheral is ready to send or accept data. RESET IN when the signal on this
pin goes low, the 8085 is reset. RESET OUT signal indicates that the 8085 is
being reset. it can be used to reset other devices.

6- Serial I/O ports (2 pins) The 8085 has two signals to implement the serial
transmission: SID (Serial Input Data) and SOD (Serial Output Data). In serial
transmission, data bits are sent over a single line, one bit at a time.

Internal Diagram of 8085

8085 microprocessor consists of six main components:

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Figure 2 Architecture of 8085 Microprocessor

 Arithmetic and Logic Unit ALU performs many of the functions that
involve arithmetic and logic operations. It also handles all data
manipulation, such as shift, rotate, and the 2’s complement operations.

 Timing and Control Unit is responsible for timing of all components

within and outside the microprocessor, Clock input, Input and Output
traffic flow on all busses.

 Instruction Register and Decoder when an instruction is fetched from

memory, it is loaded in the instruction register. The decoder decodes
the instruction and establishes the sequence of events to follow. The
instruction register is not programmable and cannot be accessed
through any instructions.

 Register Array data registers are locations where data is stored

temporary within the microprocessor.

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 Interrupt Control is used to handle the interrupts. Interrupt controller

receives interrupts according to their priority and applies them to the
microprocessor.

 Serial I/O Control is used to convert serial data into parallel and
parallel data into serial. Microprocessor works with 8-bit parallel data
and serial I/O devices works with serial transfer of data; therefore, this
unit is the interface between microprocessor and serial I/O devices.

Programming Model

The 8085 programming model includes six registers, one accumulator, one
flag register, and two 16-bit registers (stack pointer and program counter).

Figure 3 8085 Programming Model

The 8085 uses six General-Purpose Registers to store 8-bit data; these are
identified as B, C, D, E, H, and L. They can be combined as register pairs
(BC, DE, and HL) to perform some 16-bit operations. The programmer can
use these registers to store or copy data into the registers by using data copy
instructions.

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The Accumulator is an 8-bit register that is a part of arithmetic logic unit

(ALU). It is used to store 8-bit data and to perform arithmetic and logical
operations. The result of an operation is stored in the accumulator.

The ALU includes five Flags, which are set or reset after an operation
according to data conditions of the result in the accumulator and other
registers. These are Zero flag (Z), Carry (CY), Sign (S), Parity (P), and
Auxiliary Carry (AC) flags. The microprocessor uses these flags to test data
conditions so they have critical importance in the decision-making process of
the microprocessor. Five bit positions out of eight are used to store the five
flags.

S Z X AC X P X CY
B7 B6 B5 B4 B3 B2 B1 B0

The Program Counter (PC) is a 16-bit register deals with sequencing the
execution of instructions. This register is a memory pointer. Memory
locations have 16-bit addresses, and that is why this is a 16-bit register. To
execute a program, the starting address of the program is loaded in program
counter. The PC sends out an address to fetch a byte of instruction from
memory and increment its content automatically. Hence, when a byte of
instruction is fetched, the PC holds the address of the next byte of the
instruction or next instruction.

The Stack Pointer (SP) is also a 16-bit register used as a memory pointer. It
points to a memory location in the stack. The beginning of the stack is defined
by loading 16-bit address in the stack pointer.

Instruction Format

Each instruction has two parts; the operation code (op-code) and the operand.
The operand (or data) can be specified in various ways. It may include 8-bit
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(or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit)
address. In some instructions, the operand is implicit.

Addressing Modes

Every instruction of a program has to operate on a data. The method of

specifying the data to be operated by the instruction is called Addressing
mode. The 8085 has 5 different types of addressing:

1- Immediate addressing mode.

2- Register addressing mode.

3- Direct addressing mode.

4- Indirect addressing mode.

5- Implied addressing mode.

Instruction Set

The 8085 instruction set can be classified into the following five functional
headings:

 Data Transfer Instructions includes the instructions that move (copy)

data between registers or between memory locations and registers. In
all data transfer operations the content of source register is not altered.
For example: MOV A, B LDA 4600H LHLD 4200H

 Arithmetic Instructions includes the instructions which perform the

addition, subtraction, increment or decrement operations. The flag
conditions are altered after execution of an instruction in this group.
For example: ADD B SUB C INR D INX H
 Logical Instructions performs the logical operations like AND, OR,
Exclusive-OR, complement, compare and rotate instructions. The flag

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conditions are altered after execution of an instruction in this group.

For example: ORA B XRA A RAR

 Branching Instructions used to alter the sequence of program

execution either conditionally or unconditionally. For example:
JZ 4200H RST 7 CALL 4300H

 Machine Control Instructions Includes the instructions related to

interrupts and the instruction used to halt program execution. For
example: SIM RIM HLT

Interrupts

Interrupt is a signal sent by an external device to the processor (or special

instruction executed in a program) to stop the execution of the current process
in the microprocessor and perform a particular task to the called device. The
8085 has 5 hardware interrupts (TRAP, RST7.5, RST6.5, RST5.5, INTR) and
8 software interrupts (RST0, RST1, RST2 …… RST7).

8086 Pin Diagram

The 8086, announced in 1978, was the first 16-bit microprocessor introduced
by Intel Corporation. The 8086 is manufactured using high-performance
metal-oxide semiconductor (HMOS) technology, and the circuitry on its chips
is equivalent to approximately 29000 transistors. It is housed in a 40-pin dual
in-line package.

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Figure 1 8086 Pin Diagram

As seen above, many of 8086’s pins have multiple functions. For example, we
see that address bus lines A0 through A15 and data bus lines D0 through D15
are multiplexed. For this reason, these leads are labeled AD0 through AD15.
By multiplexed we mean that the same physical pin carries an address bit at
one time and the data bit at another time.

8086 Modes of Operation

The 8086 can be configured to work in either of two modes:

a- Minimum Mode is selected by applying logic 1 to the MN/MX input lead.
Minimum mode 8086 systems are typically smaller and contain a single
microprocessor.
b- Maximum Mode is selected by applying logic 0 to the MN/MX input lead.
Maximum mode configures 8086 systems for use in larger systems and with
multiple processors.
Depending on the mode of operation selected, the assignments for a number
of pins on the microprocessor package are changed. As shown above, the pin

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function of the 8086 specified in parentheses relate to a maximum-mode

system.

Table 1 8086 Common Signals Minimum Mode

Common Signals
Name Function Type
Address /data bus Bidirectional
AD15-AD0
Address / status Output
A19/S6-A16/S3
Minimum/Maximum mode control Input
MN/MX
Read control Output
RD
Wait on test control Input
TEST
Wait state control Input
READY
System reset Input
RESET
Non-maskable interrupt request Input
NMI
Interrupt request Input
INTR
System clock Input
CLK
+5 volt Input
VCC
Ground Input
GND

Minimum Mode Interface Signals

The minimum-mode signals can be divided into the following basic groups:

Table 2 Minimum Mode Signals

Minimum Mode Signals (MN/𝐌𝐗=VCC)

Name Function Type
Hold request Input
HOLD
Hold acknowledgment Output

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HLDA
Write control Output
WR
IO/memory control Output
M/IO
Data transmit /receive Output
DT/R
Data enable Output
DEN
Bank high enable/Status line 7 Output
BHE /S7
Address latch enable Output
ALE
Interrupt acknowledgment Output
INTA

1- Address/Data Bus the address bus is 20 bits long and consists of signal
lines A0 (the LSb) to A19 (the MSb).
The data bus is 16 bits long and consists of signals lines D 0 (the LSb) to D15
(the MSb). When acting as a data bus, they carry read/write data for memory,
input/output data for I/O devices, and interrupt-type codes from an interrupt
controller.
2- Status Signals the four most significant address lines, A16 through A19 are
also multiplexed, but with status signals S3 through S6. These status bits are
output on the bus at the same time that data are transferred over the other bus
lines. Bits S3 and S4 together form a 2-bit binary code that identifies which of
the internal segment registers was used to generate the physical address that
was output on the address bus during the current bus cycle. Status line S5
reflects the status of logic level of the internal interrupt enable flag.

Table 3 S3 and S4 Signals Binary Code

S4 S3 Address Status
Alternate(relative to the ES)
0 0
Stack (relative to the SS)
0 1
Code/None (relative to the CS or a default
1 0
of zero)
Data (relative to the DS)
1 1

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3- Control Signals these are provided to support the memory and I/O
interfaces of the 8086:

o ALE Signal is a pulse to logic 1 that signals external circuitry when a

valid address is on the bus. This address can be latched in external
circuitry on the 1-to-0 edge pulse at ALE.
o M/𝑰𝑶 Signal tells external circuitry whether a memory or I/O transfer
is taking place over the bus. (Logic 1 for memory operation, logic 0 for
I/O operation).
o DT/𝑹 Signal when this line is logic 1 the bus is in Transmit Mode (data
are either written into memory or output to an I/O device). When this
line is logic 0 the bus is in Receive Mode (data are either read from
memory or input from an I/O device).
o 𝑩𝑯𝑬 Signal logic 0 on this line is used as a memory enable signal for
the most significant byte half of the data bus, D8 through D15.
o 𝑹𝑫 Signal indicates that a read bus cycle is in progress.
o 𝑾𝑹 Signal indicates that a write bus cycle is in progress.
o 𝑫𝑬𝑵 Signal during read operations, this signal is also supplied to
enable external devices to supply data to the microprocessor.
o READY Signal used to insert wait states into the bus cycle so that it is
extended by a number of clock periods.

4- Interrupt Signals (INTR, INTA, TEST, RESET, NMI)

5- Direct Memory Access (DMA) Interface Signals (HOLD, HLDA)

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Figure 2 Minimum-Mode Block Diagram

Maximum Mode Interface Signals

When the 8086 microprocessor is set for the maximum-mode configuration, it

produces signals for implementing a multiprocessor/coprocessor system
environment. By multiprocessor system environment we mean that multiple
microprocessors exist in the system and that each processor executes its own
program.
During the maximum mode operation, theWR, M/IO, DT/R, DEN, ALE, and
INTA signals are no longer produced by the 8086. Instead, it outputs a status
code on three signals lines, S0, S1, and S2, prior to the initiation of each bus
cycle.

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Figure 3 Maximum-Mode Block Diagram

Table 4 Maximum Mode Signals

Maximum Mode Signals (MN/𝐌𝐗=Ground)

Name Function Type
Request/grant bus access control Bidirectional
RQ/GT1,0
Bus priority lock control Output
LOCK
Bus cycle status Output
S2 − S0
Instruction queue status Output
QS1, QS0

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o 𝑺𝟎, 𝑺𝟏, 𝑺𝟐 these three bits are input to the external bus controller
device, the 8288, which decodes them to identify the type of next bus
cycle. In addition to the signal produced the 8288 bus controller
produces DEN, DT/R, and ALE.
o 𝑳𝑶𝑪𝑲 Signal this signal is meant to be output (logic 0) whenever the
processor wants to lock out the other processors from using the bus.
o Queue Status Signals (QS0, QS1) these two bits tell the external
circuitry what type of information was removed from the queue.
o 𝑹𝑸/𝑮𝑻𝟎, 𝑹𝑸/𝑮𝑻𝟏 these two signals provide a prioritized bus access
mechanism for accessing the local bus.

Table 5 Bus Status Codes

Status Inputs
CPU Cycle 8288 Command Meaning
𝑺𝟐 𝑺𝟏 𝑺𝟎
Interrupt
0 0 0 Acknowledge INTA Interrupt acknowledge

0 0 1 Read I/O port IORC I/O read control

I/O write control,

0 1 0 Write I/O port IOWC, AIOWC
Advanced I/O write control
0 1 1 None ---
Halt
1 0 0 MRDC Memory read control
Instruction Fetch
1 0 1 MRDC Memory read control
Read Memory
Memory write control,
1 1 0 Write Memory MWTC, AMWC Advanced memory write
control
1 1 1 None ---
Passive

System Clock

The time base for synchronization of the internal and external operations of
the microprocessor in a microcomputer system is provided by the clock
(CLK) input signal. The 8086 microprocessor is manufactured in three
speeds: the 5-MHz 8086, the 8-MHz 8086-2 and the 10-MHz 8086-1.

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Bus Cycle and Time State

A bus cycle defines the basic operation that a microprocessor performs to

communicate with external devices such as Memory read, Memory write, I/O
read, and I/O write.

The bus cycle of 8086 microprocessors consists of at least four clock periods
(T1, T2, T3, and T4):

 During T1 the 8086 puts an address on the bus.

 During T2 the 8086puts the data on the bus (for write memory cycle)
and maintained through T3 and T4.
 During T2 the 8086puts the bus in high-Z state (for read cycle) and then
the data to read must be available on the bus during T3and T4.

These four clock states give a bus cycle duration of 125 ns × 4= 500 ns in an
8-MHz system.

Idle States

If no bus cycles are required, the microprocessor performs what is known as

idle state. During these states, no bus activity takes place. Each idle state is
one clock period long, and any number of them can be inserted between bus
cycles. Idle states are performed if the instruction queue inside the
microprocessor is full and it does not need to read or write operands form
memory.

Wait States

Wait states can be inserted into a bus cycle. This is done in response to
request by an event in external hardware instead of an internal event such as a
full queue. The READY input of the 8086is provided specifically for this
purpose. As long as READY is held at the 0 level, wait states are inserted
between states T3and T4 of the current bus cycle, and the data that were on the
bus during T3 are maintained. The bus cycle is not completed until the
external hardware returns READY back to the 1 logic level.

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Read Cycle

The read bus cycle begins with state T1. During this period, the 8086 output
the 20-bit address of the memory location to be accessed on its multiplexed
address/data bus AD0 through AD15 and multiplexed lines A16/S3 through
A19/S6.note that at the same time a pulse is also produced at ALE. The signal
BHE is also supplied with the address lines.

Figure 4 Minimum-Mode Memory Read Bus Cycle of the 8086

Memory Interface Circuits

The memory interface circuit of an 8086-based (maximum mode)
microcomputer system is shown below.

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Figure 1 Memory Interface Block Diagram (for Maximum Mode)

Here we find that the interface includes:

o 8288 bus controller

o Address bus latches
o Address decoders
o Bank write and read control logic
o Data bus transceiver/buffer

The status signals𝑆0 , 𝑆1 , and 𝑆2 are outputs of the 8086 and inputs to the 8288
bus controller which decodes them to produce command and control signals
needed to coordinate data transfer over the bus.

The address bus is latched, buffered, and decoded. The address lines A 0
through A19 are latched along with control signal 𝐵𝐻𝐸 in the address bus
latch. The latched address lines A17L through A19L are decoded to produce
chip enable output 𝐶𝐸 0 through𝐶𝐸 7.

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The 8288 bus controller produces the address latch enable ALE control signal
from 𝑆2𝑆1𝑆0. It is applied to the CLK input of latches.

During read operations, the bank read control logic determines whether the
data are read from one of the two memory banks or from both (depending on
whether a byte or word data transfer). Similarly, the bank write control logic
determines to which memory bank the data are written.

The bus transceivers control the direction of data transfer between the
microprocessor and memory subsystem. DEN is applied to the EN input of the
transceivers to enable them for operation. DT/𝑅 is applied to the DIR input of
the bus transceivers to select the direction of data transfer (logic 0 makes data
pass from memory to microprocessor, logic 1 makes data be carried from the
microprocessor to the memory).

For the minimum mode, the memory interface is similar to above except that
the signals ALE,𝐷𝐸𝑁, and DT/𝑅 are delivered by 8086 directly. 𝑀𝑊𝑇𝐶 and
𝑀𝑅𝐷𝐶 are produced using 𝑅𝐷, 𝑊𝑅, and M/𝐼𝑂 signals as shown below.

Figure 2 Memory Interface Block Diagram (for Minimum Mode)

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Memory Types
Every microprocessor-based system has a memory system. Memory provides
the ability to store and retrieve digital information. The memory unit of the
microcomputer is partitioned into a primary storage section and secondary
storage section.

Primary Storage Memory Secondary Storage Memory

Used for working information, such Used for storage of data,
as the instruction of the program information, and programs that are
currently being run and data that it not in use
is processing
This part normally requires high This part of the memory unit can be
speed operation but does not slow speed, but it requires very
normally require very large storage large storage capacity
capacity
It is implemented with It is normally implemented with
semiconductor memory devices, magnetic storage device, such as
such as ROM , RAM and FLASH the floppy disk and hard disk drive

Almost all systems contain two main types of memory: Read-Only Memory
ROM and Random Access Memory RAM. ROM contains system software
and permanent system data, while RAM contains temporary data and
application software.

o Read Only Memory is one type of semiconductor memory device. It is

most widely used in microcomputer systems for storage of the program
that determines overall system operation. The information stored within
a ROM integrated circuit is permanent (nonvolatile). Three types of
ROM devices are in wide use today:
1. The mask programmable read only memory (ROM)
2. The one time programmable read only memory (PROM)
3. The erasable programmable read only memory (EPROM)

o Random Access Memory RAM is similar to ROM in that its storage

location can be accessed in a random order, but it is different from
ROM in two important ways:

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1. Data stored in RAM is not permanent

2. RAM is volatile

Two types of RAMs are in wide use today:

 Static RAM (SRAM) data remain valid as long as the power supply is
not turned off.
 Dynamic RAM (DRAM) to retain data in a DRAM, it is not sufficient
just to maintain the power supply; we must periodically restore the data
in each storage location (Refreshing the DRAM).

Memory Expansion

In many applications, the microcomputer system requirement for memory is

greater than what is available in a single device. There are two basic reasons
for expanding memory capacity:

1. The byte-wide length is not large enough

2. The total storage capacity is not enough bytes.

Both of these expansion needs can be satisfied by interconnecting a number of

ICs.

Figure 1 Implementation of 32K× 16 EPROM Using Two 32K×8 EPROM

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Figure 2 Implementation of 64K× 8 EPROM Using Two 32K×8 EPROM

Ex. Design an 8086 memory system consisting of 1MB, using 64K×8

memory.

Sol.

The 8086 has 20 address bits (A0-A19) and 16 data bits (D0-D15)

1MB = 1KB×1KB = 210× 210 = 220

64KB×8 means 64K locations (bytes), each byte is 8 bits

64KB = 216 16 address bits

To get 1MB out of 64KB units

1𝑀𝐵 210 𝐾𝐵
= 6 = 16
64𝐾𝐵 2 𝐾𝐵
16 units are needed (8 for low bank and same for high bank)

Two decoders are used, one for each bank

The three MSbits (A17, A18, and A19) are input to decoders

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Input/Output Types
The input/output (I/O) system of the microprocessor allows peripherals to
provide data or receive results of processing the data; this is done using I/O
ports. Through the I/O interface, the MPU can input or output data in bit, byte,
or word.

The 8086 microcomputers can employ two different types of (I/O); Isolated
I/O and Memory-mapped I/O. These I/O methods differ in how I/O ports are
mapped into the 8086’s address spaces.

o Isolated Input/Output the I/O devices are treated separate from

memory. The address space from a software point of view for the I/O
ports is organized as bytes of data in the range 0000H through FFFFH.
The part of the I/O address space from address 0000H through 00FFH
is referred to as Page 0 as shown in Figure 1.

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Figure 1 Isolated I/O Ports

o Memory-Mapped Input/Output the I/O devices are placed in the

memory address space of the microcomputer. The MPU looks at the
I/O port as though it is a storage location in memory. For example, in
Figure 2 the 4096 memory addresses in the range form E0000H
through E0FFFH are assigned to I/O devices.

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Figure 2 Memory-Mapped I/O Ports

Isolated I/O Memory-mapped I/O

Use only the special input/output All memory instructions and
instructions (IN and OUT) addressing modes are available to
perform I/O operation (MOV,
AND, XCHG, SUB…)
Faster because I/O instructions is Slower because memory
specifically designed to run faster instructions execute slower than
than memory instructions the special I/O instructions

The memory address space is not Part of the memory address space is
affected lost
All data transfers must take place Data transfers can take place
between AL or AX register and the between an I/O port and an internal
I/O port register other than just AL or AX

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Minimum-Mode Isolated Input/Output Interface

The minimum mode isolated I/O interface is shown in Figure 3. Unlike the
memory interface, just the 16 least significant lines of the address bus (A 0
through A15) are used. This interface uses the signals ALE, BHE, M/IO, RD,
WR, DT/R, and DEN.

Figure 3 Minimum- Mode Isolated I/O Interface

Maximum-Mode Isolated Input/Output Interface

Figure 4 shows the maximum mode isolated I/O interface. This interface uses
the 8288 bus controller. Here the bus controller decodes the status bits S0, S1,
S2 to produce bus cycle commands (IORC, IOWC, and AIOWC) and the
signals ALE, DT/R, and DEN. The command signals are used to enable I/O
ports to deliver/receive data to/from the system bus during write and read
operations.

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Figure 4 Maximum- Mode Isolated I/O Interface

Input/Output Instructions

Isolated Input/output operations are performed using special input and output
instructions (IN and OUT). All data transfers take place between an I/O
device and the accumulator (byte transfers involve AL, and word transfers
involve AX).

Mnemonic Meaning Format Operation

Input direct IN Acc, Port (Acc) (Port)
IN
Input indirect (variable) IN Acc, DX (Acc) ((DX))
Output direct OUT Port, Acc (Port) (Acc)
OUT
Ouput indirect (variable) OUT DX, Acc ((DX)) (Acc)

There are two different forms of IN and OUT instructions; the Direct I/O
instructions and Variable I/O instructions.

 Direct I/O instructions The address of the I/O port is specified as part
of the instruction. Eight bits are provided for this direct address. For
this reason, its value is limited to the address range from 00H to FFH
(Page 0).

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 Variable I/O instructions use a 16-bit address that resides in the DX

register within the MPU (the value in DX is not an offset). Since the
address is 16 bits in length, variable I/O instructions can access ports
located anywhere in the 64 KB I/O address space.

Input/Output Bus cycles

The input/output bus cycles are essentially the same as those involved in the
memory interface. Figure 5 shows the output bus cycle of the 8086. It’s
similar to the write cycle except for the signal M/IO.

Figure 5 Output Bus Cycle of the 8086

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Byte-Wide Output Ports using Isolated I/O

Here we explain the circuits that can be used to implement parallel output
ports (8 bit) in microcomputer system employing isolated I/O.

Time Delay Loop and Blinking an LED at an Output Port

Figure 6 shows how to attach an LED to output port O7 of parallel port 0. The
port address is 8000H, and the LED corresponds to bit7 of the byte of data
that is written to port 0. The circuit uses 74LS374 edge clocked octal latch to
provide the output ports.

For the LED to turn on, O7 must be switched to logic 0, and it will remain on
until this output is switched back to 1. To make O7 logic 0, simply write 0 to
that bit of the octal latch.

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Figure 6 Driving an LED Connected to an Output Port.

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Ex. Write instruction sequence to make the LED in Figure 6 blinks.

Sol.

The program must first makes O7 logic 0 to turn on the LED, delays for a
short period of time, and then switches O7 back to 1 to turn off the LED. This
piece of program can run as a loop to make the LED continuously blink.

MOV DX, 8000H

MOV AL, 00H
** : OUT DX, AL
MOV CX, FFFFH
* : LOOP *
XOR AL, 80H
JMP **

Ex. What is the I/O address of port 7 on the circuit in Figure 6? Assume all
unused address bits are at logic 0.

Sol.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0

The address is 800EH

Byte-Wide Input Ports using Isolated I/O

Here we explain the circuits that can be used to implement parallel input ports
(8 bit) in microcomputer system employing isolated I/O.

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Polling the Setting of a Switch

Figure 7 shows how to attach a switch to input line I2 of parallel port 0. The
port address is 8000H, and the switch corresponds to bit2 of the byte of data
that is read from port 0. The circuit uses 74LS244 unidirectional octal buffer
to implement the input ports.

Ex. Write a program to poll a switch at I2 waiting for it to close.

Sol.

MOV CL, 03H

MOV DX, 8000H
* : IN AL, DX
SHR AL, CL
JC *
.
.
If the switch is open, then bit 2 in AL is 1 and this value is shifted into CF.
The program will keep looping until the switch is closed. If the switch is
closed, then the polling operation is complete and the instruction following
the JC is executed.

Ex. Write a sequence of instructions to read in the contents of ports 1 and 2 in

the circuit shown in figure 7, and save them at consecutive memory addresses
A0000H and A0001H in memory.

Sol.

MOV AX, A000H

MOV DS, AX
MOV DX, 8002H
IN AL, DX
MOV [0000H], AL
MOV DX, 8004H
IN AL, DX
MOV [0001H], AL

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Figure 7 Reading the Setting of Switch Connected to an Input Port.

82C55A Programmable Peripheral Interface

The 82C55A interfaces peripheral I/O devices to the microcomputer system.

It is programmable by the system software. It reduces the external logic
normally needed to interface peripheral devices and supports a variety of byte
oriented I/O interfaces (printers, keyboards, displays, floppy disk controllers,
D-to-A and A-to-D converters, etc.). It is manufactured using CMOS
technology, and the circuitry on its chips is equivalent to approximately 5200
transistors.

The standard configuration of the 82C55A makes it compatible with the 8086,
8088 and other microprocessors.

Figure 1 82C55A Pin Diagram

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82C55A consists of 3 8-bit I/O ports (A, B, and C).They are grouped as group
A (Port A with the 4 upper bits of port C) and group B (Port B with the 4
lower bits of port C).

8-bit 8-bit
D7-D0 82C55 Port A
RD
8-bit
WR Port B

RESET 8-bit
Port C
A1
Control Reg.
A0

CS

Figure 2 82C55 Ports and Signals

D0-D7 are bidirectional three-state data bus lines. RD is an active low control
signal used by the CPU to read status information or data via the data bus.
WR is an active low control signal used by the CPU to load control words and
data into the 82C55A.

The RESET signal (active high) clears the control register and all ports (A, B,
and C) are set to the input mode. Chip select (CS) is an active low input used
to enable the 82C55A for communications.

A0 and A1 signals control the selection of one of the three ports or the control
word register.

A1A0 82C55A Register

00 A
01 B
10 C
11 Control register

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The bits of control register and their control functions are shown below.

Figure 3 Control Word of the 82C55 PPI

Ex. Write down 82C55A control word that sets port A, port B and port C
lower as input, port C upper as output; all in mode 0.

Sol.

Mode set flag is active D7 = 1

Group A is in mode 0 D6 D5 = 00
A is an input D4 =1
C upper is an output D3 =0
Group B is in mode 0 D2 =0
B is an input D1 =1
C lower is an input D0 =1

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Control word = 93H D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 0 0 1 1

Ex. 2 In 8086's 8-bit isolated I/O system, an 82C55A PPI is connected so that
the address of A, B, C ports, and Control register are 4D08H, 4D09H,4D0AH
and 4D0BH respectively.

a) Draw the circuit diagram.

b) Write program to set ports A, B as input, C as output (all in mode 0)
then continuously receive two unsigned number from Registers A and
B, compare them and output the larger to Register C.

Sol.

a)

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b)
D7 D6 D5 D4 D3 D2 D1 D0
Control word = 92H
1 0 0 1 0 0 1 0

MOV AL, 92H

MOV DX, 4D0BH
OUT DX, AL
***: MOV DL, 08H
IN AL, DX
MOV BL, AL
INC DL
IN AL, DX
CMP AL, BL
JNC *
MOV AL, BL
* : INC DL
OUT DX, AL
MOV CX, 0FFFFH
** : LOOP **
JMP ***

Seven-Segment Display Interface

A seven-segment display is a form of electronic display device for displaying

decimal numerals. It is widely used in digital clocks, electronic meters, and
other electronic devices for displaying numerical information.

Figure 4 Seven-Segment Display

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There are two types of LED seven-segment displays: common cathode (CC)
and common anode (CA). The difference between the two displays is that
common cathode has all the cathodes of the seven-segments connected
directly together and that the common anode has all the anodes of the seven-
segments connected together.

When working with a CA seven segment display, power must be applied

externally to the anode connection that is common to all the segments. Then
by applying a ground to a particular segment connection (a-g), the appropriate
segment will light up.

A common cathode seven-segment is different from a common anode

segment in that the cathodes of all the LEDs are connected together. For the
use of this seven-segment the common cathode connection must be grounded
and power must be applied to appropriate segment in order to illuminate that
segment.

For example to display number (9) on CC seven-segment display, the bits

must be set as follow

a b c d e f g
1 1 1 1 0 1 1 x

If the byte F6H (or F7H because bit D0 is neglected) is written to address of
the seven-segment display then it will display number nine.

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Figure 5 Four –Digit Seven-Segment Display Interface to 8086 Microprocessor using 82C55 PPI
Yamama A. Shafeek
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Interrupt Mechanism, Types, and Priority

Interrupts provide a mechanism for quickly changing program environment.

Transfer of program control is initiated by the occurrence of either an event
internal to the microprocessor or an event in its external hardware.

The 8086 microcomputers are capable of implementing any combination of

up to 256 interrupts. They are divided into five groups; external hardware
interrupts, Nonmaskable interrupt, Software interrupts, Internal interrupts,
and Reset. Their priority hierarchy is shown below.

Increasing
priority

Reset
Internal interrupts and exceptions
Software interrupts
Nonmaskable interrupt
External hardware interrupts

Figure 1 Types of Interrupts and Their Priority

The user defines the function of the external hardware, software, and
nonmaskable interrupt. For instance, hardware interrupts are often assigned to
devices such as the keyboard, printer, and timers. On the other hand, the
functions of the internal interrupts and reset are not user defined. They
perform dedicated system functions.

An example of a high-priority service routine that should not be interrupted is

that for a power failure. Once initiated, this routine should be quickly run to
completion to assure that the microcomputer goes through an orderly power-
down. A keyboard should also be assigned to a high-priority interrupt. This
will assure that the keyboard buffer does not get full and lock out additional
entries. On the other hand, devices such as the floppy disk or hard disk
controller are typically assigned to a lower priority level.
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Interrupt Vector Table

An address pointer table is used to link the interrupt type numbers to the
locations of their service routines in the program-storage memory. Figure 2
shows a map of the pointer table in the memory of the 8086 microcomputer.

Figure 2 Interrupt Vector Table of the 8086

The interrupt vector table contains 256 address pointers (vectors). Which are
identified as vector 0 through vector 255. That is, one pointer corresponds to
each of the interrupt types 0 through 255. These address pointers identify the
starting location of their service routines in program memory.
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The pointer table is located at the low-address end of the memory address
space. It starts at address 00000H and ends at 003FEH. This represents the
first 1Kbytes of the memory.

Each of the 256 pointers requires two words (4 bytes) of memory and is
always stored at an even-address boundary. For example, the offset and base
address for type number 255, IP255 and CS255, are stored at word addresses
003FCH and 003FEH, respectively. When loaded into the MPU, it points to
the instruction at CS255:IP255.

The first 31 pointers either have dedicated functions or are reserved. The 27
reserved pointers, 5 through 31, represent a reserved portion of the pointer
table and should not be used. The remainder of the table, the 224 pointers in
the address range 00080H through 003FFH, is available to the user for storage
of software or hardware interrupt vectors.

Software Interrupts

The 8086 microcomputer system is capable of implementing software

interrupts their service routines are initiated (without interrupt
acknowledgments bus cycles) in response to the execution of a software
interrupt instruction (not external hardware). Software interrupts are not
masked out by IF.

Interrupt Instructions

A number of instructions are provided in the instruction set of the 8086

microprocessors for use with interrupt processing.

Mnemonic Meaning Format Operation Flags affected

Clear interrupt
CLI CLI 0 (IF) IF
flag
STI Set interrupt flag STI 1 (IF) IF
(Flags) ((SP)-2)
Type n software 0 TF,IF
INT n INT n TF, IF
interrupt (CS) ((SP)-4)
(2+4*n) CS

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(IP) ((SP)-6)
(4*n) (IP)
((SP)) (IP)
((SP)+2) (CS)
IRET Interrupt return IRET All
((SP)+4) (Flags)
(SP)+ 6 (SP)
Interrupt on
INTO INTO INT 4 steps TF , IF
overflow
Wait for an
HLT Halt HLT external interrupt None
or reset to occur
Wait for TEST
WAIT Wait Wait None
input to go active

o CLI Instruction permits manipulation of interrupt flag. It disables the

external interrupt input (INTR) by resetting IF.

o STI Instruction also permits manipulation of interrupt flag. It enables

the external interrupt input (INTR) for operation-that is, it sets IF.

o INT n Instruction used to initiate a vectored call of a subroutine. It

causes program control to be transferred to the subroutine pointed to by
the vector for the number n specified in the instruction.

For example, execution of the instruction INT 50 initiates execution of a

subroutine whose starting point is identified by vector 50 in the pointer table
in Figure 2. First the MPU saves the old flags on the stack, clears TF and IF,
and saves the old program context (CS and IP) on the stack. Then it reads the
values of IP50 and CS50 from addresses 000C8H and 000CAH, respectively, in
memory, loads them into the IP and CS registers, calculates the physical
address CS50:IP50, and starts to fetch instruction from this new location in
program memory.

o IRET Instruction must be included at the end of each interrupt service

routine. It causes the old values of IP, CS, and flags to be popped from
the stack back into the internal register of the MPU.
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o INTO Instruction must be included after arithmetic instructions that

can result in an overflow condition, such as divide. It tests the overflow
flag, and if the flag is found to be set, a type 4 internal interrupt is
initiated.

o HALT Instruction makes the MPU suspends operation and enters the
idle state.

o WAIT Instruction makes the MPU checks the logic level of the TEST
input prior to going into the idle state. Only if it is logic 1 then the
MPU will go into the idle state.

External Hardware-Interrupt Interface Sequence

The interrupt interface is a special input interface. When an interrupt request

has been recognized on the NMI pin, the 8086 initiate type 2 interrupt
(CS2:IP2). The NMI cannot be masked out with IF. Its input is positive edge
triggered. Therefore, a request for service is automatically latched internal to
the MPU.

If the INTR pin is logic 1, a request for service is recognized. The 8086
checks the IF if it = 0 then the interrupt request is ignored and the next
sequential instruction is executed. If IF = 1 then the service routine is initiated
and the 8086:

1. saves the flag register on the stack,

2. saves the old program context on the stack,
3. clears TF and IF.
4. responds with two pulses at INTA during interrupt acknowledge bus
cycle.

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Figure 3 Interrupt Acknowledgment Bus Cycle

During T1 of the first bus cycle, a pulse is output on ALE along with putting
the address/data bus on high impedance state and for the rest of the bus cycle.
During T2 and T3, INTA is switched to logic 0. This signals external circuitry
that the request is granted and the logic 1 at INTR can be removed.

The LOCK signal is produced only in the maximum mode. It is used to lock
other devices off the system bus, ensuring that the interrupt acknowledge
sequence continues to completion without interruption.

During the second bus cycle, a similar sequence occurs. External circuitry
puts the type number of the active interrupt on the data bus AD 0-AD7. This
code must be valid during periods T3 and T4 of the second bus cycle.

The RESET (active high) input of the 8086 MPU provides a hardware means
for initializing the microcomputer. when RESET goes back to logic 0 the
MPU clears all flags, sets IP to 0000H, CS to FFFFH, DS, SS, and ES all are
set to 0000H, and the instruction queue is emptied.

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Ex. Draw a circuit that places interrupt type number 60H on the data bus in
response to the INTR then:

(a) Write service routine at address 2000:1000H that increments the content
of memory location 0100H by 1 and outputs the new content at output port
5000H.

(b) Make this program an ISR for the type 60H interrupt.

Sol.

(a)

2000:1000H PUSH AX
PUSH DX
MOV DX, 5000H
MOV AX, [0100H]
INC AX
MOV [0100H], AX
OUT DX, AX
POP DX
POP AX
IRET

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(b)

Type 60H interrupt vector is stored at address

Address = 60H × 4 = 180H

Then IP60 (1000H) is stored at addresses 00180H and 00181H and CS60
(2000H) is stored at addresses 00182H and 00183H.

Internal Interrupt Functions

Internal interrupts occur due to a condition detected before, during, or after

execution of an instruction. They are not masked out with the interrupt flag.
No interrupt acknowledgments bus cycles are produced during the control
transfer sequence. There are four types of internal interrupts:

o Divide Error represents an error condition that can occur in the

execution of the division instruction. If the quotient of division result is
larger than the specified destination it causes automatic initiation of
type 0 interrupt.

o Single Step relates to an operation option of the 8086. If the trap flag
(TF) is set, the single-step mode of operation is enabled and the MPU
initiates type 1 interrupt service routine at the completion of execution
of every instruction of the user program.

o Breakpoint is inserted at strategic points in a program that is being

debugged to cause execution to be stopped automatically. The
breakpoint service routine can stop execution of the main program,
permit the programmer to examine the contents of registers and
memory, and allow for the resumption of execution of the program
down to the next breakpoint.

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o Overflow Error can result from the execution of any arithmetic

instruction. The transfer of program control to a service routine is not
automatic at occurrence of overflow condition. Instead, INTO
instruction must be executed to test the OF, if it is found to be set, a
type 4 interrupt service routine is initiated.

The 80286 Microprocessor

The 80286 microprocessor has 16-bit data bus and 24-bit address bus so it can
address memory up to 16 MB. None of its signal lines are multiplexed with
another signal. The instruction set of the 80286 is almost identical to the
8086, except for a few additional instructions that managed the extra 15M
bytes of memory. The clock speed of the 80286 was increased, so it executed
some instructions in as little as 250 ns with the original release 8.0 MHz. The
80286 was designed to run multitasking applications, including
communications, real-time process control, and multi-user systems.

The 80386 Microprocessor

The 80386 was Intel’s first practical 32-bit microprocessor that contained a
32-bit data bus and a 32-bit memory address that allowed it to address up to
4GB of memory. The instruction set of the 80386 was upward-compatible
with the earlier 8086, 80286 microprocessors.

The 80386 was available in a few modified versions such as 80386CX,

80386DX, 80386EX, 80386SX, and others.

 80386SX is a low cost version of the 80386 with a 16-bit data bus to
simplify circuit board layout and reduce total cost. This simplified
designs but hampered performance. Only 24 pins were connected to the
address bus, therefore limiting addressing to 16 MB.
 80386SL was introduced as a power efficient version for laptop
computers. The processor offered several power management options,
as well as different "sleep" modes to conserve battery power. It also
contained support for an external cache of 16 to 64 KB.

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The 80486 Microprocessor

The 80486 family is the Intel’s second generation of 32-bit microprocessors.

The 80486 has a 32-bit data bus and a 32-bit address bus. The 32-bit address
bus of the 80486 enabled up to 4 GB of memory to be directly addressed. An
8 KB on-chip cache stores the most recently used instructions and data.

The internal architecture of the 80486 was modified so that about half of its
instructions executed in one clock instead of two clocks. Also the 80486 was
available in different versions.

The Pentium Microprocessor

The Pentium introduced in 1993, the Pentium processor’s 32-bit architecture

is enhanced with a 64-bit external data bus and a variety of internal data paths
that are 64-bits, 128-bits, or 256-bits wide. It is able to address 4 GB and has
16 KB cache.

The Pentium processors employ an advanced superscaler pipelined internal

architecture which gives the Pentium processors the ability to execute more
than one instruction per clock cycle.

Another feature that enhances performance is a jump prediction technology

that speeds the execution of programs that include jump.

Real Mode

The 80286 and above operate in either the real or protected mode. Only the
8086 operate exclusively in the real mode. Real mode operation allows the
microprocessor to address only the first 1M byte of the memory space. The
DOS operating system requires the microprocessor to operate in the real
mode. Real mode operation allows application software written for the 8086,
which contain only 1M byte of memory, to function in the 80286 and above
without changing the software. In all cases, each of these microprocessors
begins operation in the real mode by default whenever power is applied or
microprocessor is reset.

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Protected Mode

When configured for protected-mode the microprocessor provides more

instruction and advanced software architecture (like memory management,
paging and multitasking for 80386).

Virtual 8086 Mode

This special mode is designed so that multiple 8086 real-mode software

applications can execute at one time. The virtual 8086 mode can be used to
share one microprocessor with many users by portioning the memory so that
each user has its own DOS partition. When in this mode, the 80386DX (and
above) support an 8086 microprocessor programming model and can directly
run programs written for the 8086. That is, it creates a virtual 8086 machine
for executing the program.

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Microprocessors and Microcontrollers

Microprocessor Microcontroller
Hardware architecture: Hardware architecture:

Microprocessor is a single-chip CPU Microcontrollers contain, in a single

IC, a CPU and much of remaining
circuitry of a complete
microcomputer system, like RAM,
ROM, a serial interface, a parallel
interface, timer, and interrupt
scheduling circuitry all within in the
same IC
Instruction set features: Instruction set features:

Instruction sets are processing Microcontrollers have instruction sets

intensive implying they have catering to the control of inputs and
powerful addressing modes with outputs. They have instructions to set
instructions catering to operations on and clear individual bits and perform
large volumes of data. Their other bit-oriented operations such as
instructions operate on bytes, words logically ANDing, ORing or XORing
and double words. Addressing bits.
modes provide access to large arrays The instructions are highly compact.
of data, using address pointers and The majority of instructions are
offset. implemented in a single byte.

Applications: Applications:

Microprocessors are most commonly Microcontrollers are found in small,

used as the CPU in microcomputer minimum-component designs
systems. They are suited to performing control-oriented activities.
processing information in computer They are suited to control of I/O
systems. devices in designs requiring
minimum component count.
Example: Example:

8086, 80286 . . . 8048, 8051 . . .

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