UNIT 3

DIGITAL SIGNAL PROCESSORS

3.1 INTRODUCTION

The Texas Instruments TMS320LF2407 DSP Controller (referred to as the LF2407 in

this text) is a programmable digital controller withaC2xx DSP central processing unit (CPU) as
the core processor. The LF2407 contains the DSP core processor and useful peripherals
integrated onto a single piece of silicon. The LF2407 combines the powerful CPU with on-chip
memory and peripherals. With the DSP core and control-oriented peripherals integrated into a
single chip, users can design very compact and cost-effective digital control systems.

The LF2407 DSP controller offers 40 million instructions per second (MIPS)
performance. This high processing speed of the C2xx CPU allows users to conpute

parameters in real time rather than look up approximations from tables stored in memory. This
fast performance is well suited for processing control parameters in applications such as notch
filters or sensor less motor control algorithms where a large amount of calculations must be
computed quickly.

While the brain" of the LF2407 DSP is the C2xx core, the LF2407 contains several
control-orientated peripherals onboard (see Fig. 3.1). The peripherals on the LF2407 make
virtually any digital control requirement possible. Their applications range from analog to digital
conversion to pulse width modulation (PWM) generation. Communication peripherals make
possible the communication with external peripherals, personal computers, or other DSP
processors. Below is a brief listing of the different peripherals onboard the LF2407 followed by a
graphical layout depicted in Fig. 3.1.

The LF2407 peripheral set includes:

" Two Event Managers (A and B)

" General Purpose (GP) timers
"PWM generators for digital motor control.
" Analog-to-digital converter
"Controller Area Network (CAN) interface
 "SerialPeripheral Interface (SPI) - synchronous serial port
. Serial
Communications Interface (SCI) asynchronous serial port
" General-Purpose bi-directional digital I/O
(GPIO) pins
. Watchdog Timer ("time-out" DSP reset
device for system integrity)

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12
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Figure 3.1 Graphical overview of DSP core andperipherals on the LF2407.

3.2 Brief Introduction to Peripherals
The following peripherals are those that are integrated onto the LF2407 chip. Refer to
Fig. 1.1 to view the pin-out associated with each peripheral.

2
Event Managers (EVA, EVB)
There are two Event Managers on the LF2407, the EVA and EVB. The Event Manager IS

the most important peripheral in digital motor control. It contains the necessary functions
needed to control electromechanical devices. Each EV is composed of functional blocks
including timers, comparators, and capture units for triggering on an event, PWM logiC
circuits,quadrature-encoder-pulse (QEP) circuits, and interrupt logic.
The Analog-to-Digital Converter (ADC)
The ADCon the LF2407 is used whenever an external analog signal needs to be

sampled and converted to a digital number. Examples of ADC applications range from
a
sampling a control signal for use in a digital notch filtering algorithm or using the ADC in
useful in motor
control feedback loop to monitor motor performance. Additionally, the ADC is
resistor instead of an
control applications because it allows for current sensing using a shunt
expensive current sensor.
The Control Area Network (CAN) Module
for
While the CAN module will not be covered in this text, it is a useful peripheral
multi-master serial
specific applications of the LF2407. The CAN module is used for
integrity
communication between external hardware. The CAN bus has a high level of data
automobile, or industrial
and is ideal for operation in noisy environments such as in an
environments that require reliable communication and data integrity.
Serial Peripheral Interface (SPI) and Serial Communications Interface (SCI)
used for
The SPI is a high-speed synchronous communication port that is mainly
communicating between the DSP and external peripherals or another DSP device. Typical
uses of the SPI include communication with external shift registers, display drivers, or ADCs.
The SCI is an asynchronous communication port that supports asynchronous serial (UART)
digital communication between the CPU and other asynchronous peripherals that use the
standard NRZ (non-return-to-zero) format. It is useful in communication between external
devices and the DSP. Since these communication peripherals are not directly related to motion
control applications, they will not be discussed further in this text.

3
 Watchdog Timer (WD)
The Watchdog timer (WD) peripheral monitors software and hardware operations and
enabled) wilI
asserts a system reset when its internal counter overflows. The WD timer (when
the WD
count for a specific amount of time. It is necessary for the user's software to reset
there is a
timer periodically so that an unwanted reset does not occur. If for some reason
enters
CPUdisruption, the watchdog will generate a system reset. For example, if the software
timer will overflow and a
an endless loop or if the CPUbecomes temporarily disrupted, the WD
starting point.
DSP reset will occur, which will cause the DSP program to branch to its initial
CPU function
Most error conditions that temporarily disrupt chip operation and inhibit proper
of the CPU, thus
can be cleared by the WD function. In this way, the WD increases the reliability
ensuring system integrity.
General Purpose Bi-Directional Digital I/O(GPIO) Pins
LF2407 device, many of the
Since there are only a finite number of pins available on the
the secondary GPIO function. In
pins are multiplexed to either their primary function or
general-purpose input/output pin. The GPIO
most cases, a pin's second function will be as a
controlling the functionality of pins and
capability of the LF2407 is very useful as a means of
data to and from the device. Nine 16-bit control
also provides another method to input or output
these registers:
registers control all L/O and shared pins. There are two types of
to control the multiplexer selection that
" I/O MUX Control Registers (MCRx) - Used
general-purpose LO function.
Chooses between the primary function of a pin or the
(PxDATDIR) - Used to control the data and data
" Data and Direction Control Registers
Direction of bi-directional I/O pins.

Phase Locked Loop (PLL)Clock Module

an input clock multiplier that allows
The phase locked loop (PLL) module is basically
a
user to control the input clocking frequency tothe DSP core. External to the LF2407,
the is
generated. This signal is fed into the LF2407 and
clock reference (can oscillator/crystal) is
or lower frequency) clock signal is then
multiplied or divided by the PLL. This new (higher
PLL allows the user to select a multiplication
used to clock the DSP core. The LF2407's
PLL
ranging from 0.5X to 4X that of the external clock signal. The default value of the
factor
is 4X.
4
Memory Allocation Spaces
The LF2407 DSP Controller has three different allocations of memory it can use: Data,
Program. and 1/0 memory space. Data space is used for program calculations, look-up
tables, and any other memory used by an algorithm. Data memory can be in the form of the on
chip random access memory (RAM) or external RAM. Program memory is the location of user's
program code. Program nmemory on the LF2407 is either mapped to the off-chip RAM
(MP/MC- pin =1)or to the on-chip flash memory (MP/MC- =0), depending on the logic value
of the MP/MC-pin.
1/Ospace is not really memory but a virtual memory address used to output data to
peripherals external to the LF2407. For example, the digital-to-analog converter (DAC) on the
TM
Spectrum Digital evaluation module is accessed with I/O memory. If one desires to output
data to the DAC, the data is simply sent to the configured address of I/O space with the "OUT"
command. This process is similar to writing to data memory except that the OUT command is
used and the data is copied to and outputted on the DAC instead of being stored in memory.

3.3 Types of Physical Memory

Random Access Memory (RAM)
The LF2407 has 544 words of l6 bits each in the on-chip DARAM. These 544 words are
partitioned into three blocks: B0, B1, and B2. Blocks Bl and B2 are allocated for use only as
data memory. Memory block BO is different than Bl and B2. This memory block is normally
configuredas Data Memory, and hence primarily used to hold data, but in the case of the BO
block, it can also be configured as Program Memory. BO memory can be configured as
program or data memory depending on the value of the core level "CNF" bit.
"(CNF-0) maps B0 to data memory.
"(CNF=1) maps B0 to program memory.
The LF2407 also has 2K of single-access RAM (SARAM). The addresses associated
with the SARAM can be used for both data memory and program memory, and are software
configurable to the internal SARAM or external memory.

5
Non-Volutile Flaslh Memory
The LF2407contains 32K of on-chip tlash memory that can be mapped to program space
if the MP/MC-pin is made logie 0(tied to ground), The Ilush memory provides a permanent
location to store code that is unaflected by cutting power to the device. The flash mecmorycan be
clectronically programmed and erased many times to allow for code development. Usually, the
external RAM on the LF2407 Evaluation Module (EVM) board is used instead of the flash lor
code development due to the fact that aseparate "lash progranmming" routine must be performed
lo lash code into the flash memory. 'The on-chip Ilash is normally used in situations where the
DSP program necds to be tested where a JTAG connection is not practical or where the DSP
needs to be tested as a "stand-alone" device, F'or example, if a LF2407 was used to develop a
DSP control solution to an automobile braking system, it would be somewhat impractical to have
a DSP/JTAG/PCinterface inacar that is
undergoing perfornmance testing.
3.4 Introduction to the C2xx DSP Core and Code
Generation
The heart of the LF2407 DSP Controller is the C2xx DSP corc. This core is a l6-bit fixed
point processor, meaning that it works with 16-bit binary numbers. One can think of the C2xx as
the central processor in a personal computer. The LF2407 DSP consists of the C2Xx DSP core
plus many peripherals such as Event Managers, ADC, etc., all integrated onto one single chip.
3.5 The Components of the C2xx DSP Core:
The DSP core (like all microprocessors) consists of several
subcomponents necessary to
perform arithmetic operations on 16-bit binary numbers. The following is a list of the multiple
subcomponents found in the C2xx core which we will discuss further:
"A 32-bit central arithmetic logic unit (CALU)
"A32-bit accumulator (used frequently in programs)
" Inputand output data-scaling shifters for the CALU
" A(16-bit by 16-bit) multiplier
"A product-scaling shifter
Eight auxiliary registers (ARO - AR7) and an auxiliary register arithmetic unit
(ARAU)
Each of the above components is eitlher accessed directly by the user code or is indirectly
uscd during the execution of an assembly command.

6
 oROCES

Central Arithmetic Logic Unit (CALU)

The C2xx performs 2s-complement arithmetic using the 32-bit CALU. The CALUuses
l6-bit words taken from data memory, derived from an immediate instruction, or from the 32
bit multiplier result. In addition to arithmetic operations, the CALUcan perform Boolean
operations. The CALUis somewhat transparent to the user. For example, if an arithmetic
command is used, the user only needs to write the command and later read the output from the
appropriate register. In this sense, the CALUis transparent" in that it is not accessed directly by
the user.

Accumulator

The accumulator stores the output from the CALUand also serves as another input to the CALU
(many arithmetic commands perform operations on numbers that are currently stored in the
accumulator; versus other memory locations). The accumulator is 32 bits wide and is divided
into two sections, each consisting of 16 bits. The high-order bits consist of bits 31 through 16,
and the low-order bits are made up of bits 15 through 0. Assembly language instructions are
provided for storing the high- and low-order accumulator words to data memory. In most cases,
the accumulator is written to and read from directly by the user code via assembly commands. In
some instances, the accumulator is also transparent to the user (similar to the CALUoperation in
that it is accessed "behind the scenes).
Scaling Shifters
The C2xx has three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic, and

overflow-prevention operations. The scaling shifters make possible commands that shift data left
or right. Like the CALU, the operation of the scaling shifters is transparent" to the user. For
example, the user needs only to use a shift command, and observe the result. Any one of the
three shifters could be used by the C2xx depending on the specific instruction entered. The
following is a description of the three shifters:
" Input data-scaling shifter (input shifter): This shifter left-shifts 16-bit input data by 0 to 16
bits to align the data to the 32-bit input of the CALU. For example, when the
user uses a
command such as *ADD 300h, 5", the input shifter is responsible for first shifting the data in
memory address $300h" to the left by five places before it is added to the
contents of the
accumulator.

7
" Qutput data-scaling shifter (output shifter): This shifter left-shifts data from the accumulator
by 0 to 7 bits before the output is stored to data memory. The content of the accumulator
remains unchanged. For example, when the user uses a command such as "SACL 30Oh, 4",

the output shifter is responsible for first shifting the contents of the accumulator to the left by
four places before it is stored to the memory address "300h".
Product-scaling shifter (product shifter): The product register (PREG) receives the output
of the multiplier. The product shifter shifts the output of the PREG before that output is sent
to the input of the CALU.The product shifter has four product shift modes (no shift, left shift
by one bit, left shift by four bits, and right shift by six bits), which are useful for performing
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.
Multiplier
The multiplier performs 16-bit, 2s-complement multiplication and creates a 32-bit result.
In conjunction with the multiplier, the C2xx uses the l6-bit temporary register (TREG) and the
32-bit product register (PREG).
The operation of the multiplier is not as "transparent' as the CALUor shifters. The
TREG always needs to be loaded with one of the numbers that are to be multiplied. Other than
this prerequisite, the multiplication commands do not require any more actions from the user
code. The output of the multiply is stored in the PREG, which can later be read by the user code.
Auxiliary Register Arithmetic Unit (ARAU) and Auxiliary Registers
The ARAU generates data memory addresses when an instruction uses indirect addressing to
access data memory (more on indirect addressing will be covered later along with assembly
programming). Eight auxiliary registers (ARO through AR7) support the ARAU, each of which
can be loaded with a 16-bit value from data memory or directly from an instruction. Each
auxiliary register value can also be stored in data memory. The auxiliary registers are mainly
used as "pointers" to data memory locations to more easily facilitate looping or repeating
algorithms. They are directly written to by the user code and are automatically incremented or
decremented by particular assembly instructions during a looping or repeating operation. The
auxiliary register pointer (ARP) embedded in status register STO references the auxiliary register.
The status registers (ST0, STI) are core level registers where values such as the Data Page (DP)
and ARP located.

8
3.6 Sstem Configuration Registers:
configure or
The System Control and Status Registers (SCSRI, SCSR2) are used to
the
display fundamental settings of the LF2407. For exanmple,these fundamental settings include
peripherals are enabled.
clock speed (clock pre-scale setting) of the LF2407, which
microprocessor microcontroller mode, etc. Bits are controlled by writing to the corresponding
an external pin as with the
data memory address or the logic level
microprocessormicrocontroller (MPMC) select bit. The bit descriptions of these two registers

(mapped to data memory) are listed below.

System Control and Status Register 1(SCSRI)- Address 07018h
13 12 11 10
15
CLK PS2 CLK PS1 CLK PSO Reserved
Reserved CLKSRC LPM1 LPMO
RW-1 RW-1 R-O
RW-0 RW-O RW-0 RW-1
R-O
3 2
7
EVA Reserved ILLADR
SCI SPI CAN EVB
ADC CLKEN
CLKEN CLKEN CLKEN CLKEN
CLKEN
RW-0 RW-0 R-O RC-0
RW-0 RW-0 RW-O RW-O

cleai, -0 = value after reser.

Note: R =read access, W=write access, C=
Bit 15Reserved
Bit 14 CLKSRC. CLKOUT pin source select
device) as the output
CLKOUT pin has CPU Clock (40 MHz on a 40-MHz
CLKOUT pin has Watchdog clock as the output
select
Bits 13-12LPM (1:0). Low-power mode
entered when the CPUexecutes the IDLE
These bits indicate which low-power mode is
instruction. Description of the low-power modes:
Low-Power mode selected
LPAI(1:0)
IDLE1 (LPMO)
00
IDLE2. (LPM1)
01
HALT (LPM2)
Bits ||-9
input clock.
prescale select. These bits select the PLL multiplication factor for the
PLL Clock
System Clock Frequency
CLK CLK CLK
PS2 PS1 PS0
4 x Fin
1 2x Fin
1.33 x Fn
1
1 1 1 x Fin
0.8 x Fin
1
0.66 x Fn
1
0.57 x Fin
0.5 x Fin
1 1
Note: Fn is the input clock frequency.

Bit 8 Reserved
control bit.
Bit 7 ADC CLKEN, ADC module clock enable
Clock to module is disabled (i.e., shut down to conserve power).
Clock to module is enabled and running normally.
Bit6 SCI CLKEN. SCI module clock enable control bit.
0 Clock to module is disabled (i.e., shut down to conserve power).
Clock to module is enabled and running normally.

Bit 5 SPI CLKEN. SPImodule clock enable control bit

0 Clock to module is disabled (i.e., shut down to conserve power)
Clock to module is enabled and running normally
Bit 4 CAN CLKEN. CAN module clock enable control bit
0 Clock to module is disabled (i.e., shut down to conserve power)
Clock to module is enabled and running normally
Bit 3 EVB CLKEN. EVB module clock enable control bit
0 Clock to module is disabled (i.e., shut down to conserve power)
Clock to module is enabled and running normally
Bit 2 EVA CLKEN. EVA module clock enable control bit
Clock to module is disabled (i.e., shut down to conserve power)
Clock to module is enabled and running normally
Note: In order to modify/read the register contents of any peripheral, the clock to that peripheral
must be enabled by writing a Ito the appropriate bit.
10
Bit IReserved
Bit 0 ILLADR. IIlegal Address detect bit

If an illegal address has occurred, this bit will be set. It is up to software to clear this bit
following an illegal address detects. This bit is cleared by writing a l to it and should be cleared
as part of the initialization sequence. Note: An illegal address will cause a Non-Mask able
Interrupt (NMI).
System Control and Status Register 2 (SCSR2) Address 07019h

15-8
Reserved
RW-O
7 6 3 2

Reserved VP QUAL WD XMIF H-Z BOOT EN MP/MC DON PON

OVERRIDE

RW-0 RC-1 RW-0 RW-BOOT RW RW-1 RW-1

EN pin MPIMC pin

Note: R =read access, W= write access, C = clear, -0 = value after reset.

Bits 15-7 Reserved. Writes have no effect; reads are undefined
Bit 6 Input Qualifier Clocks.
An input-qualifier circuitry qualifies the input signal to the CAPI-6, XINTI/2,
ADCSOC, and PDPINTA/B pins in the 240xA devices. The lVO functions of these pins do not
use the input-qualifier circuitry. The state of the internal input signal will change only after the
pin is held high/low for 6 (or 12) clock edges. This ensures that a glitch smaller than (or equal to)
5(or 11) CLKOUT Cycles wide will not change the internal pin input state. The user must hold
the pin high/low for 6 (or 12) cycles to ensure that the device will see the level change. This bit
determines the width of the glitches (in number of internal clock cycles) that will be blocked.
Note that the internal clock is not the same as CLKOUT, although its frequency is the same as
CLKOUT.
The input-qualifier circuitry blocks glitches up to 5 clock cycles long
1 The input-qualifier circuitry blocks glitches up to 1lclock cycles long
Note: This bit is applicable only for the 240xA devices, not for the 240x devices because they
lack an input-qualifier circuitry.
 Bit 5 Watchdog Override. (WD protect bit)
the WD function through
After RESET, this bit gives the user the ability to disable
clear-only bit and defaults to
software (by setting the WDDIS bit = | in the WDCR). This bit is a
a l after reset.

Note: This bit is cleared by writing a l to it.

Protects the WD from being disabled by software. This bit cannot be set to 1by

software. It isa clear-only bit, cleared by writing a 1.

This is the default reset value and allows the user to disable the WD through the

WDDIS bitin the WDCR. Once cleared, however, this bit can no longer be set to Iby software,
thereby protecting the integrity of the WD timer.
Bit 4 XMIF Hi-Z Control
This bit controls the state of the external memory interface (XMIF) signals.
XMIF signals in normal driven mode; i.e., not Hi-Z (high impedance).
1 AllXMIF signals are forced to Hi-Z state.
Bit 3Boot Enable
This bit reflects the state of the B00T EN /XF pin at the time of reset. After reset and device
has "booted up'", this bit can be changed in software to re-enable Flash memory visibility or
return to active Boot ROM.

Enable Boot ROM - Address space 0000 00FF is now occupied by the on
chip Boot ROM Block. Flash memory is totally disabled in this mode. Note: There is no on-chip
boot ROM in ROM devices (i.e., LC240xA)
Disable Boot ROM Program address space 0000 -- 7FFF is mapped to on
chip Flash memory in the case of LF2407A and LF2406A. In the case of LF2402A, addresses
0000 - 1FFF are mapped
Bit 2Microprocessor/Microcontroller Select
This bit reflecis the state of the MP/MC pin at time of reset. After reset, this bit can be changed
in software to allow dynamic mapping of memory on and off chip.
Set to Microcontroller mode - Program Address range 0000 -- 7FFF is mapped
internally (ie., Flash)
Set to Microprocessor mode Program Address range 0000 -7FFF is mapped
extemally (i.e.,customer provides external memory device.)

12
3.7 Memory Addressing Modes:
used by the C2xx instruction set. The three
There are three basic memory addressing modes
modes are:
Ar Immediate addressing mode (does not actually access memory)
I" Direct addressing mode
1" Indirect addressing mode
3.7.1 Immediate Addressing Mode
instruction contains a constant to be manipulated by the
In the immediate addressing mode, the
addressing" suggests that a memory location is
instruction. Even though the name immediate
usually
with a user-specified constant which is
accessed, immediate addressing is simply dealing an immediate
assembly command syntax. The #" sign indicates that the value
included in the
immediate addressing modes are:
address (just a constant).The two types of
short-immediate addressing have an 8
Short-immediate addressing. The instructions that use
bit, 9-bit, or 13-bit constant as the operand.
For example, the instruction:
LACL #44h ;loads lower bits of accumulator with
;Eight-bit constant (44h in this case)
a long
command will work only with ashort 8-bit constant. If you want to load
Note: The LACL
LACC command.
16-bit constant, then use the
long-immediate addressing have a 16-bit
Long-immediate addressing. Instructions that use
constant or as a 2s
operand. This 16-bit value can be used as an absolute
constant as an
complement value.
instruction:
For example, the
LACC #4444h :loads accumulator with up to a l6-bit
;Constant (4444h in this case)
you must use either direct or
access locations in data memory,
If you need to use registers or
indirect addressing.
3.7.2 Direct Addressing Mode words called data
addressing, data memory is first addressed in blocks of 128
In direct 511, as shown in
64K of data memory consists of 512 DPs labeled 0 through
pages. The entire register
DP is determined by the value in the 9-bit DP pointer in status
the Fig. 3.2. The current 14
 0. If the DP value is "0
For example, if the DP value is "0 0000 0000", the current DP is
STO.
particular memory address can be found
0000 0010", the current data page is 2. The DP of a

easily by dividing the address (in hexadecimal) by 80h.

pointer is 6h.
example: For the data memory address 0300h, 300h/80h = 6h so the DP
For
Likewise, the DP pointer for 200h is 4h.
DP Value Offset Data Memory
0000 0000 0 000 0000
Page 0: 0000h-007Fh
0000 0000 0 111 1111
0000 0000 1 000 0000
Page 1: 0080h-0OFFh
0000 0000 1 111 1111
0000 0001 0 000 0000
Page 2: 0100h-017Fh
0000 0001 0 111 1111

1111 1111 1 000 0000

Page 511: FFB0h-FFFFh
1111 11111111.1111

Figure 3.2 Data pages and corresponding memory ranges.

In addition to the DP, the DSP must know the particular word being referenced on that
page. This is determined by a 7-bit offset. The 7-bit offset is simply the 7 least significant bits
(LSBs) of the memory address. The DP and the offset make up the 16-bit memory address (see
Fig. 3.3).

15
 Data page potnter (DP) Instruction rogister (|R)

9bits 8MSBS 7LSBS

All 9 bits from DP 7LSBs from IR

Page (9 MSBs) Offset (7 LSBS)

16-bit date-memory address
Figure 3.3 Data page and offset make up a 16-bit memory address.
When youuse direct addressing, the processor uses the 9 DP bits and the 7 LSBs of the
instruction to obtain the true memory address. The following steps should be followed when
using direct addressing:
Set the DP. Load the appropriate value (from 0 to 511 in decimal or 0-1FF in hex) into
the DP. The easiest way to do this is with the LDP instruction. The LDP instruction loads
the DP directly to the STO register without affecting any other bits of the ST0.

LDP#0Elh ;sets the data page pointer to Elh

Or
LDP #225 ;sets the datapage pointer to 225 decimal
; Which is El in hexadecimal
2 Specify the offset. For example, if you want the ADD instruction to use the value at the
second address of the current data page, you wouldwrite: ADD lh
Ir the data page points to 300h, then the above instruction will add the contents of 301h to the
accumulator
Note: You do not have to set the data page prior to every instruction that uses direct
addressing, If all the instructions in a block of code access the same data page, you can simply
load the DPbefore the block. However, if various data pages are being accessed throughout the
block of code be sure the DP is changed accordingly.
Examples of Direct Addressing
In Example 1, the first instruction loads the DP with 0 0000 0100, to set the current data
page to 4. The ADD instruction then references a data memory address that is generated as
16
shown tollowing the program code. Before the ADD
instruction is executed, the opcode is
loaded into the instruction register. Together. the DP
and the seven LSBs of the
register form the complete 16-bit address,0000 instruction
0010 0000 10012(0209h).
In Example 2, the ADD
instruction references a data memory address that is generated as
shown following the program code. For any
is not embedded directly in the
instruction that performs a shift of 16, the shift value
instruction word: instead, all eight MSBs contain an opcode
not only indicates the that
instruction type, but also a shift of 16. The eight MSBs of the
word indicate an ADD with a shift of 16. instruction
Example l Using Direct Addressing with ADD
(Shift of 0to 15)
LDP #4 ;Set ata page to 4
ADD 9h,5 ; The
contents of data(addresses 0200h-027Fh)
address 0209h are
;left shifted 5 bits and
aáded to the
;Contents of the accumulatOr.
DP = 4
Instruction register (IR)
0000 0010 0
0010 0010 000 1001
ADD Shift of 5 9h
opcode
All 9 bits from DP
7LSBS from IR

0000 001 0 0 000 1001

16-bit data address 0209h

Example 2 Using Direct Addressing with ADD (Shift of 16)

17
 LDP #5 ;Set data page to 5 (addresses 0280n-02?Pa)
ADD 9h, 16 :The contents of ata adiress 0289n are
:left shifted 16 bits and a ied to thE
:contents oÍ the accumulator.

DP =5 instruction register (IR)

0000 0010 1 0110 0001 000 1001

ADD with shift of 16

opcode
All9 bits from DP 7 LSBS frorm iR

0000 D010 1 000 1 001

16-bit data address 0289h

In Example 3, the ADDCinstruction references a data memory address that is generated

as shown following the program code. You should note that if an instruction does not perforn
shifts (such as the ADDC instruction), all eight MSBs of the instruction contain the opcode for
the instruction type.
Example3 Using Direct Addressing with ADDC

LDP #500 ;Set ata page to 500 (adiresses FA00h-FA7Fh).

ADDC 6h :The contents of data a iress PA06h
;and the value of the carry bit (C) are
;adied to the contents of the accumulato.

DP = 500 Instruction register (IR)

1111 1010 0 0110 0000 000 0110
ADDC opcode 6h

All 9 bits from DP 7 LSBS from IR

1111 1010 0 00001 10

16-bit data address FA06h

18
A 3.7.3 lndirect Addressing Mode
Indirect addressing is a powerful way of addressing data memory. Indirect
mode is not dependent on the current data page as is direct addressing
addressing. Instead, when using
indirect addressing you load the memory space that you
would like to access into one of e
auxiliary registers (ARx). The current auxiliary register acts as a
pointer that pointsto a specitic
memory address,
"The register pointed to by the ARP is referred to as
the current auxiliary register or
current AR.To select a specific auxiliary register, load the 3-bit
auxiliary register pointer (ARP)
with a value from 0 to 7. The ARP can be
loaded with the MAR instruction or by the LARP
instruction. An ARP value can also be loaded by using the ARX
operand after any instruction
that supports indirect addressing as seen below.
Example of using MAR:
ADD *, ARI ;Adds using current *, then makes ARI the
;New current AR for future uses
Example of using LARP
LARP #2 : this will make AR2 the current AR
The C2xX provides four types of indirect addressing options:
No increment or decrement. The instruction uses the
content of the current auxiliary
register as the data memory addresses but neither increments nor decrements the content
of the current auxiliary register.
Increment or decrement by 1. The instruction uses the content of the current auxiliary
register as the data memory address and then increments or decrements the content of the
current auxiliary register by one.
Increment or decrement by an index amount. The value in ARO is the index amount.
The instruction uses the content of the current auxiliary register as the data
memory
address and then increments or decrements the content of the current auxiliary register by
the index amount.

Increment or decrement by an index amount using reverse carry. The value in AR0 i
the index amount. After the instruction uses the content of the current auxiliary register as
the data memory address, that content is incremented or decremented by the index
19
 Example 2, illustrates how the
instruction register is loaded with the value
instruction is fetched from program shown when the ADD
Example 2. Indirect memory.
ADD *+,8,AR4
Addressing-Increment by I

;Operates
;in
as in Examp le 1 but
addition,
¿register
the current
byauxiliary
is
;AR4 ig chosenincremented
as the next one, and
;register. auxiliary
15 14 13 12
11 10 7 6 5 4
1 3 2 1
1
0 1 1 0
ADD opcode Shift = 8

NAR = 4
Addressing mode= indirect N= next AR specified
ARU= increment current AR
by 1
Example 3. Indirect Addressing
-Decrement by 1
ADD *-,8 :Operates as in Example 1 but in
¡addition, the current
iis
decremented by one. auxiliary register
Example 4. Indirect
Addressing-Increment by Index Amount
ADD *0+,8 ;Operates as in Example 1 but in
;addition, the content of
;isadded to the current register ARO
¡register. auxiliary

Example 5. Indirect Addressing-Decrement by Index Amount

ADD *0-,8 ;Operates as in Example 1 but in

;addition, the content of register ARO
:is subtracted from the
;register. current auxiliary

21
 amount. The addition and subtraction process is accomplished with the carry propagation
reversed and is useful in fast Fourier transforms algorithms.
Table 3.1 displays the various operands that are available for use with instructions while using
indirect addressing mode.
Operand Option Exomplo
No increment or decrement
LT loads the temporary register TREG with the content of
the data mennory address referenced by the current AR.
Increment by 1
LT loads the TREG ith the content of the data memory
address referenced by the current AR and then adds 1 to the
content of the current AR.
Decrement by 1 LT - loads the TREG WIth the content of the data memory
address referenced by the current AR and then subtracts
from the content of the current AR.
"0+ Incrennent by index amount LT '0+ loads the TREG with the content of the
data memory
address referenced by the current AR and then adds the
content of ARO to the content of the current AR.
"0 Decrement by index amount LT "0- oads the TREG With the content of the
data memory
address referenced by the current AR and then subtracts the
content of ARO from the content of the current AR.
*BRO+ Increment by index amount, LT BR0+ loads the TREG with the
adding with reverse carry content of the data
memory address referenced by the current AR and then adds
the content of ARO to the content of the current AR,
with reverse carry adding
*BRO Decrement by index anount, propagation.
LT BR0- loads the TREG with the
subtracting with reverse carry content of the data
memory address referenced by the current AR
subtracts the content of ARO from the content of theand then
AR, subtracting with bit reverse carry current
propagation.
Table 3.1 Indirect addressing operands.
Examples of Indirect Addressing
Examplel illustrates how the instruction register is loaded with the value
shown when the ADD
instruction is fetched from program memory.
Example 1. Indirect Addressing-No Increment or
Decrement
ADD *,8 :Add to the
accumulator the content of the
;data-memory
; current address referenced by the
:is auxiliary register. The data
left shifted 8 bits
before being added.
15 14 13 12
10 8 7 6 5 3 2 1 0
1 1
1
X X x
ADD opcode Shift =8

NAR = don't cares

Addressing mode = indirect
N= No next AR
specified
ARU No operation on
=
current AR

20
 nabledig 97 contaiTheLF240 nntrol-orient
*iaitalcontrol cecond MI
Taxas

3.8 Assembly Programming Using the C2Xx DSP Instruction Set

The complete detailed instruction set for the C2xx DSP core can be found in the
Texas
Instruments TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set:
Literature Number: SPRU160C. This reference guide contains a complete descriptive listing on
syntax, operands. binary opcode, instruction execution order, status bits affected by the
instruction, number of memory words required to store the instruction, and clock-cycles used by
the instruction. The Texas Instruments documentation on the assembly instruction set is very
well written. Each assembly instruction has a complete explanation of the instruction, all
optional operands, and severalexamples of the instructions used. Since including the instruction
set and conmplete documentation would make this book excessively long, we will assume the
reader has access to thedocumentation referred to above.
We willtherefore focus on developing code, not the instruction set itself. Each command starts
with the basic assembly instruction. Each command supports specific addressing modes and
options. For example, the ADD command will work with direct, indirect, and immediate
addressing. In addition to the basic command, many instructions have additional options that
may be used with the instruction.For example, the ADD command supports left shifting of the
data before it is added to the accumulator.

The following is the instruction syntax for the ADD command:

ADD dma [, shifi] ;Direct addressing
ADD dmna, 16 ;Direct with left shift of 16
ADD ind [, shift [, ARn]] ;Indirect addressing
ADD ind, 16[, ARn] ;Indirect with left shift of 16
ADD #k ;short immediate addressing
ADD #Ik [, shifi] ; Long immediate addressing
The following is a list of the various notations used in C2xX Syntax examples:
Italics Italic symbols in instruction syntax represent variables.
Example:
LACCdma, youcan use several ways to address the dma (data memory
address).
LACC *

Or

LACC 200h

22
 LACC V ; where "v" is any variable assigned to data memory
Where *, 200h, and v are the duta memory addresses
Boldiace Characters Boldface characters must be included in the syntax.
Example:
LAR dma, l6 : direct addressing with left shift of 16
LAR ARI, 60h, 16 ; load auxiliary ARI register with the memory contents of 60h that
was left shifted 16 bits
Example:
LACC dna, [shifi] optional lefl shift from0, 15; defaults to O
LACC nain coumter, 8 ;shifts contents of the variable "main counter" data 8 places to
the left before loading accumulator
)An optionaloperand may be placed in the placed here.
Example:
LACCind [, shift [, AR n)_] Indirect addressing
LACC %
; load Accum. W/contents of the memory
;Location pointed to by the current AR.
LACC *, 5 ; load Accum. With the contents of the
memory
;Location pointed to by the current AR after
;The memory contents are left shifted by 5
; Bits.
LACC *, 0, AR3 :load Accum. With the contents of the memory
;Location pointed to by the current AR after
;The memory contents are left shifted by 5
;Bits. Now you have the option of
choosing
:A new AR. In this case, AR3 will become the
:New AR.
|, xl[, x2]] Operands x1 and x2 are optional, but you cannot
include x2 without also including
xl.

23
 nrogrammat LF2407 contaihs ontrol-oriented
combin peripherals integ
LF2407
nn,The '*nlcontrol systems.
(MIPS)

It is optional when using indirect addressing to

shift value from 0...15 (even a modify the data. Once yousupply a left
shift of ), then you have the
option of changing to a new current
auxiliary register (AR).
# The # sign is prefix that signifies that the number used is a
constant as opposed to
memory location.
Example:
RPT #15 : this syntax is using short immediate addressing. It will repeat the next
instruction 15+1 times.
LACC #60h :this will load the accumulator with the
;:Constant 60h
LACC 60h :However, this instruction will load the
;Accumulator with the contents in the data
; Memory location 60h, not the constant #60h
We will now provide a few examples of using the instruction set. Example 2.1
performs a few
arithmetic functions with the DSP core and illustrates the nature of
assembly programming.
Programming with the assembly instruction set is somewhat different than languages such as C.
In a high-level language, to add two numbers we might just code c = a
+ b". In assembly, the
user must be sure to code everything that needs to happen in order for a task to be
executed. Take
the following example:
Example 2.1 - Add the two numbers 2" and 3";
LDP #6h ; loads the proper DP for dma 300h
SPLK #2, 300h ;store the umber "2" in memory address 300h
LACL #3 : load the accumulator with the numnber "3"
ADD 300h ;adds contents of 300h ("2 ") to the contents
; of the accumulator ("3 "): accumulator = 5
Another way:
LDP #6h ;loads the proper DP for dna 300h
SPLK #2h, 300h ;store the number "2h" in memory address
;300h
SPLK #3h, 301h ;stores the umber "3h" into memnory address
; 301h
24
 LACI 300h load the ecunmulutor with the contents In
;Memory locatlon 300h
ADD 30lh adds contents of memory address 301lh ("3h ")
; To the contents of the accumulator ("2h")
aceummulator 5h

Looping algorithms are very common inallprogramming languages, In high-level languages, the
"For" and "While" loops can be used, However, in assembly, we necd a slightly different
approach to perlorm arepeating algorithm. The following example is an algorithm that stores the
value " to memory locations 300h, 301h, 302h, 303h,and 304h.

Example 2.,2- Looping Algorithm Using the Auxiliary Register

LAR AR0, #4 : load auxiliary register Owilth #4
LARARI, #300h :this AR will be used as a memory pointer
LACL #Ih ;loads "!" into the accumulator
LOOPER MAR *, ARI ;makes ARIthe next current AR
SACL *+, ARO ;writes contents of uccumulator to address
pointed to by ARI, the "+" increments ARI
;By 1, next current ARis ARO
BANZ LOOPER :branch to LOOPER while current AR is not 0;
decrements current AR by 1 and branches
back to LOOPER
One might wonder if assembly language is so tedious to use, why not just program in a high
level language all the time. When code written in a high level language is comnpiled into
assembly, the length of the code increases substantially. For example, if' an assembly program
compiled. For
(akes up 50 lines, the same programn written in Cmight take I50 Iines afer it is
memory than
this reason, code written in assembly almost always executed faster and uses less
high-level language code.

25