High Accuracy/Low Current LIRC Flash MCU

HT66F2630

Revision: V1.10 Date: November 19, 2019

 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Table of Contents
Features................................................................................................................. 6
CPU Features...............................................................................................................................6
Peripheral Features.......................................................................................................................6

General Description.............................................................................................. 7
Block Diagram....................................................................................................... 7
Pin Assignment..................................................................................................... 8
Pin Description..................................................................................................... 9
Absolute Maximum Ratings............................................................................... 10
D.C. Characteristics............................................................................................ 10
Operating Voltage Characteristics...............................................................................................10
Standby Current Characteristics................................................................................................. 11
Operating Current Characteristics............................................................................................... 11

A.C. Characteristics............................................................................................ 12
High Speed Internal Oscillator – HIRC – Frequency Accuracy...................................................12
Low Speed Internal Oscillator – LIRC – Frequency Accuracy....................................................12
Operating Frequency Characteristic Curves...............................................................................13
System Start Up Time Characteristics........................................................................................13

Input/Output Characteristics............................................................................. 14
Memory Characteristics..................................................................................... 14
A/D Converter Electrical Characteristics.......................................................... 15
LVD/LVR Electrical Characteristics................................................................... 15
Internal Bandgap Reference Voltage Electrical Characteristics.................... 16
Power-on Reset Characteristics........................................................................ 16
System Architecture........................................................................................... 17
Clocking and Pipelining...............................................................................................................17
Program Counter.........................................................................................................................18
Stack...........................................................................................................................................18
Arithmetic and Logic Unit – ALU.................................................................................................19

Flash Program Memory...................................................................................... 19

Structure......................................................................................................................................19
Special Vectors...........................................................................................................................20
Look-up Table..............................................................................................................................20
Table Program Example..............................................................................................................20
In Circuit Programming – ICP.....................................................................................................21
On-Chip Debug Support – OCDS...............................................................................................22

Data Memory....................................................................................................... 22
Structure......................................................................................................................................22
General Purpose Data Memory..................................................................................................23
Special Purpose Data Memory...................................................................................................23

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HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Special Function Register Description............................................................. 25

Indirect Addressing Registers – IAR0, IAR1...............................................................................25
Memory Pointers – MP0, MP1....................................................................................................25
Bank Pointer – BP.......................................................................................................................26
Accumulator – ACC.....................................................................................................................26
Program Counter Low Register – PCL........................................................................................26
Look-up Table Registers – TBLP, TBHP, TBLH...........................................................................26
Status Register – STATUS..........................................................................................................27

EEPROM Data Memory....................................................................................... 28

EEPROM Data Memory Structure..............................................................................................28
EEPROM Registers....................................................................................................................28
Reading Data from the EEPROM...............................................................................................29
Writing Data to the EEPROM......................................................................................................30
Write Protection...........................................................................................................................30
EEPROM Interrupt......................................................................................................................30
Programming Considerations......................................................................................................30

Oscillators........................................................................................................... 32
Oscillator Overview.....................................................................................................................32
System Clock Configurations......................................................................................................32
Internal High Speed RC Oscillator – HIRC.................................................................................33
Internal 32kHz Oscillator – LIRC.................................................................................................33

Operating Modes and System Clocks.............................................................. 33

System Clocks............................................................................................................................33
System Operation Modes............................................................................................................34
Control Registers........................................................................................................................35
Operating Mode Switching..........................................................................................................37
Standby Current Considerations.................................................................................................41
Wake-up......................................................................................................................................41

Watchdog Timer.................................................................................................. 42
Watchdog Timer Clock Source....................................................................................................42
Watchdog Timer Control Register...............................................................................................42
Watchdog Timer Operation.........................................................................................................43

Reset and Initialisation....................................................................................... 44

Reset Functions..........................................................................................................................44
Reset Initial Conditions...............................................................................................................48

Input/Output Ports.............................................................................................. 50
Pull-high Resistors......................................................................................................................51
Port A Wake-up...........................................................................................................................52
I/O Port Control Registers...........................................................................................................52
Pin-shared Functions..................................................................................................................52
I/O Pin Structures........................................................................................................................55
Programming Considerations......................................................................................................55

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Timer Modules – TM........................................................................................... 56

Introduction.................................................................................................................................56
TM Operation..............................................................................................................................56
TM Clock Source.........................................................................................................................56
TM Interrupts...............................................................................................................................56
TM External Pins.........................................................................................................................57
Programming Considerations......................................................................................................57

Periodic Type TM – PTM..................................................................................... 59

Periodic TM Operation................................................................................................................59
Periodic Type TM Register Description.......................................................................................60
Periodic Type TM Operating Modes............................................................................................64

Analog to Digital Converter............................................................................... 73

A/D Converter Overview.............................................................................................................73
A/D Converter Register Description............................................................................................74
A/D Converter Reference Voltage...............................................................................................76
A/D Converter Input Signals........................................................................................................76
A/D Converter Operation.............................................................................................................77
Conversion Rate and Timing Diagram........................................................................................78
Summary of A/D Conversion Steps.............................................................................................78
Programming Considerations......................................................................................................79
A/D Conversion Function............................................................................................................79
A/D Conversion Programming Examples....................................................................................80

Low Voltage Detector – LVD.............................................................................. 82

LVD Register...............................................................................................................................82
LVD Operation.............................................................................................................................83

Interrupts............................................................................................................. 83
Interrupt Registers.......................................................................................................................83
Interrupt Operation......................................................................................................................86
External Interrupts.......................................................................................................................87
TM Interrupts...............................................................................................................................88
Time Base Interrupts...................................................................................................................88
A/D Converter Interrupt...............................................................................................................90
LVD Interrupt...............................................................................................................................90
EEPROM Interrupt......................................................................................................................90
Interrupt Wake-up Function.........................................................................................................91
Programming Considerations......................................................................................................91

Configuration Options........................................................................................ 92
Application Circuits............................................................................................ 92
Instruction Set..................................................................................................... 93
Introduction.................................................................................................................................93
Instruction Timing........................................................................................................................93
Moving and Transferring Data.....................................................................................................93
Arithmetic Operations..................................................................................................................93

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High Accuracy/Low Current LIRC Flash MCU

Logical and Rotate Operation.....................................................................................................94

Branches and Control Transfer...................................................................................................94
Bit Operations.............................................................................................................................94
Table Read Operations...............................................................................................................94
Other Operations.........................................................................................................................94

Instruction Set Summary................................................................................... 95

Table Conventions.......................................................................................................................95

Instruction Definition.......................................................................................... 97
Package Information........................................................................................ 106
8-pin SOP (150mil) Outline Dimensions...................................................................................107
10-pin MSOP (118mil) Outline Dimensions...............................................................................108
16-pin SSOP (150mil) Outline Dimensions...............................................................................109
16-pin NSOP (150mil) Outline Dimensions............................................................................... 110
20-pin NSOP (150mil) Outline Dimensions............................................................................... 111

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Features

CPU Features
• Operating voltage
♦ fSYS=2MHz: 1.8V~5.5V
♦ fSYS=4MHz: 1.8V~5.5V
♦ fSYS=8MHz: 2.2V~5.5V
• Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Oscillator types
♦ Internal High Speed RC – HIRC
♦ Internal Low Speed 32kHz RC – LIRC
• Multi-mode operation: FAST, SLOW, IDLE and SLEEP
• Fully integrated internal oscillators require no external components
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 8-level subroutine nesting
• Bit manipulation instruction

Peripheral Features
• Flash Program Memory: 2K×16
• RAM Data Memory: 128×8
• True EEPROM Memory: 64×8
• Watchdog Timer function
• 18 bidirectional I/O lines
• Two pin-shared external interrupts
• One Timer Module for time measurement, input capture, compare match output or PWM output
or single pulse output function
• Dual Time-Base functions for generation of fixed time interrupt signals
• 4 external channels 12-bit resolution A/D converter
• Low voltage reset function
• Low voltage detect function
• Package types: 8-pin SOP, 10-pin MSOP, 16-pin SSOP, 16/20-pin NSOP

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High Accuracy/Low Current LIRC Flash MCU

General Description
The device is a Flash Memory A/D type 8-bit high performance RISC architecture microcontroller.
Offering users the convenience of Flash Memory multi-programming features, the device also
includes a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog feature includes a multi-channel 12-bit A/D converter. A single extremely flexible Timer
Module provides timing, pulse generation and PWM generation functions. Protective features such
as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent
noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical
environments.
A full choice of internal high and low speed oscillators are provided and the two fully integrated
system oscillators require no external components for their implementation. The ability to operate
and switch dynamically between a range of operating modes using different clock sources gives
users the ability to optimize microcontroller operation and minimize power consumption.
The inclusion of flexible I/O programming features and Time-Base funcitons along with many other
features ensure that the device will find excellent use in applications such as timed wake up products
in addition to many others.

Block Diagram

Reset
RES ROM RAM Port A Driver PA0~PA7
Circuit I/O
2K × 16 128 × 8
Pin-Shared
INT0~ Interrupt EEPROM Stack Port B Driver PB0~PB7
Function
INT1 Controller 64 × 8 8-level
Timer
Port C Driver PC0~PC1
Pin-Shared Watchdog
With Port A & B LVD/LVR
Timer
Digital Peripherals
HT8 MCU Core
SYSCLK
Bus

VDD

VREF
Time Bases LIRC
32kHz 1.2V Pin-Shared
MUX

12-bit With Port A

MUX

VDD VDD HIRC ADC

2/4/8MHz AN0~AN3
VSS VSS
Clock System Pin-Shared
Analog to Digital Converter
With Port A

Analog Peripheral

: Pin-Shared Node

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Pin Assignment
PA3/INT0/PTCK/AN3 1 10 PA4/INT1/PTPI
VDD 1 8 VSS PA2/AN2/ICPCK/OCDSCK 2 9 PA5/PTPB/PTPI
PA7/RES 2 7 PA0/AN0/ICPDA/OCDSDA PA1/AN1/VREF 3 8 PA6/PTP
PA4/INT1/PTPI 3 6 PA1/AN1/VREF PA0/AN0/ICPDA/OCDSDA 4 7 PA7/RES
PA3/INT0/PTCK/AN3 4 5 PA2/AN2/ICPCK/OCDSCK VSS 5 6 VDD

HT66F2630/HT66V2630 HT66F2630/HT66V2630
8 SOP-A 10 MSOP-A

PB2/INT0 1 16 PA4/INT1/PTPI
PA3/INT0/PTCK/AN3 2 15 PA5/PTPB/PTPI
PA2/AN2/ICPCK/OCDSCK 3 14 PA6/PTP
PA1/AN1/VREF 4 13 PA7/RES
PA0/AN0/ICPDA/OCDSDA 5 12 PB5
PB0 6 11 PB4/PTCK
PB1 7 10 PB3/INT1
VSS 8 9 VDD

HT66F2630/HT66V2630
16 SSOP-A

PA7/RES 1 16 PB5
PA6/PTP 2 15 PB4/PTCK
PA5/PTPB/PTPI 3 14 PB3/INT1
PA4/INT1/PTPI 4 13 VDD
PB2/INT0 5 12 VSS
PA3/INT0/PTCK/AN3 6 11 PB1
PA2/AN2/ICPCK/OCDSCK 7 10 PB0
PA1/AN1/VREF 8 9 PA0/AN0/ICPDA/OCDSDA

HT66F2630/HT66V2630
16 NSOP-A

PB7 1 20 PB6
PA7/RES 2 19 PB5
PA6/PTP 3 18 PB4/PTCK
PA5/PTPB/PTPI 4 17 PB3/INT1
PA4/INT1/PTPI 5 16 VDD
PB2/INT0 6 15 VSS
PA3/INT0/PTCK/AN3 7 14 PB1
PA2/AN2/ICPCK/OCDSCK 8 13 PB0
PA1/AN1/VREF 9 12 PC0
PA0/AN0/ICPDA/OCDSDA 10 11 PC1

HT66F2630/HT66V2630
20 NSOP-A

Note: 1. The desired pin-shared function is determined by the corresponding pin-shared or functional control bits.
2. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such only available
for the HT66V2630 device which is the OCDS EV chip for the HT66F2630 device.
3. For the less pin count package type there will be unbounded pins which should be properly configured
to avoid unwanted power consumption resulting from floating input conditions. Refer to the “Standby
Current Considerations” and “Input/Output Ports” sections.

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High Accuracy/Low Current LIRC Flash MCU

Pin Description
The function of each pin is listed in the following table, however the details behind how each pin
is configured is contained in other sections of the datasheet. As the Pin Description table shows the
situation for the package with the most pins, not all pins in the tables will be available on smaller
package sizes.
Pin Name Function OPT I/T O/T Description
PAPU
General purpose I/O. Register enabled pull-up
PA0 PAWU ST CMOS
and wake-up.
PAS0
PA0/AN0/ICPDA/OCDSDA AN0 PAS0 AN — A/D Converter external analog input
ICPDA — ST CMOS ICP Data/Address pin
OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only.
PAPU
General purpose I/O. Register enabled pull-up
PA1 PAWU ST CMOS
and wake-up.
PA1/AN1/VREF PAS0
AN0 PAS0 AN — A/D Converter external analog input
VREF PAS0 AN — A/D Converter external reference input
PAPU
General purpose I/O. Register enabled pull-up
PA2 PAWU ST CMOS
and wake-up.
PAS0
PA2/AN2/ICPCK/OCDSCK AN2 PAS0 AN — A/D Converter external analog input
ICPCK — ST — ICP clock pin
OCDSCK — ST — OCDS clock pin, for EV chip only
PAPU
General purpose I/O. Register enabled pull-up
PA3 PAWU ST CMOS
and wake-up.
PAS0
PAS0
IFS
PA3/INT0/PTCK/AN3 INT0 ST — External Interrupt 0
INTEG
INTC0
PAS0
PTCK ST — PTM clock input
IFS
AN3 PAS0 AN — A/D Converter external analog input
PAPU General purpose I/O. Register enabled pull-up
PA4 ST CMOS
PAWU and wake-up.
IFS
PA4/INT1/PTPI
INT1 INTEG ST — External Interrupt 1
INTC0
PTPI IFS ST — PTM capture input
PAPU
General purpose I/O. Register enabled pull-up
PA5 PAWU ST CMOS
and wake-up.
PAS1
PA5/PTPB/PTPI
PTPB PAS1 — CMOS PTM inverted output
PAS1
PTPI ST — PTM capture input
IFS
PAPU
General purpose I/O. Register enabled pull-up
PA6 PAWU ST CMOS
PA6/PTP and wake-up.
PAS1
PTP PAS1 — CMOS PTM non-inverted output
PAPU
General purpose I/O. Register enabled pull-up
PA7 PAWU ST CMOS
PA7/RES and wake-up.
RSTC
RES RSTC ST — External reset input
PB0~PB1 PB0~PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up.

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Pin Name Function OPT I/T O/T Description

PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PB2/INT0 IFS
INT0 INTEG ST — External Interrupt 0
INTC0
PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PB3/INT1 IFS
INT1 INTEG ST — External Interrupt 1
INTC0
PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PB4/PTCK
PTCK IFS ST — PTM clock input
PB5~PB7 PB5~PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up.
PC0~PC1 PC0~PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up.
VDD VDD — PWR — Positive power supply
VSS VSS — PWR — Negative power supply, ground

Legend: I/T: Input type; O/T: Output type;

OPT: Optional by register option; PWR: Power;
ST: Schmitt Trigger input; CMOS: CMOS output;
AN: Analog signal.

Absolute Maximum Ratings

Supply Voltage...........................................................................................................VSS−0.3V to 6.0V
Input Voltage..................................................................................................... VSS−0.3V to VDD+0.3V
Storage Temperature...................................................................................................... -50°C to 125°C
Operating Temperature.................................................................................................... -40°C to 85°C
IOH Total....................................................................................................................................... -80mA
IOL Total........................................................................................................................................ 80mA
Total Power Dissipation............................................................................................................ 500mW

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to the device. Functional operation of
the devices at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics
For data in the following tables, note that factors such as oscillator type, operating voltage, operating
frequency, pin load conditions, temperature and program instruction type, etc., can all exert an
influence on the measured values.

Operating Voltage Characteristics

Ta=-40°C~85°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
fSYS=fHIRC=2MHz 1.8 — 5.5
Operating Voltage – HIRC fSYS=fHIRC=4MHz 1.8 — 5.5 V
VDD
fSYS=fHIRC=8MHz 2.2 — 5.5
Operating Voltage – LIRC fSYS=fLIRC=32kHz 1.8 — 5.5 V

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HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Standby Current Characteristics

Ta=25°C, unless otherwise specified.
Test Conditions Max.
Symbol Standby Mode Typ. Max. Unit
VDD Conditions @85°C
1.8V 0.2 0.6 0.7
3V WDT off 0.2 0.8 1.0 μA
5V 0.5 1.0 1.2
SLEEP Mode
1.8V 0.9 1.8 2.9
3V WDT on 1.0 2.0 3.6 μA
5V 2.2 4.5 6.0
1.8V 1.0 2.0 4.8
IDLE0 Mode – LIRC 3V fSUB on 1.3 2.5 6.0 μA
5V 2.5 5.0 12.0
ISTB
1.8V 60 100 160
3V fSUB on, fSYS=2MHz 80 120 240 μA
5V 160 240 360
1.8V 144 200 240
IDLE1 Mode – HIRC 3V fSUB on, fSYS=4MHz 180 250 300 μA
5V 400 600 720
2.2V 288 400 480
3V fSUB on, fSYS=8MHz 360 500 600 μA
5V 600 800 960

Note: When using the characteristic table data, the following notes should be taken into consideration:
1. Any digital inputs are set in a non-floating condition.
2. All measurements are taken under conditions of no load and with all peripherals in an off state.
3. There are no DC current paths.
4. All Standby Current values are taken after a HALT instruction execution thus stopping all instruction execution.

Operating Current Characteristics

Ta=25°C
Test Conditions
Symbol Operating Mode Min. Typ. Max. Unit
VDD Conditions
1.8V — 8 16
SLOW Mode – LIRC 3V fSYS=32kHz — 10 20 μA
5V — 30 50
1.8V — 0.2 0.4
3V fSYS=2MHz — 0.3 0.5 mA
5V — 0.6 1.0
IDD
1.8V — 0.3 0.5
FAST Mode – HIRC 3V fSYS=4MHz — 0.4 0.6 mA
5V — 0.8 1.2
2.2V — 0.6 1.0
3V fSYS=8MHz — 0.8 1.2 mA
5V — 1.6 2.4

Note: When using the characteristic table data, the following notes should be taken into consideration:
1. Any digital inputs are set in a non-floating condition.
2. All measurements are taken under conditions of no load and with all peripherals in an off state.
3. There are no DC current paths.
4. All Operating Current values are measured using a continuous NOP instruction program loop.

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

A.C. Characteristics
For data in the following tables, note that factors such as oscillator type, operating voltage, operating
frequency and temperature etc., can all exert an influence on the measured values.

High Speed Internal Oscillator – HIRC – Frequency Accuracy

During the program writing operation the writer will trim the HIRC oscillator at a user selected
HIRC frequency and user selected voltage of either 3V or 5V.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Temperature
25°C -1% 2 +1%
3V/5V -20°C~60°C -2% 2 +2%
-40°C~85°C -3% 2 +3%
2 MHz Writer Trimmed HIRC
25°C -6% 2 +9% MHz
Frequency 2.2V~5.5V
-40°C~85°C -6% 2 +10%
25°C -6% 2 +12%
1.8V~5.5V
-40°C~85°C -6% 2 +15%
25°C -1% 4 +1%
3V/5V
fHIRC -40°C~85°C -2.5% 4 +2.5%
4 MHz Writer Trimmed HIRC 25°C -2.5% 4 +2.5%
2.2V~5.5V MHz
Frequency -40°C~85°C -3% 4 +3%
25°C -3.5% 4 +3.5%
1.8V~5.5V
-40°C~85°C -4% 4 +4%
25°C -1% 8 +1%
3V/5V
8 MHz Writer Trimmed HIRC -40°C~85°C -10% 8 +2%
MHz
Frequency 25°C -10% 8 +3%
2.2V~5.5V
-40°C~85°C -15% 8 +5%

Note: 1. The 3V/5V values for VDD are provided as these are the two selectable fixed voltages at which the HIRC
frequency is trimmed by the writer.
2. The row below the 3V/5V trim voltage row is provided to show the values for the full VDD range
operating voltage. It is recommended that the trim voltage is fixed at 3V for application voltage ranges
from 1.8V to 3.6V and fixed at 5V for application voltage ranges from 3.3V to 5.5V.
3. The minimum and maximum tolerance values provided in the table are only for the frequency at which
the writer trims the HIRC oscillator. After trimming at this chosen specific frequency any change in
HIRC oscillator frequency using the oscillator register control bits by the application program will give a
frequency tolerance to within ±20%.

Low Speed Internal Oscillator – LIRC – Frequency Accuracy

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Temperature
25°C -0.5% 32 +0.5%
3V -20°C~70°C -3% 32 +3%
fLIRC 32kHz Writer Trimmed LIRC Frequency -40°C~85°C -4% 32 +4% kHz
25°C -3% 32 +3%
1.8V~5.5V
-40°C~85°C -7% 32 +7%

Note: The 3V value for VDD is provided as this is the fixed voltage at which the LIRC frequency is trimmed by
the writer. The row below the 3V trim voltage row is provided to show the values for the full VDD range
operating voltage.

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HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Operating Frequency Characteristic Curves

System Operating Frequency

8MHz

4MHz

2MHz
~
~

~
~

~
~
1.8V 2.2V 5.5V
Operating Voltage

System Start Up Time Characteristics

Ta=-40°C~85°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
System Start-up Time — fSYS=fH~fH/64, fH=fHIRC — 16 — tHIRC
Wake-up from Condition where fSYS is off — fSYS=fSUB=fLIRC — 2 — tSYS
System Start-up Time — fSYS=fH~fH/64, fH=fHIRC — 2 — tSYS
tSST Wake-up from Condition where fSYS is on — fSYS=fSUB= fLIRC — 2 — tSYS
System Speed Switch Time
FAST to SLOW Mode or — fHIRC switches from off → on — 16 — tHIRC
SLOW to FAST Mode
System Reset Delay Time
Reset source from Power-on Reset or — RRPOR=5V/ms
LVR Hardware Reset 42 48 54 ms
System Reset Delay Time
tRSTD LVRC/WDTC/RSTC Software Reset
— —

System Reset Delay Time

Reset source from WDT Overflow or RES — — 14 16 18 ms
pin reset
tSRESET Minimum Software Reset Width to Reset — — 45 90 120 μs

Note: 1. For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen
fSYS system oscillator. Details are provided in the System Operating Modes section.
2. The time units, shown by the symbols, tHIRC, etc. are the inverse of the corresponding frequency values as
provided in the frequency tables. For example tHIRC=1/fHIRC, tSYS=1/fSYS etc.
3. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up.

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 HT66F2630
High Accuracy/Low Current LIRC Flash MCU

Input/Output Characteristics
Ta=-40°C~85°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
5V — 0.0 — 1.5
Input Low Voltage for I/O Ports
VIL — — 0.0 — 0.2VDD V
Input Low Voltage for RES pin — — 0.0 — 0.4VDD
5V — 3.5 — 5.0
Input High Voltage for I/O Ports
VIH — — 0.8VDD — VDD V
Input High Voltage for RES pin — — 0.9VDD — VDD
3V 16 32 —
IOL Sink Current for I/O Ports VOL=0.1VDD mA
5V 32 65 —
3V -4 -8 —
IOH Source Current for I/O Ports VOH=0.9VDD mA
5V -8 -16 —
3V LVPU=0, 20 60 100
5V PxPU=FFH (x=A, B or C) 10 30 50
RPH Pull-high Resistance for I/O Ports(Note) kΩ
3V LVPU=1, 6.67 15.00 23.00
5V PxPU=FFH (x=A, B or C) 3.5 7.5 12.0
ILEAK Input Leakage Current for I/O Ports 5V VIN=VDD or VIN=VSS — — ±1 μA
tTPI PTPI Capture Input Minimum Pulse Width — — 0.3 — — μs
tTCK PTCK Clock Input Minimum Pulse Width — — 0.3 — — μs
tINT Interrupt Input Pin Minimum Pulse Width — — 10 — — μs
tRES External Reset Minimum Low Pulse Width — — 10 — — μs

Note: The RPH internal pull-high resistance value is calculated by connecting to ground and enabling the input pin
with a pull-high resistor and then measuring the pin current at the specified supply voltage level. Dividing
the voltage by this measured current provides the RPH value.

Memory Characteristics
Ta=-40°C~85°C, unless otherwise specified.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
Flash Program / Data EEPROM Memory
Operating Voltage for Flash Program Read/Write — — VDDmin — VDDmax V
VDD Operating Voltage for Data EEPROM Read — — 1.8 — 5.5 V
Operating Voltage for Data EEPROM Write — Ta=-40°C~85°C 2.2 — 5.5 V
Erase/Write Time – Flash Program Memory — — — 2 3 ms
tDEW
Write Cycle Time – Data EEPROM Memory — — — 4 6 ms
IDDPGM Programming/Erase Current on VDD — — — — 5 mA
Cell Endurance – Flash Program Memory — — 10K — — E/W
EP
Cell Endurance – Data EEPROM Memory — — 100K — — E/W
tRETD ROM Data Retention Time — Ta=25°C — 40 — Year
RAM Data Memory
VDD Operating Voltage for Read/Write — — VDDmin — VDDmax
VDR RAM Data Retention Voltage — Device in SLEEP Mode 1 — — V

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A/D Converter Electrical Characteristics

Ta=25°C, unless otherwise specified.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VADI Input Voltage — — 0 — VREF V
VREF Reference Voltage — — 1.8 — VDD V
VREF=VDD, tADCK=0.5μs,
DNL Differential Non-linearity — -3 — +3 LSB
Ta=-40°C~85°C
VREF=VDD, tADCK=0.5μs,
INL Integral Non-linearity — -4 — +4 LSB
Ta=-40°C~85°C
1.8V — 1.0 2.0
IADC Additional Current for A/D Converter Enable 3V No load, tADCK=0.5μs — 1.0 2.0 mA
5V — 1.5 3.0
tADCK Clock Period — — 0.5 — 10 μs
tON2ST A/D Converter On-to-Start Time — — 4 — — μs
Conversion Time
tADC — — — 16 — tADCK
(Including A/D Sample and Hold Time)

LVD/LVR Electrical Characteristics

Ta=25°C, unless otherwise specified.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
LVR enable, voltage select 1.70V,
-5% 1.70 +5%
Ta=-40°C~85°C
LVR enable, voltage select 1.90V,
-5% 1.90 +5%
Ta=-40°C~85°C
LVR enable, voltage select 2.55V,
VLVR Low Voltage Reset Voltage — -3% 2.55 +3% V
Ta=-40°C~85°C
LVR enable, voltage select 3.15V,
-3% 3.15 +3%
Ta=-40°C~85°C
LVR enable, voltage select 3.80V,
-3% 3.80 +3%
Ta=-40°C~85°C
LVD enable, voltage select 1.8V,
-5% 1.8 +5%
Ta=-40°C~85°C
LVD enable, voltage select 2.0V,
-5% 2.0 +5%
Ta=-40°C~85°C
LVD enable, voltage select 2.4V,
-5% 2.4 +5%
Ta=-40°C~85°C
LVD enable, voltage select 2.7V,
-5% 2.7 +5%
Ta=-40°C~85°C
VLVD Low Voltage Detect Voltage — V
LVD enable, voltage select 3.0V,
-5% 3.0 +5%
Ta=-40°C~85°C
LVD enable, voltage select 3.3V,
-5% 3.3 +5%
Ta=-40°C~85°C
LVD enable, voltage select 3.6V,
-5% 3.6 +5%
Ta=-40°C~85°C
LVD enable, voltage select 4.0V,
-5% 4.0 +5%
Ta=-40°C~85°C

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Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
3V LVD enable, LVR enable, — — 10
5V VLVR=1.9V, VLVD=2.0V, VBGEN=0 — 8 15
ILVRLVDBG Operating Current μA
3V LVD enable, LVR enable, — — 200
5V VLVR=1.9V, VLVD=2.0V, VBGEN=1 — 210 245
ILVR Additional Current for LVR Enable 5V LVD disable, VBGEN=0 — — 8 μA
ILVD Additional Current for LVD Enable 5V LVR disable, VBGEN=0 — — 8 μA
LVR enable, VBGEN=0,
— — — 15
LVD off → on, Ta=-40°C~85°C
tLVDS LVDO Stable Time μs
LVR disable, VBGEN=0,
— — — 150
LVD off → on, Ta=-40°C~85°C
Minimum Low Voltage Width to
tLVR — — 120 240 480 μs
Reset
Minimum Low Voltage Width to
tLVD — — 60 120 240 μs
Interrupt

Internal Bandgap Reference Voltage Electrical Characteristics

Ta=-40°C~85°C, unless otherwise specified.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VBG Bandgap Reference Voltage — Ta=-40°C~85°C -5% 1.2 +5% V
Additional Current for Bandgap
IBG — LVR disable, LVD disable — — 230 μA
Reference Voltage Enable
tBGS VBG Turn On Stable Time — No load — — 50 μs

Note: The VBG voltage is used as the A/D converter internal signal input.

Power-on Reset Characteristics

Ta=-40°C~85°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV
RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms
Minimum Time for VDD Stays at VPOR to
tPOR — — 1 — — ms
Ensure Power-on Reset

VDD

tPOR RRPOR

VPOR
Time

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System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
their internal system architecture. The device takes advantage of the usual features found within RISC
microcontrollers providing increased speed of operation and enhanced performance. The pipelining
scheme is implemented in such a way that instruction fetching and instruction execution are
overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or
call instructions which need one more cycle. An 8-bit wide ALU is used in practically all instruction
set operations, which carries out arithmetic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can
be directly or indirectly addressed. The simple addressing methods of these registers along with
additional architectural features ensure that a minimum of external components is required to provide
a functional I/O and A/D control system with maximum reliability and flexibility. This makes the
device suitable for low-cost, high-volume production for controller applications.

Clocking and Pipelining

The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
fSYS
(System Clock)

Phase Clock T1

Phase Clock T2

Phase Clock T3

Phase Clock T4

Program Counter PC PC+1 PC+2

Fetch Inst. (PC)

Pipelining
Execute Inst. (PC-1) Fetch Inst. (PC+1)
Execute Inst. (PC) Fetch Inst. (PC+2)
Execute Inst. (PC+1)

System Clocking and Pipelining

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1 MOV A,[12H] Fetch Inst. 1 Execute Inst. 1

2 CALL DELAY Fetch Inst. 2 Execute Inst. 2
3 CPL [12H] Fetch Inst. 3 Flush Pipeline
4 : Fetch Inst. 6 Execute Inst. 6
5 : Fetch Inst. 7
6 DELAY: NOP

Instruction Fetching

Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a non-
consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading
the required address into the Program Counter. For conditional skip instructions, once the condition
has been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter
Program Counter High Byte PCL Register
PC10~PC8 PCL7~PCL0
Program Counter

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly; however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.

Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack is organized into multiple levels and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.

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If the stack is overflow, the first Program Counter save in the stack will be lost.

Program Counter

Top of Stack Stack Level 1

Stack Level 2
Stack
Stack Level 3
Pointer Program Memory
:
:
:
Bottom of Stack Stack Level 8

Arithmetic and Logic Unit – ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement: INCA, INC, DECA, DEC
• Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Flash Program Memory

The Program Memory is the location where the user code or program is stored. For the device the
Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, the Flash device offers users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and updating.

Structure
The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which can
be set in any location within the Program Memory, is addressed by a separate table pointer register.

000H Reset
004H
Interrupt Vectors
024H

n00H
Look-up Table
nFFH

7FFH 16 bits

Program Memory Structure

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Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.

Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers
can store fixed data. To use the look-up table, the table pointer must first be configured by placing
the address of the look up data to be retrieved in the table pointer registers, TBLP and TBHP. These
registers define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL[m]” instructions respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.

Program Memory
Last Page or
TBHP Register Address
Data
16 bits
TBLP Register

Register TBLH User Selected

Register
High Byte Low Byte

Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is “700H” which refers to the start
address of the last page within the 2K words Program Memory of the device. The table pointer low
byte register is set here to have an initial value of “06H”. This will ensure that the first data read
from the data table will be at the Program Memory address “706H” or 6 locations after the start of
the last page. Note that the value for the table pointer is referenced to the specific address pointed by
the TBLP and TBHP registers if the “TABRD [m]” instruction is being used. The high byte of the
table data which in this case is equal to zero will be transferred to the TBLH register automatically
when the “TABRD [m]” instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.

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Table Read Program Example

tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or the page that tbhp pointed
mov a,07h ; initialise high table pointer
mov tbhp,a
:
:
tabrd tempreg1 ; transfers value in table referenced by table pointer,
; data at program memory address “706H” transferred to tempreg1 and
TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer,
; data at program memory address “705H” transferred to tempreg2 and TBLH
; in this example the data “1AH” is transferred to tempreg1 and data “0FH” to
; register tempreg2
; the value “00H” will be transferred to the high byte register TBLH
:
:
org 700h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

In Circuit Programming – ICP

The provision of Flash type Program Memory provides the user with a means of convenient and
easy upgrades and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a means of programming the microcontroller in-
circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to easily
keep their manufactured products supplied with the latest program releases without removal and re-
insertion of the device.
Holtek Writer Pins MCU Programming Pins Pin Description
ICPDA PA0 Programming Serial Data/Address
ICPCK PA2 Programming Clock
VDD VDD Power Supply
VSS VSS Ground

The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data
is downloaded and uploaded serially on a single pin with an additional line for the clock. Two
additional lines are required for the power supply and one line for the reset. The technical details
regarding the in-circuit programming of the device is beyond the scope of this document and will be
supplied in supplementary literature.
During the programming process, the user must take care of the ICPDA and ICPCK pins for data
and clock programming purposes to ensure that no other outputs are connected to these two pins.

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Writer Connector MCU Programming

Signals Pins

Writer_VDD VDD

ICPDA PA0

ICPCK PA2

Writer_VSS VSS

* *

To other Circuit

Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance
of * must be less than 1nF.

On-Chip Debug Support – OCDS

There is an EV chip named HT66V2630 which is used to emulate the HT66F2630 device. The EV
chip device also provides an “On-Chip Debug” function to debug the real MCU device during the
development process. The EV chip and the real MCU device are almost functionally compatible
except for “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip
device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development
tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is
the OCDS clock input pin. When users use the EV chip for debugging, other functions which are
shared with the OCDSDA and OCDSCK pins in the device will have no effect in the EV chip.
However, the two OCDS pins which are pin-shared with the ICP programming pins are still used
as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the
corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.
Holtek e-Link Pins EV Chip Pins Pin Description
OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output
OCDSCK OCDSCK On-Chip Debug Support Clock input
VDD VDD Power Supply
VSS VSS Ground

Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.

Structure
Categorised into two types, the first of these is an area of RAM, known as the Special Function Data
Memory. These registers have fixed locations and are necessary for correct operation of the device.
Many of these registers can be read from and written to directly under program control, however,
some remain protected from user manipulation. The second area of Data Memory is known as the
General Purpose Data Memory, which is reserved for general purpose use. All locations within this
area are read and write accessible under program control.

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The overall Data Memory is subdivided into two banks, which are implemented in 8-bit wide
Memory. The Special Purpose Data Memory registers are accessible in Bank 0, with the exception
of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the
different Data Memory banks is achieved by properly setting the Bank Pointer to the correct value.
The start address of the Data Memory for the device is the address 00H. The address range of the
Special Purpose Data Memory for the device is from 00H to 7FH while the address range of the
General Purpose Data Memory is from 80H to FFH.
Special Purpose General Purpose
Data Memory Data Memory
Located Bank Capacity Bank: Address
0, 1 128×8 0: 80H~FFH
Data Memory Summary

00H

40H: EEC
Special Purpose (Bank 1)
Data Memory

7FH
80H

General Purpose
Data Memory

FFH Bank 0

Data Memory Structure

General Purpose Data Memory

All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user programing for both reading
and writing operations. By using the bit operation instructions individual bits can be set or reset
under program control giving the user a large range of flexibility for bit manipulation in the Data
Memory.

Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value “00H”.

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Bank 0 Bank 0 Bank 1

00H IAR0 40H EEC
01H MP0 41H EEA
02H IAR1 42H EED
03H MP1 43H
04H BP
05H ACC
06H PCL
07H TBLP
08H TBLH
09H TBHP
0AH STATUS
0BH SCC
0CH HIRCC
0DH
0EH
0FH RSTFC
10H INTC0
11H INTC1
12H INTC2
13H
14H PA
15H PAC
16H PAPU
17H PAWU
18H PB
19H PBC
1AH PBPU
1BH PC
1CH PCC
1DH PCPU
1EH LVPUC
1FH RSTC
20H INTEG
21H WDTC
22H LVRC
23H LVDC
24H PSC0R
25H PSC1R
26H TB0C
27H TB1C
28H PTMC0
29H PTMC1
2AH PTMDL
2BH PTMDH
2CH PTMAL
2DH PTMAH
2EH PTMRPL
2FH PTMRPH
30H
31H
32H
33H
34H
35H
36H SADOH
37H SADOL
38H SADC0
39H SADC1
3AH
3BH PAS0
3CH PAS1
3DH
3EH
3FH IFS 7FH

: Unused, read as 00H

Special Purpose Data Memory

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Special Function Register Description

Most of the Special Function Register details will be described in the relevant functional section;
however several registers require a separate description in this section.

Indirect Addressing Registers – IAR0, IAR1

The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 register together with the
MP1 register can access data from any Data Memory Bank. As the Indirect Addressing Registers are
not physically implemented, reading the Indirect Addressing Registers will return a result of “00H”
and writing to the registers will result in no operation.

Memory Pointers – MP0, MP1

Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 together with IAR1 are
used to access data from all data banks according to the BP register. Direct Addressing can only be
used with Bank 0, Bank 1 must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.

Indirect Addressing Program Example

data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ´code´
org 00h
start:
mov a, 04h ; set size of block
mov block, a
mov a, offset adres1 ; Accumulator loaded with first RAM address
mov mp0, a ; set memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by MP0
inc mp0 ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the examples shown above, no reference is made to
specific Data Memory addresses.

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Bank Pointer – BP
The Data Memory is divided into two banks, Banks 0 and Bank 1. Selecting the required Data
Memory area is achieved using the bit 0 of the Bank Pointer register. The Data Memory is initialised
to Bank 0 after a reset, except for a WDT time-out reset in the IDLE or SLEEP Mode, in which case,
the Data Memory bank remains unaffected. Directly addressing the Data Memory will always result
in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank 1
must be implemented using the indirect addressing.

• BP Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — — DMBP0
R/W — — — — — — — R/W
POR — — — — — — — 0

Bit 7~1 Unimplemented, read as “0”

Bit 0 DMBP0: Data Memory Bank selection
0: Bank 0
1: Bank 1

Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.

Program Counter Low Register – PCL

To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers – TBLP, TBHP, TBLH

These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be set before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.

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Status Register – STATUS

This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.

• STATUS Register
Bit 7 6 5 4 3 2 1 0
Name — — TO PDF OV Z AC C
R/W — — R R R/W R/W R/W R/W
POR — — 0 0 x x x x
“x”: unknown
Bit 7~6 Unimplemented, read as “0”
Bit 5 TO: Watchdog Time-out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred
Bit 4 PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instruction
Bit 3 OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2 Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero

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Bit 1 AC: Auxiliary flag

0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0 C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The “C” flag is also affected by a rotate through carry instruction.

EEPROM Data Memory

This device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a non-
volatile form of re-programmable memory, with data retention even when its power supply is
removed. By incorporating this kind of data memory, a whole new host of application possibilities
are made available to the designer. The availability of EEPROM storage allows information such
as product identification numbers, calibration values, specific user data, system setup data or other
product information to be stored directly within the product microcontroller. The process of reading
and writing data to the EEPROM memory has been reduced to a very trivial affair.

EEPROM Data Memory Structure

The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and
RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and
is therefore not directly addressable in the same way as the other types of memory. Read and Write
operations to the EEPROM are carried out in single byte operations using an address and a data
register in Bank 0 and a single control register in Bank 1.

EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same way as any
other Special Function Register. The EEC register however, being located in Bank 1, can only be
read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register,
IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory
Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H,
before any operations on the EEC register are executed.

Register Bit
Name 7 6 5 4 3 2 1 0
EEA — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC — — — — WREN WR RDEN RD
EEPROM Register List

• EEA Register
Bit 7 6 5 4 3 2 1 0
Name — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0
R/W — — R/W R/W R/W R/W R/W R/W
POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5~0 EEA5~EEA0: Data EEPROM address bit 5 ~ bit 0

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• EED Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: Data EEPROM data bit 7 ~ bit 0

• EEC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — WREN WR RDEN RD
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2 WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1 RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0 RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: 1. The WREN, WR, RDEN and RD cannot be set high at the same time in one instruction. The
WR and RD cannot be set high at the same time.
2. Ensure that the fSUB clock is stable before executing the write operation.
3. Ensure that the write operation is totally complete before changing the EEC register content.

Reading Data from the EEPROM

To read data from the EEPROM, the EEPROM address of the data to be read must first be placed in
the EEA register. Then the read enable bit, RDEN, in the EEC register must be set high to enable the
read function. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting
the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle
terminates, the RD bit will be automatically cleared to zero, after which the data can be read from
the EED register. The data will remain in the EED register until another read or write operation is
executed. The application program can poll the RD bit to determine when the data is valid for reading.

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Writing Data to the EEPROM

To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in
the EEA register and the data placed in the EED register. To initiate a write cycle, the write enable
bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR
bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed in two consecutive instruction cycles. The global interrupt bit EMI should also
first be cleared before implementing any write operations, and then set again after the write cycle
has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has
not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is
asynchronous to microcontroller system clock, a certain time will elapse before the data will have
been written into the EEPROM. Detecting when the write cycle has finished can be implemented
either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write
cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing
the user that the data has been written to the EEPROM. The application program can therefore poll
the WR bit to determine when the write cycle has ended.

Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer register, BP, will be reset to zero, which means that
Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this
adds a further measure of protection against spurious write operations. During normal program
operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against
incorrect write operations.

EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set high. If the global and EEPROM
interrupts are enabled and the stack is not full, a jump to the EEPROM Interrupt vector will take
place. When the interrupt is serviced the EEPROM interrupt flag will be automatically reset.

Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer register, BP, could be normally cleared to zero as this would inhibit access to Bank
1 where the EEPROM control register exists. Although certainly not necessary, consideration might
be given in the application program to the checking of the validity of new write data by a simple
read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,
to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device
should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally
complete. Otherwise, the EEPROM read or write operation will fail.

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Programming Examples

Reading data from the EEPROM – polling method

MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, 40H ; set memory pointer MP1
MOV MP1, A ; MP1 points to EEC register
MOV A, 01H ; set bank pointer BP
MOV BP, A
SET IAR1.1 ; set RDEN bit, enable read operations
SET IAR1.0 ; start Read Cycle - set RD bit
BACK:
SZ IAR1.0 ; check for read cycle end
JMP BACK
CLR IAR1 ; disable EEPROM read if no more read operations are required
CLR BP
MOV A, EED ; move read data to register
MOV READ_DATA, A
Note: For each read operation, the address register should be re-specified followed by setting the RD
bit high to activate a read cycle even if the target address is consecutive.

Writing Data to the EEPROM – polling method

MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, EEPROM_DATA ; user defined data
MOV EED, A
MOV A, 40H ; set memory pointer MP1
MOV MP1, A ; MP1 points to EEC register
MOV A, 01H ; set bank pointer BP
MOV BP, A
CLR EMI
SET IAR1.3 ; set WREN bit, enable write operations
SET IAR1.2 ; start Write Cycle - set WR bit – executed immediately
; after set WREN bit
SET EMI
BACK:
SZ IAR1.2 ; check for write cycle end
JMP BACK
CLR BP

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Oscillators
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator operations are selected
through a combination of configuration option and the relevant control registers.

Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. The fully integrated internal oscillators, requiring
no external components, are provided to form a wide range of both fast and slow system oscillators.
The higher frequency oscillator provides higher performance but carry with it the disadvantage of
higher power requirements, while the opposite is of course true for the lower frequency oscillator.
With the capability of dynamically switching between fast and slow system clock, the device has the
flexibility to optimize the performance/power ratio, a feature especially important in power sensitive
portable applications.
Type Name Frequency
Internal High Speed RC HIRC 2/4/8MHz
Internal Low Speed RC LIRC 32kHz
Oscillator Types

System Clock Configurations

There are two oscillator sources, one high speed oscillator and one low speed oscillator. The high
speed system clock is sourced from the internal 2/4/8MHz RC oscillator, HIRC. The low speed
oscillator is the internal 32kHz RC oscillator, LIRC. Selecting whether the low or high speed
oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC
register and the system clock can be dynamically selected.

fH

fH/2
High Speed
Oscillator fH/4

HIRC fH/8
IDLE0 Prescaler fH/16 fSYS
SLEEP
fH/32
HIRCEN
fH/64

fSUB
Low Speed
Oscillator
CKS2~CKS0
fLIRC
LIRC
IDLE2 fSUB
SLEEP

fLIRC_PTM

fLIRC/8

System Clock Configurations

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Internal High Speed RC Oscillator – HIRC

The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has three fixed frequencies of 2MHz, 4MHz and 8MHz, which is selected
using a configuration option. The HIRC1~HIRC0 bits in the HIRCC register must also be setup to
match the selected configuration option frequency. Setting up these bits is necessary to ensure that
the HIRC frequency accuracy specified in the A.C. Characterisitcs is achieved. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations
on the oscillation frequency are minimised. Note that this internal system clock option requires no
external pins for its operation.

Internal 32kHz Oscillator – LIRC

The Internal 32kHz System Oscillator is a fully integrated low frequency RC oscillator with a
typical frequency of 32kHz, requiring no external components for its implementation. The LIRC
oscillator also provides a fLIRC_PTM and a fLIRC/8 clock for some certain peripherals. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised.

Operating Modes and System Clocks

Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice versa, lower speed clocks reduce
current consumption. As Holtek has provided the device with both high and low speed clock sources
and the means to switch between them dynamically, the user can optimise the operation of their
microcontroller to achieve the best performance/power ratio.

System Clocks
The device has many different clock sources for both the CPU and peripheral function operation. By
providing the user with a wide range of clock options using register programming, a clock system
can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is
sourced from the HIRC oscillator. The low speed system clock source is sourced from the LIRC
oscillator. The other choice, which is a divided version of the high speed system oscillator has a
range of fH/2~fH/64.

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fH

fH/2
High Speed
Oscillator fH/4

HIRC fH/8
IDLE0 Prescaler fH/16 fSYS
SLEEP
HIRCEN fH/32
fH/64

fSUB
Low Speed
Oscillator
fLIRC CKS2~CKS0
LIRC
IDLE2 fSUB
SLEEP
fLIRC_PTM
PTM

fLIRC/8 fSYS TB0ON

WDT
fSYS/4
fPSC0 Time
fLIRC/8 Prescaler 0 Base 0
fLIRC_PTM
PSC0EN TB0[2:0]
CLKSEL0[1:0]

fSYS TB1ON
fSYS/4
fPSC1 Time
fLIRC/8 Prescaler 1 Base 1
fLIRC_PTM
PSC1EN TB1[2:0]
CLKSEL1[1:0]

Device Clock Configurations

Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator will
stop to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for
peripheral circuit to use, which is determined by configuring the corresponding high speed
oscillator enable control bit.

System Operation Modes

There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the FAST Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0,
IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power.

Operation Register Setting

CPU fSYS fH fSUB fLIRC
Mode FHIDEN FSIDEN CKS2~CKS0
FAST On x x 000~110 fH~fH/64 On On On
(1)
SLOW On x x 111 fSUB On/Off On On
000~110 Off
IDLE0 Off 0 1 Off On On
111 On
IDLE1 Off 1 1 xxx On On On On
000~110 On
IDLE2 Off 1 0 On Off On
111 Off
(2)
SLEEP Off 0 0 xxx Off Off Off On/Off
“x”: Don’t care
Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit
in the SLOW mode.
2. The fLIRC clock can be switched on or off which is controlled by the WDT function being enabled
or disabled in the SLEEP mode.

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FAST Mode
This is one of the main operating modes where the microcontroller has all of its functions
operational and where the system clock is provided by the high speed oscillator. This mode operates
allowing the microcontroller to operate normally with a clock source which will come from the high
speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio ranging
from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although
a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the
operating current.

SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB, which is derived from the LIRC oscillator.

SLEEP Mode
The SLEEP Mode is entered when a HALT instruction is executed and when the FHIDEN and
FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. The fSUB clock provided to the
peripheral function will also be stopped, too. However the fLIRC clock can continues to operate if the
WDT function is enabled.

IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in
the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the
CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral
functions.

IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU
will be switched off but both the high and low speed oscillators will be turned on to provide a clock
source to keep some peripheral functions operational.

IDLE2 Mode
The IDLE2 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in the
SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU
will be switched off but the high speed oscillator will be turned on to provide a clock source to keep
some peripheral functions operational.

Control Registers
The SCC and HIRCC registers are used to control the system clock and the corresponding oscillator
configurations.

Register Bit
Name 7 6 5 4 3 2 1 0
SCC CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN
HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN
System Operating Mode Control Register List

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• SCC Register
Bit 7 6 5 4 3 2 1 0
Name CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN
R/W R/W R/W R/W — — — R/W R/W
POR 1 1 1 — — — 0 0

Bit 7~5 CKS2~CKS0: System clock selection

000: fH
001: fH/2
010: fH/4
011: fH/8
100: fH/16
101: fH/32
110: fH/64
111: fSUB
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from fH or fSUB, a divided version
of the high speed system oscillator can also be chosen as the system clock source.
Bit 4~2 Unimplemented, read as “0”
Bit 1 FHIDEN: High Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the high speed oscillator is activated or stopped
when the CPU is switched off by executing an “HALT” instruction.
Bit 0 FSIDEN: Low Frequency oscillator control when CPU is switched off
0: Disable
1: Enable
This bit is used to control whether the low speed oscillator is activated or stopped
when the CPU is switched off by executing an “HALT” instruction.

• HIRCC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — HIRC1 HIRC0 HIRCF HIRCEN
R/W — — — — R/W R/W R R/W
POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3~2 HIRC1~HIRC0: HIRC frequency selection
00: 2MHz
01: 4MHz
10: 8MHz
11: 2MHz
When the HIRC oscillator is enabled or the HIRC frequency selection is changed
by application program, the clock frequency will automatically be changed after the
HIRCF flag is set to 1. It is recommended that the HIRC frequency selected by these
bits is the same as the frequency determined by the configuration option to ensure a
higer HIRC frequency accuracy spedified in the A.C. chanracteristics.
Bit 1 HIRCF: HIRC oscillator stable flag
0: HIRC unstable
1: HIRC stable
This bit is used to indicate whether the HIRC oscillator is stable or not. When the
HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be
cleared to 0 and then set to 1 after the HIRC oscillator is stable.
Bit 0 HIRCEN: HIRC oscillator enable control
0: Disable
1: Enable

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Operating Mode Switching

The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, mode switching between the FAST Mode and SLOW Mode is executed using the
CKS2~CKS0 bits in the SCC register while mode switching from the FAST/SLOW Modes to the
SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed,
whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the
FHIDEN and FSIDEN bits in the SCC register.

FAST SLOW
fSYS=fH~fH/64 fSYS=fSUB
fH on fSUB on
CPU run CPU run
fSYS on fSYS on
fSUB on fH on/off

SLEEP IDLE0
HALT instruction executed HALT instruction executed
CPU stop CPU stop
FHIDEN=0 FHIDEN=0
FSIDEN=0 FSIDEN=1
fH off fH off
fSUB off fSUB on

IDLE2 IDLE1
HALT instruction executed HALT instruction executed
CPU stop CPU stop
FHIDEN=1 FHIDEN=1
FSIDEN=0 FSIDEN=1
fH on fH on
fSUB off fSUB on

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FAST Mode to SLOW Mode Switching

When running in the FAST Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by set the
CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator
which will consume less power. Users may decide to do this for certain operations which do not
require high performance and can subsequently reduce power consumption.
The SLOW Mode system clock is sourced from the LIRC oscillator and therefore requires this
oscillator to be stable before full mode switching occurs.

FAST Mode

CKS2~CKS0 = 111

SLOW Mode

FHIDEN=0, FSIDEN=0
HALT instruction is executed

SLEEP Mode

FHIDEN=0, FSIDEN=1
HALT instruction is executed

IDLE0 Mode

FHIDEN=1, FSIDEN=1
HALT instruction is executed

IDLE1 Mode

FHIDEN=1, FSIDEN=0
HALT instruction is executed

IDLE2 Mode

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SLOW Mode to FAST Mode Switching

In the SLOW mode the system clock is derived from fSUB. When system clock is switched back to
the FAST mode from fSUB, the CKS2~CKS0 bits should be set to “000”~“110” and then the system
clock will respectively be switched to fH~fH/64.
However, if fH is not used in the SLOW mode and thus switched off, it will take some time to re-
oscillate and stabilise when switching to the FAST mode from the SLOW Mode. This is monitored
using the HIRCF bit in the HIRCC register. The time duration required for the high speed system
oscillator stabilisation is specified in the System Start Up Time Characteristics.

SLOW Mode

CKS2~CKS0 = 000~110

FAST Mode

FHIDEN=0, FSIDEN=0
HALT instruction is executed

SLEEP Mode

FHIDEN=0, FSIDEN=1
HALT instruction is executed

IDLE0 Mode

FHIDEN=1, FSIDEN=1
HALT instruction is executed

IDLE1 Mode

FHIDEN=1, FSIDEN=0
HALT instruction is executed

IDLE2 Mode

Entering the SLEEP Mode

There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT”
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to “0”. In this mode all the clocks and functions will be switched off except the WDT function.
When this instruction is executed under the conditions described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT”
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.

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Entering the IDLE0 Mode

There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the
FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be stopped and the application program will stop at the “HALT” instruction, but
the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.

Entering the IDLE1 Mode

There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register
equal to “1”. When this instruction is executed under the conditions described above, the following
will occur:
• The fH and fSUB clocks will be on but the application program will stop at the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.

Entering the IDLE2 Mode

There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT”
instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the
FSIDEN bit in the SCC register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The fH clock will be on but the fSUB clock will be off and the application program will stop at the
“HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
• The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT
function is disabled, the WDT will be cleared and then stopped.

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Standby Current Considerations

As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by
the circuit designer if the power consumption is to be minimised. Special attention must be made to
the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or
low level as any floating input pins could create internal oscillations and result in increased current
consumption. This also applies to the device which has different package types, as there may be
unbonded pins. These must either be set as outputs or if set as inputs must have pull-high resistors
connected.
Care must also be taken with the loads, which are connected to I/O pins, which are set as outputs.
These should be placed in a condition in which minimum current is drawn or connected only to
external circuits that do not draw current, such as other CMOS inputs. Also note that additional
standby current will also be required if the LIRC oscillator has enabled.
In the IDLE1 and IDLE2 Mode the high speed oscillator is on, if the peripheral function clock
source is derived from the high speed oscillator, the additional standby current will also be perhaps
in the order of several hundred micro-amps.

Wake-up
To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the
CPU will be switched off. However, when the device is woken up again, it will take a considerable
time for the original system oscillator to restart, stabilise and allow normal operation to resume.
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
“HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be set using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a pin wake-up occurs, the program will resume execution at the
instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two
possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.

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Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal clock, fLIRC/8 which is sourced from
the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32kHz and this
specified internal clock period can vary with VDD, temperature and process variations. The Watchdog
Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value
being chosen using the WS2~WS0 bits in the WDTC register.

Watchdog Timer Control Register

A single register, WDTC, controls the required time-out period as well as the enable/disable operation.

• WDTC Register
Bit 7 6 5 4 3 2 1 0
Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 1 0 1 0 0 1 0

Bit 7~3 WE4~WE0: WDT function software control

10101: Disable
01010: Enable
Other values: Reset MCU
When these bits are changed to any other values due to environmental noise the
microcontroller will be reset; this reset operation will be activated after a delay time,
tSRESET, and the WRF bit in the RSTFC register will be set high.
Bit 2~0 WS2~WS0: WDT time-out period selection
000: 28/fLIRC/8
001: 210/fLIRC/8
010: 212/fLIRC/8
011: 214/fLIRC/8
100: 215/fLIRC/8
101: 216/fLIRC/8
110: 217/fLIRC/8
111: 218/fLIRC/8
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
• RSTFC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — RSTF LVRF LRF WRF
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 x 0 0
“x”: unknown
Bit 7~4 Unimplemented, read as “0”
Bit 3 RSTF: Reset control register software reset flag
Refer to the RES Pin Reset section.
Bit 2 LVRF: LVR function reset flag
Refer to the Low Voltage Reset section.
Bit 1 LRF: LVR control register software reset flag
Refer to the Low Voltage Reset section.

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Bit 0 WRF: WDT control register software reset flag

0: Not occurred
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application program.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear instruction will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five
bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the
Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of
10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the
WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device
after a delay time, tSRESET. After power on these bits will have a value of 01010B.
WE4~WE0 Bits WDT Function
10101B Disable
01010B Enable
Any other value Reset MCU
Watchdog Timer Enable/Disable Control

Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer. The
first is a WDTC software reset, which means a certain value except 01010B and 10101B written into
the WE4~WE0 bits, the second is using the Watchdog Timer software clear instruction, the third
is via a HALT instruction. The last is an external hardware reset, which means a low level on the
external reset pin if the external reset pin function is selected by configuring the RSTC register.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT.
The maximum time-out period is when the 218 division ratio is selected. With a 32kHz LIRC
oscillator clock divided by 8 as its source clock, this will give a maximum watchdog period of
around 66s for the 218 division ratio, and a minimum timeout of 64ms for the 28 division ration.

WDTC Register WE4~WE0 bits Reset MCU

“CLR WDT” Instruction

CLR
“HALT” Instruction
RES pin reset

fLIRC/8 8-stage fLIRC/211

WDT Prescaler WDT Time-out
Divider
(211/fLIRC ~ 221/fLIRC)

WS2~WS0 8-to-1 MUX

Watchdog Timer

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Reset and Initialisation

A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply
a reset condition when the device is running. One example of this is where after power has been
applied and the device is already running, the RES line is forcefully pulled low. In such a case,
known as a normal operation reset, some of the registers remain unchanged allowing the device to
proceed with normal operation after the reset line is allowed to return high.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup.

Reset Functions
There are several ways in which a microcontroller reset can occur, through events occurring both
internally and externally.

Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.

VDD

Power-on Reset
tRSTD

SST Time-out

Power-on Reset Timing Chart

RES Pin Reset

Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.

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For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to
the RES pin should be kept as short as possible to minimise any stray noise interference.
For applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.

VDD

VDD

1N4148* 10kΩ~
100kΩ

RES
0.01µF** 300Ω*

0.1µF~1µF

VSS

Note: * It is recommended that this component is added for added ESD protection.
** It is recommended that this component is added in environments where power line noise is
significant.
External RES Circuit

Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in
the case of other resets, the Program Counter will reset to zero and program execution initiated from
this point.

0.9VDD
RES 0.4VDD

tRSTD+tSST

Internal Reset

RES Reset Timing Chart

There is an internal reset control register, RSTC, which is used to provide a reset when the device
operates abnormally due to the environmental noise interference. If the content of the RSTC register
is set to any value other than 01010101B or 10101010B, it will reset the device after a delay time,
tSRESET. After power on the register will have a value of 01010101B.
RSTC7 ~ RSTC0 Bits Reset Function
01010101B PA7
10101010B RES
Any other value Reset MCU
Internal Reset Function Control

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• RSTC Register
Bit 7 6 5 4 3 2 1 0
Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 1 0 1 0 1 0 1

Bit 7~0 RSTC7~RSTC0: Reset function control

01010101: PA7
10101010: RES
Other values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after a delay time, tSRESET, and the
RSTF bit in the RSTFC register will be set high. All resets will reset this register to
POR value except the WDT time out hardware warm reset.

• RSTFC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — RSTF LVRF LRF WRF
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 x 0 0
“x”: unknown
Bit 7~4 Unimplemented, read as “0”
Bit 3 RSTF: Reset control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the RSTC control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Bit 2 LVRF: LVR function reset flag
Refer to the Low Voltage Reset section.
Bit 1 LRF: LVR control register software reset flag
Refer to the Low Voltage Reset section.
Bit 0 WRF: WDT control register software reset flag
Refer to the Watchdog Timer Control Register section.

Low Voltage Reset – LVR

The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device and provides an MCU reset should the value fall below a certain predefined level.
If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when
changing the battery in battery powered applications, the LVR will automatically reset the device
internally and the LVRF bit in the RSTFC register will also be set high. For a valid LVR signal,
a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater
than that specified by tLVR in the LVD/LVR characteristics. If the low supply voltage state duration
does not exceed this value, the LVR will ignore the low supply voltage and will not perform a
reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the
LVS7~LVS0 bits are changed to some different values by environmental noise, the LVR will reset
the device after a delay time, tSRESET. When this happens, the LRF bit in the RSTFC register will be
set high. After power on the register will have the value of 01100110B. Note that the LVR function
will be automatically disabled when the device enters the IDLE or SLEEP mode.

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LVR

tRSTD + tSST

Internal Reset

Low Voltage Reset Timing Chart

• LVRC Register
Bit 7 6 5 4 3 2 1 0
Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 1 1 0 0 1 1 0

Bit 7~0 LVS7~LVS0: LVR Voltage Select control

01100110: 1.7V
01010101: 1.9V
00110011: 2.55V
10011001: 3.15V
10101010: 3.8V
11110000: LVR disable
Any other value: Generates MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by one of the five defined
LVR voltage values above, an MCU reset will be generated. The reset operation
will be activated after the low voltage condition keeps more than a tLVR time. In this
situation the register contents will remain the same after such a reset occurs.
Any register value, other than the five defined LVR values and disable option shown
above, will also result in the generation of an MCU reset. The reset operation will be
activated after a delay time, tSRESET. However in this situation the register contents will
be reset to the POR value.

• RSTFC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — RSTF LVRF LRF WRF
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 x 0 0
“x”: unknown
Bit 7~4 Unimplemented, read as “0”
Bit 3 RSTF: Reset control register software reset flag
Refer to the RES Pin Reset section.
Bit 2 LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set high when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to zero by the application program.
Bit 1 LRF: LVR control register software reset flag
0: Not occur
1: Occurred
This bit is set high if the LVRC register contains any non-defined LVR voltage register
values. This in effect acts like a software-reset function. This bit can only be cleared to
zero by the application program.
Bit 0 WRF: WDT control register software reset flag
Refer to the Watchdog Timer Control Register section.

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Watchdog Time-out Reset during Normal Operation

The Watchdog time-out Reset during normal operations in the FAST or SLOW mode is the same as
a hardware RES pin reset except that the Watchdog time-out flag TO will be set to “1”.

WDT Time-out

tRSTD

Internal Reset

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode

The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the System Start Up Time
Characteristics for tSST details.

WDT Time-out

tSST

Internal Reset

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF Reset Conditions
0 0 Power-on reset
u u RES or LVR reset during FAST or SLOW Mode operation
1 u WDT time-out reset during FAST or SLOW Mode operation
1 1 WDT time-out reset during IDLE or SLEEP Mode operation
“u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item Condition After Reset
Program Counter Reset to zero
Interrupts All interrupts will be disabled
WDT, Time Bases Cleared after reset, WDT begins counting
Timer Module Timer Module will be turned off
Input/Output Ports I/O ports will be set as inputs
Stack Pointer Stack Pointer will point to the top of the stack

The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that as
more than one package type exists, the table will reflect the situation for the larger package type.

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Reset RES Reset LVR Reset WDT Time-out WDT Time-out

Register
(Power On) (Normal Operation) (Normal Operation) (Normal Operation) (IDLE/SLEEP)
IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
IAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBHP ---- -xxx ---- - uuu ---- - uuu ---- -uuu ---- - uuu
STATUS --00 xxxx --uu uuuu --uu uuuu --1u uuuu - - 11 u u u u
SCC 111 - - - 0 0 111 - - - 0 0 111 - - - 0 0 111 - - - 0 0 uuu- --uu
HIRCC ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu
RSTFC ---- 0x00 ---- uuuu ---- u1uu ---- uuuu ---- uuuu
INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
INTC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
INTC2 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu
PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu
PCPU ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
LVPUC ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u
RSTC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu
INTEG ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu
WDTC 0101 0010 0101 0010 0101 0010 0101 0010 uuuu uuuu
LVRC 0 11 0 0 11 0 0 11 0 0 11 0 uuuu uuuu 0 11 0 0 11 0 uuuu uuuu
LVDC --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu
PSC0R ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu
PSC1R ---- -000 ---- -000 ---- -000 ---- -000 ---- -uuu
TB0C 0--- -000 0--- -000 0--- -000 0--- -000 u--- -uuu
TB1C 0--- -000 0--- -000 0--- -000 0--- -000 u--- -uuu
PTMC0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u---
PTMC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMDL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMDH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMAL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMAH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMRPL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTMRPH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu

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Reset RES Reset LVR Reset WDT Time-out WDT Time-out

Register
(Power On) (Normal Operation) (Normal Operation) (Normal Operation) (IDLE/SLEEP)
uuuu uuuu
(ADRFS=0)
SADOH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
---- uuuu
(ADRFS=1)
uuuu ----
(ADRFS=0)
SADOL xxxx ---- xxxx ---- xxxx ---- xxxx ----
uuuu uuuu
(ADRFS=1)
SADC0 0000 --00 0000 --00 0000 --00 0000 --00 uuuu --uu
SADC1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PAS0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PAS1 --00 00-- --00 00-- --00 00-- --00 00-- --uu uu--
IFS ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu
EEA --00 0000 --00 0000 --00 0000 --00 0000 -- uu uuuu
EED 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
EEC ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu
Note: “u” stands for unchanged
“x” stands for unknown
“-” stands for unimplemented

Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA~PC. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.

Register Bit
Name 7 6 5 4 3 2 1 0
PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0
PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0
PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0
PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0
PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0
PC — — — — — — PC1 PC0
PCC — — — — — — PCC1 PCC0
PCPU — — — — — — PCPU1 PCPU0
LVPUC — — — — — — — LVPU
“—”: Unimplemented, read as “0”
I/O Logic Function Register List

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Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as a digital input have the capability of being connected to an internal pull-high resistor.
These pull-high resistors are selected using the LVPUC and PxPU registers, and are implemented
using weak PMOS transistors. The PxPU register is used to determine whether the pull-high
function is enabled or not while the LVPUC register is used to select the pull-high resistor value for
low voltage power supply applications.
Note that the pull-high resistor can be controlled by the relevant pull-high control register only when
the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high
resistors cannot be enabled.
Not that the LVPU bit in the LVPUC register is only available when the corresponding pin pull-high
function is enabled. If the pull-high function is disabled, the LVPU bit has no effect on selecting the
pull-high resistor value.

• PxPU Register
Bit 7 6 5 4 3 2 1 0
Name PxPU7 PxPU6 PxPU5 PxPU4 PxPU3 PxPU2 PxPU1 PxPU0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

PxPUn: I/O Port x Pin pull-high function control

0: Disable
1: Enable
The PxPUn bit is used to control the pin pull-high function. Here the “x”can be A, B and C.
However, the actual available bits for each I/O Port may be different.

• LVPUC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — — LVPU
R/W — — — — — — — R/W
POR — — — — — — — 0

Bit 7~1 Unimplemented, read as “0”

Bit 0 LVPU: Pull-high resistor selection for low voltage power supply
0: All pin pull-high resistors are 60kΩ @ 3V
1: All pin pull-high resistors are 15kΩ @ 3V

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Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
Note that the wake-up function can be controlled by the wake-up control registers only when the pin
is selected as a general purpose input and the MCU enters the IDLE or SLEEP mode.

• PAWU Register
Bit 7 6 5 4 3 2 1 0
Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 PAWU7~PAWU0: PA7~PA0 wake-up function control

0: Disable
1: Enable

I/O Port Control Registers

Each I/O port has its own control register known as PAC~PCC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a “1”. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a “0”,
the I/O pin will be set as a CMOS output. If the pin is currently set as an output, instructions can still
be used to read the output register. However, it should be noted that the program will in fact only
read the status of the output data latch and not the actual logic status of the output pin.

• PxC Register
Bit 7 6 5 4 3 2 1 0
Name PxC7 PxC6 PxC5 PxC4 PxC3 PxC2 PxC1 PxC0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1

PxCn: I/O Port x Pin type selection

0: Output
1: Input
The PxCn bit is used to control the pin type selection. Here the “x”can be A, B and C.
However, the actual available bits for each I/O Port may be different.

Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the
desired function of the multi-function I/O pins is selected by a series of registers via the application
program control.

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Pin-shared Function Selection Registers

The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. The device includes Port A Output Function Selection
register “n”, labeled as PASn, and Input Function Selection register, labeled as IFS, which can select
the desired functions of the multi-function pin-shared pins.
The most important point to note is to make sure that the desired pin-shared function is properly
selected and also deselected. For most pin-shared functions, to select the desired pin-shared function,
the pin-shared function should first be correctly selected using the corresponding pin-shared control
register. After that the corresponding peripheral functional setting should be configured and then the
peripheral function can be enabled. However, a special point must be noted for some digital input
pins, such as INT0 and PTCK, which share the same pin-shared control configuration with their
corresponding general purpose I/O functions when setting the relevant pin-shared control bit fields.
To select this pin function, in addition to the necessary pin-shared control and peripheral functional
setup aforementioned, they must also be set as an input by setting the corresponding bit in the I/O
port control register. To correctly deselect the pin-shared function, the peripheral function should
first be disabled and then the corresponding pin-shared function control register can be modified to
select other pin-shared functions.

Register Bit
Name 7 6 5 4 3 2 1 0
PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00
PAS1 — — PAS15 PAS14 PAS13 PAS12 — —
IFS — — — — PTPIS PTCKS INT1S INT0S
Pin-shared Function Selection Register List

• PAS0 Register
Bit 7 6 5 4 3 2 1 0
Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~6 PAS07~PAS06: PA3 Pin-Shared function selection

00: PA3/PTCK/INT0
01: PA3/PTCK/INT0
10: PA3/PTCK/INT0
11: AN3
Bit 5~4 PAS05~PAS04: PA2 Pin-Shared function selection
00: PA2
01: PA2
10: PA2
11: AN2
Bit 3~2 PAS03~PAS02: PA1 Pin-Shared function selection
00: PA1
01: PA1
10: AN1
11: VREF
Bit 1~0 PAS01~PAS00: PA0 Pin-Shared function selection
00: PA0
01: PA0
10: PA0
11: AN0

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• PAS1 Register
Bit 7 6 5 4 3 2 1 0
Name — — PAS15 PAS14 PAS13 PAS12 — —
R/W — — R/W R/W R/W R/W — —
POR — — 0 0 0 0 — —

Bit 7~6 Unimplemented, read as “0”

Bit 5~4 PAS15~PAS14: PA6 Pin-Shared function selection
00: PA6
01: PA6
10: PA6
11: PTP
Bit 3~2 PAS13~PAS12: PA5 Pin-Shared function selection
00: PA5/PTPI
01: PA5/PTPI
10: PA5/PTPI
11: PTPB
Bit 1~0 Unimplemented, read as “0”

• IFS Register
Bit 7 6 5 4 3 2 1 0
Name — — — — PTPIS PTCKS INT1S INT0S
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 PTPIS: PTPI input source pin selection
0: PA4
1: PA5
Bit 2 PTCKPS: PTCK input source pin selection
0: PA3
1: PB4
Bit 1 INT1S: INT1 input source pin selection
0: PA4
1: PB3
Bit 1 INT0S: INT0 input source pin selection
0: PA3
1: PB2

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I/O Pin Structures

The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact
logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to
assist with the functional understanding of the I/O logic function. The wide range of pin-shared
structures does not permit all types to be shown.

VDD

Pull-high
Control Bit Register Weak
Select Pull-up
Data Bus D Q

Write Control Register CK Q

S
Chip Reset
I/O pin
Read Control Register
Data Bit
D Q
Write Data Register CK Q
S
M
U
X
Read Data Register

System Wake-up wake-up Select PA only

Logic Function Input/Output Structure

Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pull-
high selections have been chosen. If the port control registers are then programmed to set some
pins as outputs, these output pins will have an initial high output value unless the associated port
data registers are first programmed. Selecting which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct values into the appropriate port control register or by
programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up function. When the device is in the SLEEP
or IDLE Mode, various methods are available to wake the device up. One of these is a high to low
transition of any of the Port A pins. Single or multiple pins on Port A can be set to have this function.

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Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control
and measure time. To implement time related functions each device includes a Timer Module,
abbreviated to the name TM. The TM is a multi-purpose timing unit and serves to provide operations
such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as
being the functional unit for the generation of PWM signals. The TM has two individual interrupts.
The addition of input and output pins for the TM ensures that users are provided with timing units
with a wide and flexible range of features.

Introduction
The device contains one Periodic Type TM having a reference name of PTM. The general features to
the Periodic TM will be described in this section and the detailed operation will be described in the
Periodic type TM section. The main features of the PTM are summarised in the accompanying table.
Function PTM
Timer/Counter √
Input Capture √
Compare Match Output √
PWM Output √
Single Pulse Output √
PWM Alignment Edge
PWM Adjustment Period & Duty Duty or Period

TM Function Summary

TM Operation
The Periodic type TM offers a diverse range of functions, from simple timing operations to
PWM signal generation. The key to understanding how the PTM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a PTM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the PTM output pin. The internal PTM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.

TM Clock Source
The clock source which drives the main counter in the PTM can originate from various sources. The
selection of the required clock source is implemented using the PTCK2~PTCK0 bits in the PTM
control registers. The clock source can be a ratio of the system clock fSYS or the fLIRC_PTM, fLIRC/8
clock source or the external PTCK pin. The PTCK pin clock source is used to allow an external
signal to drive the PTM as an external clock source or for event counting.

TM Interrupts
The Periodic type TM has two internal interrupts, one for each of the internal comparator A or
comparator P, which generate a PTM interrupt when a compare match condition occurs. When a
PTM interrupt is generated it can be used to clear the counter and also to change the state of the
PTM output pin.

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TM External Pins
The Periodic type TM has two input pins, with the label PTCK and PTPI respectively. The PTM
input pin, PTCK, is essentially a clock source for the PTM and is selected using the PTCK2~PTCK0
bits in the PTMC0 register. This external PTM input pin allows an external clock source to drive the
internal PTM. The PTCK input pin can be chosen to have either a rising or falling active edge. The
PTCK pin is also used as the external trigger input pin in single pulse output mode.
The other PTM input pin, PTPI, is the capture input whose active edge can be a rising edge, a
falling edge or both rising and falling edges and the active edge transition type is selected using the
PTIO1~PTIO0 bits in the PTMC1 register. There is another capture input, PTCK, for PTM capture
input mode, which can be used as the external trigger input source except the PTPI pin.
The PTM has two output pins with the label PTP and PTPB. The PTPB pin outputs the inverted
signal of the PTP. When the PTM is in the Compare Match Output Mode, these pins can be
controlled by the PTM to switch to a high or low level or to toggle when a compare match situation
occurs. The external PTP and PTPB output pins are also the pins where the PTM generates the
PWM output waveform.
As the PTM input and output pins are pin-shared with other functions, the PTM input and output
functions must first be selected using the relevant pin-shared function selection bits described in the
Pin-shared Function section as well as the functional control bit in the Periodic Type TM section.
PTM
Input Output
PTCK, PTPI PTP, PTPB
TM External Pins

Clock/capture input
PTCK
CCR capture input
PTPI
PTM

CCR output
PTP
PTPB

PTM Function Pin Block Diagram

Programming Considerations
The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low
and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be
accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in
a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its
related low byte only takes place when a write or read operation to its corresponding high byte is
executed.
As the CCRA and CCRP registers are implemented in the way shown in the following diagram and
accessing these register pairs is carried out in a specific way as described above, it is recommended
to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named PTMAL and
PTMRPL, using the following access procedures. Accessing the CCRA or CCRP low byte registers
without following these access procedures will result in unpredictable values.

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PTM Counter Register (Read only)

PTMDL PTMDH

8-bit Buffer

PTMAL PTMAH

PTM CCRA Register (Read/Write)

PTMRPL PTMRPH

PTM CCRP Register (Read/Write)

Data Bus

The following steps show the read and write procedures:

• Writing Data to CCRA or CCRP
♦ Step 1. Write data to Low Byte PTMAL or PTMRPL
– Note that here data is only written to the 8-bit buffer.
♦ Step 2. Write data to High Byte PTMAH or PTMRPH
– Here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers, CCRA or CCRP
♦ Step 1. Read data from the High Byte PTMDH, PTMAH or PTMRPH
– Here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦ Step 2. Read data from the Low Byte PTMDL, PTMAL or PTMRPL
– This step reads data from the 8-bit buffer.

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Periodic Type TM – PTM

The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
be controlled with two external input pins and can drive two external output pins.
PTM Core PTM Input Pin PTM Output Pin
16-bit PTM PTCK, PTPI PTP, PTPB

CCRP

Comparator P Match
16-bit Comparator P PTMPF Interrupt
fSYS/4 000
fSYS 001 PTOC
b0~b15
fSYS/16 010
fSYS/64 011 Counter Clear 0 Output Polarity Pin PTP
16-bit Count-up Counter
fLIRC_PTM 100 1 Control Control Control PTPB
fLIRC/8 101 PTON PTCCLR
110 PTPAU b0~b15 PTM1, PTM0
Pin PTPOL PAS1
PTCK 111 PTIO1, PTIO0
Control
Comparator A Match
PTCK2~PTCK0 16-bit Comparator A PTMAF Interrupt
PAS0 IFS
PTIO1, PTIO0

Edge 0 PTPI
CCRA
Detector 1
PTCAPTS

Note: PTPB is the inverted signal of PTP.

16-bit Periodic Type TM Block Diagram

Periodic TM Operation
The Periodic Type TM core is a 16-bit count-up counter which is driven by a user selectable internal
or external clock source. There are also two internal comparators with the names, Comparator A
and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA
registers. The CCRP and CCRA comparators are 16-bit wide whose value is respectively compared
with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the PTON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pins. All operating setup conditions
are selected using relevant internal registers.

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Periodic Type TM Register Description

Overall operation of the Periodic Type TM is controlled using a series of registers. A read only
register pair exists to store the internal counter 16-bit value, while two read/write register pairs exist
to store the internal 16-bit CCRA value and CCRP value. The remaining two registers are control
registers which set the different operating and control modes.

Register Bit
Name 7 6 5 4 3 2 1 0
PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — —
PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR
PTMDL D7 D6 D5 D4 D3 D2 D1 D0
PTMDH D15 D14 D13 D12 D11 D10 D9 D8
PTMAL D7 D6 D5 D4 D3 D2 D1 D0
PTMAH D15 D14 D13 D12 D11 D10 D9 D8
PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0
PTMRPH PTRP15 PTRP14 PTRP13 PTRP12 PTRP11 PTRP10 PTRP9 PTRP8
16-bit Periodic TM Register List

• PTMC0 Register
Bit 7 6 5 4 3 2 1 0
Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — —
R/W R/W R/W R/W R/W R/W — — —
POR 0 0 0 0 0 — — —

Bit 7 PTPAU: PTM counter pause control

0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the PTM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes to
a low value again.
Bit 6~4 PTCK2~PTCK0: PTM counter clock selection
000: fSYS/4
001: fSYS
010: fSYS/16
011: fSYS/64
100: fLIRC_PTM
101: fLIRC/8
110: PTCK rising edge clock
111: PTCK falling edge clock
These three bits are used to select the clock source for the PTM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS
is the system clock, while fLIRC_PTM or fLIRC/8 is provided by the LIRC oscillator, the
details of which can be found in the oscillator section.
Bit 3 PTON: PTM counter on/off control
0: Off
1: On
This bit controls the overall on/off function of the PTM. Setting the bit high enables
the counter to run, clearing the bit disables the PTM. Clearing this bit to zero will
stop the counter from counting and turn off the PTM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again.

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If the PTM is in the Compare Match Output Mode, PWM output Mode or Single Pulse
Output Mode then the PTM output pin will be reset to its initial condition, as specified
by the PTOC bit, when the PTON bit changes from low to high.
Bit 2~0 Unimplemented, read as “0”

• PTMC1 Register
Bit 7 6 5 4 3 2 1 0
Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~6 PTM1~PTM0: PTM operating mode selection

00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Output Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits are used to set the required operating mode for the PTM. To ensure reliable
operation the PTM should be switched off before any changes are made to the PTM1
and PTM0 bits. In the Timer/Counter Mode, the PTM output pin state is undefined.
Bit 5~4 PTIO1~PTIO0: PTM external pin (PTP or PTPI/PTCK) function selection
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Output Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of PTPI or PTCK
01: Input capture at falling edge of PTPI or PTCK
10: Input capture at falling/rising edge of PTPI or PTCK
11: Input capture disabled
Timer/Counter Mode
Unused
These two bits are used to determine how the PTM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the PTM is running.
In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the
PTM output pin changes state when a compare match occurs from the Comparator A.
The PTM output pin can be set to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the bits are both zero,
then no change will take place on the output. The initial value of the PTM output pin
should be set using the PTOC bit in the PTMC1 register. Note that the output level
requested by the PTIO1 and PTIO0 bits must be different from the initial value setup
using the PTOC bit otherwise no change will occur on the PTM output pin when a
compare match occurs. After the PTM output pin changes state, it can be reset to its
initial level by changing the level of the PTON bit from low to high.
In the PWM Output Mode, the PTIO1 and PTIO0 bits determine how the PTM
output pin changes state when a certain compare match condition occurs. The PWM
output function is modified by changing these two bits. It is necessary to only change
the values of the PTIO1 and PTIO0 bits only after the TM has been switched off.
Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed

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when the PTM is running.

Bit 3 PTOC: PTM PTP output control
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the PTM output pin. Its operation depends upon
whether PTM is being used in the Compare Match Output Mode or in the PWM
Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/
Counter Mode. In the Compare Match Output Mode it determines the logic level of
the PTM output pin before a compare match occurs. In the PWM Output Mode it
determines if the PWM signal is active high or active low. In the Single Pulse Output
Mode it determines the logic level of the PTM output pin when the PTON bit changes
from low to high.
Bit 2 PTPOL: PTM PTP output polarity control
0: Non-invert
1: Invert
This bit controls the polarity of the PTP output pin. When the bit is set high the PTM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
PTM is in the Timer/Counter Mode.
Bit 1 PTCAPTS: PTM capture trigger source selection
0: From PTPI pin
1: From PTCK pin
Bit 0 PTCCLR: PTM counter clear condition selection
0: PTM Comparator P match
1: PTM Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PTCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not
used in the PWM Output Mode, Single Pulse Output Mode or Capture Input Mode.

• PTMDL Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: PTM Counter Low Byte Register bit 7 ~ bit 0
PTM 16-bit Counter bit 7 ~ bit 0

• PTMDH Register
Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D12 D11 D10 D9 D8
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0

Bit 7~0 D15~D8: PTM Counter High Byte Register bit 7 ~ bit 0
PTM 16-bit Counter bit 15 ~ bit 8

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• PTMAL Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: PTM CCRA Low Byte Register bit 7 ~ bit 0
PTM 16-bit CCRA bit 7 ~ bit 0

• PTMAH Register
Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 D15~D8: PTM CCRA High Byte Register bit 7 ~ bit 0
PTM 16-bit CCRA bit 15 ~ bit 8

• PTMRPL Register
Bit 7 6 5 4 3 2 1 0
Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0
PTM 16-bit CCRP bit 7 ~ bit 0

• PTMRPH Register
Bit 7 6 5 4 3 2 1 0
Name PTRP15 PTRP14 PTRP13 PTRP12 PTRP11 PTRP10 PTRP9 PTRP8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~0 PTRP15~PTRP8: PTM CCRP High Byte Register bit 7 ~ bit 0
PTM 16-bit CCRP bit 15 ~ bit 8

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Periodic Type TM Operating Modes

The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.

Compare Match Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to “00” respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be cleared to zero.
If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 16-bit, FFFF
Hex, value, however here the PTMAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the PTM output pin, will change
state. The PTM output pin condition however only changes state when a PTMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM
output pin. The way in which the PTM output pin changes state are determined by the condition of
the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the
PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the PTM output pin, which is configured
after the PTON bit changes from low to high, is configured using the PTOC bit. Note that if the
PTIO1 and PTIO0 bits are zero then no pin change will take place.

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Counter Value Counter overflow

PTCCLR = 0; PTM [1:0] = 00
CCRP > 0
CCRP=0
Counter cleared by CCRP value
0xFFFF
CCRP > 0 Counter
Resume Restart
CCRP
Pause Stop
CCRA

Time

PTON

PTPAU

PTPOL

CCRP Int.
Flag PTMPF

CCRA Int.
Flag PTMAF

PTM O/P Pin

Output not affected by
PTMAF flag. Remains High Output Inverts
Output pin set Output Toggle with until reset by PTON bit when PTPOL is high
to initial Level PTMAF flag
Low if PTOC=0 Output Pin
Here PTIO [1:0] = 11 Note PTIO [1:0] = 10 Reset to Initial value
Toggle Output select Active High Output select Output controlled by
other pin-shared function

Compare Match Output Mode – PTCCLR=0

Note: 1. With PTCCLR=0 a Comparator P match will clear the counter

2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to its initial state by a PTON bit rising edge

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Counter Value PTCCLR = 1; PTM [1:0] = 00

CCRA > 0 Counter cleared by CCRA value CCRA = 0

Counter overflow
0xFFFF
Resume CCRA=0
CCRA
Pause Stop Counter Restart

CCRP

Time

PTON

PTPAU

PTPOL
No PTMAF flag
generated on
CCRA Int. CCRA overflow
Flag PTMAF

CCRP Int.
Flag PTMPF

PTMPF not Output does

generated not change
PTM O/P Pin
Output not affected by
PTMAF flag. Remains High Output Inverts
Output Toggle with
Output pin set until reset by PTON bit when PTPOL is high
PTMAF flag Output Pin
to initial Level Reset to Initial value
Low if PTOC=0 Here PTIO [1:0] = 11 Note PTIO [1:0] = 10
Active High Output select Output controlled by
Toggle Output select other pin-shared function

Compare Match Output Mode – PTCCLR=1

Note: 1. With PTCCLR=1 a Comparator A match will clear the counter

2. The PTM output pin is controlled only by the PTMAF flag
3. The output pin is reset to its initial state by a PTON bit rising edge
4. A PTMPF flag is not generated when PTCCLR=1

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Timer/Counter Mode
To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “11” respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM
output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the PTM output pins are not used in
this mode, the pins can be used as normal I/O pins or other pin-shared functions.

PWM Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “10” respectively.
The PWM function within the PTM is useful for applications which require functions such as motor
control, heating control, illumination control etc. By providing a signal of fixed frequency but of
varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM Output Mode, the PTCCLR bit has no effect on the
PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform,
one register is used to clear the internal counter and thus control the PWM waveform frequency,
while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle
can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to
select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to
enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit
is used to reverse the polarity of the PWM output waveform.

• 16-bit PTM, PWM Output Mode, Edge-aligned Mode

CCRP 1~65535 0
Period 1~65535 65535
Duty CCRA

If fSYS=8MHz, PTM clock source select fSYS/4, CCRP=512 and CCRA=128,

The PTM PWM output frequency=(fSYS/4)/512=fSYS/2048≈4kHz, duty=128/512=25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.

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Counter Value PTM [1:0] = 10

Counter cleared by
CCRP
Counter Reset when
PTON returns high
CCRP
Counter Stop if
Pause Resume
PTON bit low
CCRA

Time

PTON

PTPAU

PTPOL

CCRA Int.
Flag PTMAF

CCRP Int.
Flag PTMPF

PTM O/P Pin

(PTOC=1)
PTM O/P Pin
(PTOC=0)

PWM Duty Cycle PWM resumes

set by CCRA operation
Output controlled by
other pin-shared function Output Inverts
When PTPOL = 1
PWM Period set by CCRP

PWM Output Mode

Note: 1. Counter cleared by CCRP

2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PTIO[1:0]=00 or 01
4. The PTCCLR bit has no influence on PWM operation

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Single Pulse Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “10” respectively
and also the PTIO1 and PTIO0 bits should be set to “11” respectively. The Single Pulse Output
Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which
can be implemented using the application program. However in the Single Pulse Output Mode, the
PTON bit can also be made to automatically change from low to high using the external PTCK pin,
which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the
counter will start running and the pulse leading edge will be generated. The PTON bit should remain
high when the pulse is in its active state. The generated pulse trailing edge will be generated when
the PTON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PTON bit and
thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to
control the pulse width. A compare match from Comparator A will also generate a PTM interrupt.
The counter can only be reset back to zero when the PTON bit changes from low to high when the
counter restarts. In the Single Pulse Output Mode CCRP is not used. The PTCCLR bit is not used in
this Mode.

CCRA CCRA
Leading Edge Trailing Edge
S/W Command S/W Command
SET“PTON” PTON bit PTON bit CLR“PTON”
or or
0 1 1 0
PTCK Pin CCRA Compare
Transition Match

PTP Output Pin

Pulse Width = CCRA Value

Single Pulse Generation

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Counter Value PTM [1:0] = 10; PTIO [1:0] = 11

Counter stopped by
CCRA
Counter Reset when
PTON returns high
CCRA
Resume Counter Stops by
Pause software
CCRP

Time

PTON
Auto. set by
Software Cleared by PTCK pin Software
Trigger CCRA match Software Software Software Trigger
Trigger Trigger Clear
PTCK pin
PTCK pin
PTPAU Trigger

PTPOL

No CCRP Interrupts
CCRP Int. generated
Flag PTMPF

CCRA Int.
Flag PTMAF

PTM O/P Pin

(PTOC=1)

PTM O/P Pin

(PTOC=0)
Pulse Width Output Inverts
set by CCRA when PTPOL = 1

Single Pulse Output Mode

Note: 1. Counter stopped by CCRA

2. CCRP is not used
3. The pulse is triggered by the PTCK pin or by setting the PTON bit high
4. A PTCK pin active edge will automatically set the PTON bit high
5. In the Single Pulse Output Mode, PTIO[1:0] must be set to “11” and cannot be changed

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Capture Input Mode

To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to “01” respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the PTPI or PTCK pin which is selected using the PTCAPTS bit in the PTMC1 register.
The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges;
the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register.
The counter is started when the PTON bit changes from low to high which is initiated using the
application program.
When the required edge transition appears on the PTPI or PTCK pin the present value in the counter
will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events
occur on the PTPI or PTCK pin, the counter will continue to free run until the PTON bit changes
from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this
way the CCRP value can be used to control the maximum counter value. When a CCRP compare
match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of
overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths.
The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising
edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture
operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be
noted that the counter will continue to run.
As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the
Capture Input Mode. This is because if the pin is set as an output, then any transitions on this pin
may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not
used in this Mode.

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Counter Value PTM [1:0] = 01

Counter cleared by
CCRP
Counter Counter
Stop Reset
CCRP

YY Resume
Pause

XX

Time

PTON

PTPAU
Active Active
Active edge
edge edge
PTM Capture pin
PTPI or PTCK

CCRA Int.
Flag PTMAF

CCRP Int.
Flag PTMPF

CCRA XX YY XX YY
Value

PTIO [1:0] 00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture
Value

Capture Input Mode

Note: 1. PTM[1:0]=01 and active edge set by the PTIO[1:0] bits

2. A PTM Capture input pin active edge transfers the counter value to CCRA
3. PTCCLR bit not used
4. No output function – PTOC and PTPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero

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Analog to Digital Converter

The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.

A/D Converter Overview

This device contains a multi-channel analog to digital converter which can directly interface
to external analog signals, such as that from sensors or other control signals and convert these
signals directly into a 12-bit digital value. The external or internal analog signal to be converted is
determined by the SAINS2~SAINS0 bits together with the SACS1~SACS0 bits. When the external
analog signal is to be converted, the corresponding pin-shared control bits should first be properly
configured and then desired external channel input should be selected using the SAINS2~SAINS0
and SACS1~SACS0 bits. Note that when the internal analog signal is to be converted, some pin-
shared control bits should also be properly configured except the SAINS and SACS bit fields to
avoid external channel input. More detailed information about the A/D input signal is described in
the “A/D Converter Control Registers” and “A/D Converter Input Signals” sections respectively.
External Input Channels Internal Signal A/D Channel Select Bits
SAINS2~SAINS0,
4: AN0~AN3 1: VBG
SACS1~SACS0

The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.

VDD
fSYS

Pin-shared SACKS2~ ÷ 2N
Selection SACS1~SACS0 SACKS0 (N=0~7) ADCEN

VSS
AN0 ADRFS
A/D Clock

AN1 SADOL
A/D Converter A/D Data
SADOH Registers
AN2

AN3 A/D Reference Voltage

START ADBZ ADCEN

SAINS2~SAINS0 SAVRS1~SAVRS0

VDD
VBG
VREF

Pin-shared
Selection

A/D Converter Structure

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A/D Converter Register Description

Overall operation of the A/D converter is controlled using four registers. A read only register pair
exists to store the A/D converter data 12-bit single value. The remaining two registers are control
registers which configures the operating and control function of the A/D converter.

Register Bit
Name 7 6 5 4 3 2 1 0
SADOL
D3 D2 D1 D0 — — — —
(ADRFS=0)
SADOL
D7 D6 D5 D4 D3 D2 D1 D0
(ADRFS=1)
SADOH
D11 D10 D9 D8 D7 D6 D5 D4
(ADRFS=0)
SADOH
— — — — D11 D10 D9 D8
(ADRFS=1)
SADC0 START ADBZ ADCEN ADRFS — — SACS1 SACS0
SADC1 SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0
A/D Converter Register List

A/D Converter Data Registers – SADOL, SADOH

As the internal A/D converter provides a 12-bit digital conversion value, it requires two data
registers to store the converted value. These are a high byte register, known as SADOH, and a low
byte register, known as SADOL. After the conversion process takes place, these registers can be
directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the
16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit
in the SADC0 register, as shown in the accompanying table. Any unused bits will be read as zero.
Note that A/D data registers contents will be unchanged if the A/D converter is disabled.
SADOH SADOL
ADRFS
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A/D Converter Data Registers

A/D Converter Control Registers – SADC0, SADC1

To control the function and operation of the A/D converter, two control registers known as SADC0
and SADC1 are provided. These 8-bit registers define functions such as the selection of which
analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock
source as well as controlling the start function and monitoring the A/D converter busy status. As the
device contains only one actual analog to digital converter hardware circuit, each of the external
or internal analog signal inputs must be routed to the converter. The SAINS2~SAINS0 bits in the
SADC1 register are used to determine that the analog signal to be converted comes from the internal
analog signal or external analog channel input. The SACS1~SACS0 bits in the SADC0 register are
used to determine which external channel input is selected to be converted.
The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog
inputs for the A/D converter input and which pins are not to be used as the A/D converter input.
When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-
shared function will be removed. In addition, any internal pull-high resistor connected to the pin will
be automatically removed if the pin is selected to be an A/D converter input.

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• SADC0 Register
Bit 7 6 5 4 3 2 1 0
Name START ADBZ ADCEN ADRFS — — SACS1 SACS0
R/W R/W R R/W R/W — — R/W R/W
POR 0 0 0 0 — — 0 0

Bit 7 START: Start the A/D conversion

0 → 1 → 0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
Bit 6 ADBZ: A/D converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
Bit 5 ADCEN: A/D converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable the
A/D converter. If the bit is cleared to zero, then the A/D converter will be switched off
reducing the device power consumption. When the A/D converter function is disabled,
the contents of the A/D data register pair known as SADOH and SADOL will be
unchanged.
Bit 4 ADRFS: A/D converter data format selection
0: A/D converter data format → SADOH = D[11:4]; SADOL = D[3:0]
1: A/D converter data format → SADOH = D[11:8]; SADOL = D[7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D data register section.
Bit 3~2 Unimplemented, read as “0”
Bit 1~0 SACS1~SACS0: A/D converter external analog channel input selection
00: AN0
01: AN1
10: AN2
11: AN3

• SADC1 Register
Bit 7 6 5 4 3 2 1 0
Name SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7~5 SAINS2~SAINS0: A/D converter input signal selection

000: External input – External analog channel input, ANn
001: Internal input – Internal Bandgap reference voltage, VBG
010~100: Undefined, connected to ground
101~111: External input – External analog channel input, ANn
Care must be taken if the SAINS2~SAINS0 bits are set to “001” to select the internal
analog signal to be coverted. When the internal bandgap reference voltage is selected
to be converted, the external input pin must never be selected as the A/D input signal
by properly configuring the corresponding pin-shared function control bits. Otherwise,
the external channel input will be connected together with the internal analog signal,
which will result in unpredictable situations such as an irreversible damage.

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Bit 4~3 SAVRS1~SAVRS0: A/D converter reference voltage selection

00: External VREF pin
01: Internal A/D converter power supply, VDD
1x: External VREF pin
These bits are used to select the A/D converter reference voltage. Care must be taken
if the SAVRS1~SAVRS0 bits are set to “01” to select the A/D converter power supply
as the reference voltage source. In this condition, the VREF pin can not be configured
as the reference voltage input by properly configuring the corresponding pin-shared
function control bits. Otherwise, the external input voltage on the VREF pin will be
connected together with the A/D power supply voltage.
Bit 2~0 SACKS2~SACKS0: A/D conversion clock source selection
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: fSYS/128
These three bits are used to select the clock source for the A/D converter.

A/D Converter Reference Voltage

The reference voltage supply to the A/D converter can be supplied from the internal A/D power
supply voltage, VDD, or from an external reference source supplied on pin VREF. The desired
selection is made using the SAVRS1 and SAVRS0 bits. When the SAVRS bit field is set to “01”, the
A/D converter reference voltage will come from the power supply voltage. Otherwise, if the SAVRS
bit field is set to other value except “01”, the A/D converter reference voltage will come from the
VREF pin. As the VREF pin is pin-shared with other functions, when the VREF pin is selected
as the reference voltage supply pin, the VREF pin-shared function control bits should be properly
configured to disable other pin functions. However, if the A/D power supply voltage is selected as
the reference voltage, the VREF pin must not be configured as the reference voltage input function
to avoid the internal connection between the VREF pin and the power supply. The analog input
values must not be allowed to exceed the selected reference voltage.
SAVRS[1:0] Reference Description
00, 10, 11 VREF pin External A/D converter reference pin VREF
01 VDD Internal A/D converter power supply voltage
A/D Converter Reference Voltage Selection

A/D Converter Input Signals

All the external A/D analog channel input pins are pin-shared with the I/O pins as well as other
functions. The corresponding control bits for each A/D external input pin in the PAS0 register
determine whether the input pins are set as A/D converter analog inputs or whether they have other
functions. If the pin is set to be as an A/D analog channel input, the original pin functions will be
disabled. In this way, pins can be changed under program control to change their function between
A/D inputs and other functions. All pull high resistors, which are set through register programming,
will be automatically disconnected if the pins are set as A/D inputs. Note that it is not necessary
to first set the A/D pin as an input in the port control register to enable the A/D input as when the
pin-shared function control bits enable an A/D input, the status of the port control register will be
overridden.

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If the SAINS2~SAINS0 bits are set to “000” or “100~111”, the external analog channel input is
selected to be converted and the SACS1~SACS0 bits can determine which actual external channel
is selected to be converted. If the SAINS2~SAINS0 bits are set to “001”, the VBG voltage is selected
to be converted. Note that if the internal analog signal is selected to be converted, the external input
channel determined by the SACS1~SACS0 bits must be switched to other pin-shared funcions by
properly configuring the relevant pin-shared function control bits.
SAINS[2:0] SACS[1:0] Input Signals Description
000, 101~111 00~11 AN0~AN3 External channel analog input ANn
001 — VBG Internal bandgap reference voltage
010~100 — GND Connected to ground
A/D Converter Input Signal Selection

A/D Converter Operation

The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller
sets this bit from low to high and then low again, an analog to digital conversion cycle will be
initiated.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an
A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be
cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the associated interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the
microcontroller can poll the ADBZ bit in the SADC0 register to check whether it has been cleared
as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by
the system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the A/D clock
source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK,
is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, if the system
clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or
111. Doing so will give A/D clock periods that are less than the minimum A/D clock period or larger
than the maximum A/D clock period, which may result in inaccurate A/D conversion values. Refer
to the following table for examples, where values marked with an asterisk * show where special care
must be taken.
A/D Clock Period (tADCK)
SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0] SACKS[2:0]
fSYS = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111
(fSYS) (fSYS/2) (fSYS/4) (fSYS/8) (fSYS/16) (fSYS/32) (fSYS/64) (fSYS/128)
1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *
2MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *
4MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs *
8MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs *
A/D Clock Period Examples

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Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When
the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if
no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be
consumed. In power conscious applications it is therefore recommended that the ADCEN is set low
to reduce power consumption when the A/D converter function is not being used.

Conversion Rate and Timing Diagram

A complete A/D conversion contains two parts, data sampling and data conversion. A total of 16 A/D
clock cycles for an external input A/D conversion which is defined as tADC are necessary.
Maximum single A/D conversion rate = A/D clock period/16
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period.

tON2ST

ADCEN off on off on

A/D sampling time A/D sampling time

START

Start of A/D conversion Start of A/D conversion Start of A/D conversion

ADBZ
End of A/D End of A/D
conversion conversion

SACS[1:0] 11B 10B 00B 01B

(SAINS[2:0]=000)

A/D channel tADC tADC tADC

switch A/D conversion time A/D conversion time A/D conversion time

A/D Conversion Timing – External Channel Input

Summary of A/D Conversion Steps

The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by correctly programming bits SACKS2~SACKS0 in
the SADC1 register.
• Step 2
Enable the A/D converter by setting the ADCEN bit in the SADC0 register to “1”.
• Step 3
Select which signal is to be connected to the internal A/D converter by correctly configuring the
SAINS and SACS bit fields.
Select the external channel input to be converted, go to Step 4.
Select the internal analog signal to be converted, go to Step 5.

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• Step 4
If the A/D input signal comes from the external channel input selected by configuring the SAINS
bit field, the corresponding pin should be configured as A/D input function by configuring the
relevant pin-shared function control bits. The desired analog channel then should be selected by
configuring the SACS bit field. After this step, go to Step 6.
• Step 5
Before the A/D input signal is selected to come from the internal analog signal by configuring
the SAINS bit field, the external input pin must be disabled by properly configuring the relevant
pin-shared function control bits. The desired internal analog signal then can be selected by
configuring the SAINS bit field. After this step, go to Step 6.
• Step 6
Select the reference voltage source by configuring the SAVRS1~SAVRS0 bits in the SADC1
register. If the A/D power supply voltage is selected, the external reference input pin function
must be disabled by properly configuring the corresponding pin-shared control bits.
• Step 7
Select A/D converter output data format by setting the ADRFS bit in the SADC0 register.
• Step 8
If the A/D conversion interrupt is used, the interrupt control registers must be correctly
configured to ensure the A/D interrupt function is active. The master interrupt control bit, EMI,
and the A/D conversion interrupt control bit, ADE, must both be set high in advance.
• Step 9
The A/D conversion procedure can now be initialized by setting the START bit from low to high
and then low again.
• Step 10
If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion
process is complete, the ADBZ flag will go low and then the output data can be read from
SADOH and SADOL registers.
Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit
in the SADC0 register is used, the interrupt enable step above can be omitted.

Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by clearing bit ADCEN to 0 in the
SADC0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.

A/D Conversion Function

As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the actual A/D converter reference voltage,
VREF, this gives a single bit analog input value of VREF divided by 4096.
1 LSB = VREF ÷ 4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage = A/D output digital value × VREF ÷ 4096

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The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VREF level.
Note that here the VREF voltage is the actual A/D converter reference voltage determined by the
SAVRS field.

1.5 LSB
FFFH

FFEH

FFDH
A/D Conversion
Result
0.5 LSB
03H

02H

01H
VREF
0 1 2 3 4093 4094 4095 4096 4096
Analog Input Voltage

Ideal A/D Transfer Function

A/D Conversion Programming Examples

The following two programming examples illustrate how to configure and implement an A/D
conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used
to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is
used to determine when the conversion is complete.
Example: using an ADBZ polling method to detect the end of conversion
clr ADE ; disable ADC interrupt
mov a,03h ; select fSYS/8 as A/D clock and
mov SADC1,a ; select external channel input and external reference input
mov a,0Fh ; set PAS0 to configure pin AN0 and pin VREF
mov PAS0,a
mov a,20h
mov SADC0,a ; enable A/D and connect AN0 channel to A/D converter
:
:
start_conversion:
clr START ; high pulse on start bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
polling_EOC:
sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a,SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
:
jmp start_conversion ; start next A/D conversion

Example: using the interrupt method to detect the end of conversion

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clr ADE ; disable ADC interrupt

mov a,03h ; select fSYS/8 as A/D clock and
mov SADC1,a ; select external channel input and external reference input
mov a,0Fh ; set PAS0 to configure pin AN0 and pin VREF
mov PAS0,a
mov a,20h
mov SADC0,a ; enable A/D and connect AN0 channel to A/D converter
:
:
Start_conversion:
clr START ; high pulse on START bit to initiate conversion
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set ADE ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
ADC_ISR: ; ADC interrupt service routine
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a, SADOL ; read low byte conversion result value
mov SADOL_buffer,a ; save result to user defined register
mov a, SADOH ; read high byte conversion result value
mov SADOH_buffer,a ; save result to user defined register
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti

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Low Voltage Detector – LVD

The device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.

LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The LVDEN bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.

• LVDC Register
Bit 7 6 5 4 3 2 1 0
Name — — LVDO LVDEN VBGEN VLVD2 VLVD1 VLVD0
R/W — — R R/W R/W R/W R/W R/W
POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5 LVDO: LVD Output flag
0: No low voltage detected
1: Low voltage detected
Bit 4 LVDEN: Low Voltage Detector Enable control
0: Disable
1: Enable
Bit 3 VBGEN: Bandgap Voltage Output Enable control
0: Disable
1: Enable
Note that the Bandgap circuit is enabled when the LVD or LVR function is enabled or
when the VBGEN bit is set high.
Bit 2~0 VLVD2~VLVD0: LVD Voltage selection
000: 1.8V
001: 2.0V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V

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LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level defined by the LVDC register. This has a range of between 1.8V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. When the device is in the SLEEP mode,
the low voltage detector will be disabled even if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the
LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that
of VLVD, there may be multiple bit LVDO transitions.

VDD

VLVD

LVDEN

LVDO
tLVDS

LVD Operation

The Low Voltage Detector also has its own interrupt providing an alternative means of low voltage
detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay
of tLVD after the LVDO bit has been set high by a low voltage condition, i.e., VDD falls below the
preset LVD voltage. In this case, the LVF interrupt request flag will be set, causing an interrupt to be
generated. This will cause the device to wake-up from the IDLE Mode, however if the Low Voltage
Detector wake up function is not required then the LVF flag should be first set high before the device
enters the IDLE Mode.

Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains several external
interrupt and internal interrupt functions. The external interrupts are generated by the action of the
external INT0~INT1 pins, while the internal interrupts are generated by various internal functions
including the TM, Time Bases, LVD, EEPROM and the A/D converter.

Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application
program, is controlled by a series of registers, located in the Special Purpose Data Memory, as
shown in the accompanying table. The number of registers falls into two categories. The first is the
INTC0~INTC2 registers which set the primary interrupts, the second is the INTEG register to set
the external interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/disable bit or “F” for request flag.

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Function Enable Bit Request Flag Notes

Global EMI — —
INTn Pin INTnE INTnF n=0 or 1
Time Bases TBnE TBnF n=0 or 1
A/D Converter ADE ADF —
LVD LVE LVF —
EEPROM DEE DEF —
PTMPE PTMPF —
PTM
PTMAE PTMAF —
Interrupt Register Bit Naming Conventions

Register Bit
Name 7 6 5 4 3 2 1 0
INTEG — — — — INTS3 INTS2 INTS1 INTS0
INTC0 — PTMPF INT1F INT0F PTMPE INT1E INT0E EMI
INTC1 ADF TB1F TB0F PTMAF ADE TB1E TB0E PTMAE
INTC2 — — DEF LVF — — DEE LVE
Interrupt Register List

• INTEG Register
Bit 7 6 5 4 3 2 1 0
Name — — — — INTS3 INTS2 INTS1 INTS0
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3~2 INTS3~INTS2: Interrupt edge control for INT1 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 1~0 INTS1~INTS0: Interrupt edge control for INT0 pin
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges

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• INTC0 Register
Bit 7 6 5 4 3 2 1 0
Name — PTMPF INT1F INT0F PTMPE INT1E INT0E EMI
R/W — R/W R/W R/W R/W R/W R/W R/W
POR — 0 0 0 0 0 0 0

Bit 7 Unimplemented, read as “0”

Bit 6 PTMPF: PTM Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 5 INT1F: INT1 interrupt request flag
0: No request
1: Interrupt request
Bit 4 INT0F: INT0 interrupt request flag
0: No request
1: Interrupt request
Bit 3 PTMPE: PTM Comparator P match interrupt control
0: Disable
1: Enable
Bit 2 INT1E: INT1 interrupt control
0: Disable
1: Enable
Bit 1 INT0E: INT0 interrupt control
0: Disable
1: Enable
Bit 0 EMI: Global interrupt control
0: Disable
1: Enable

• INTC1 Register
Bit 7 6 5 4 3 2 1 0
Name ADF TB1F TB0F PTMAF ADE TB1E TB0E PTMAE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0

Bit 7 ADF: A/D converter interrupt request flag

0: No request
1: Interrupt request
Bit 6 TB1F: Time Base 1 interrupt request flag
0: No request
1: Interrupt request
Bit 5 TB0F: Time Base 0 interrupt request flag
0: No request
1: Interrupt request
Bit 4 PTMAF: PTM Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 3 ADE: A/D converter interrupt control
0: Disable
1: Enable
Bit 2 TB1E: Time Base 1 interrupt control
0: Disable
1: Enable

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Bit 1 TB0E: Time Base 0 interrupt control

0: Disable
1: Enable
Bit 0 PTMAE: PTM Comparator A match interrupt control
0: Disable
1: Enable

• INTC2 Register
Bit 7 6 5 4 3 2 1 0
Name — — DEF LVF — — DEE LVE
R/W — — R/W R/W — — R/W R/W
POR — — 0 0 — — 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5 DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 4 LVF: LVD interrupt request flag
0: No request
1: Interrupt request
Bit 3~2 Unimplemented, read as “0”
Bit 1 DEE: Data EEPROM interrupt control
0: Disable
1: Enable
Bit 0 LVE: LVD interrupt control
0: Disable
1: Enable

Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A
match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether
the request flag actually generates a program jump to the relevant interrupt vector is determined by
the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to
its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual
interrupt will not be generated and the program will not jump to the relevant interrupt vector. The
global interrupt enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. All interrupt sources have their own individual
vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global
interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt
nesting from occurring. However, if other interrupt requests occur during this interval, although the
interrupt will not be immediately serviced, the request flag will still be recorded.

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If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.

Legend
xxF Request Flag, auto reset in ISR

xxE Enable Bits

EMI auto disabled in ISR

Interrupt Request Enable Master Vector Priority

Name Flags Bits Enable
High
INT0 Pin INT0F INT0E EMI 04H

INT1 Pin INT1F INT1E EMI 08H

PTM P PTMPF PTMPE EMI 0CH

PTM A PTMAF PTMAE EMI 10H

Time Base 0 TB0F TB0E EMI 14H

Time Base 1 TB1F TB1E EMI 18H

A/D ADF ADE EMI 1CH

LVD LVF LVE EMI 20H

EEPROM DEF DEE EMI 24H

Low

Interrupt Structure

External Interrupts
The external interrupts are controlled by signal transitions on the pins INT0 and INT1. An external
interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address,
the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E,
must first be set. Additionally the correct interrupt edge type must be selected using the INTEG
register to enable the external interrupt function and to choose the trigger edge type. As the external
interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if
their external interrupt enable bit in the corresponding interrupt register has been set and the external
interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also
be set as an input by setting the corresponding bit in the port control register. When the interrupt is
enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a
subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the

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external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.

TM Interrupts
The Periodic Type TM has two interrupts, one comes from the comparator A match situation and
the other comes from the comparator P match situation. For the Periodic Type TM there are two
interrupt request flags and two enable control bits. A PTM interrupt request will take place when
any of the PTM request flags are set, a situation which occurs when a PTM comparator P or A match
situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, and the PTM Interrupt enable bit must first be set. When the interrupt is enabled, the stack
is not full and a PTM comparator match situation occurs, a subroutine call to the PTM Interrupt
vector location, will take place. When the PTM interrupt is serviced, the PTM interrupt request flags
will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.

Time Base Interrupts

The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4, fLIRC_PTM or fLIRC/8
and then passes through a divider, the division ratio of which is selected by programming the
appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value
ranges. The clock source which in turn controls the Time Base interrupt period is selected using
the CLKSEL0[1:0] bits in the PSC0R register and the CLKSEL1[1:0] bits in the PSC1R register
respectively.

TB0ON
fSYS M
M fPSC0 fPSC0/28 ~ fPSC0/215
fSYS/4 U Time Base 0 Interrupt
U Prescaler 0
fLIRC_PTM X
X
fLIRC/8
PSC0EN TB0[2:0]
CLKSEL0[1:0]

fSYS
M fPSC1 fPSC1/28 ~ fPSC1/215 M
fSYS/4
U Prescaler 1 U Time Base 1 Interrupt
fLIRC_PTM
X X
fLIRC/8
TB1ON
PSC1EN
CLKSEL1[1:0] TB1[2:0]

Time Base Interrupts

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• PSC0R Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — PSC0EN CLKSEL01 CLKSEL00
R/W — — — — — R/W R/W R/W
POR — — — — — 0 0 0

Bit 7~3 Unimplemented, read as “0”

Bit 2 PSC0EN: Prescaler 0 control
0: Disable
1: Enable
Bit 1~0 CLKSEL01~CLKSEL00: Prescaler 0 clock source fPSC0 selection
00: fSYS
01: fSYS/4
10: fLIRC_PTM
11: fLIRC/8

• PSC1R Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — PSC1EN CLKSEL11 CLKSEL10
R/W — — — — — R/W R/W R/W
POR — — — — — 0 0 0

Bit 7~3 Unimplemented, read as “0”

Bit 2 PSC1EN: Prescaler 1 control
0: Disable
1: Enable
Bit 1~0 CLKSEL11~CLKSEL10: Prescaler 1 clock source fPSC1 selection
00: fSYS
01: fSYS/4
10: fLIRC_PTM
11: fLIRC/8

• TB0C Register
Bit 7 6 5 4 3 2 1 0
Name TB0ON — — — — TB02 TB01 TB00
R/W R/W — — — — R/W R/W R/W
POR 0 — — — — 0 0 0

Bit 7 TB0ON: Time Base 0 Control

0: Disable
1: Enable
Bit 6~3 Unimplemented, read as “0”
Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period
000: 28/fPSC0
001: 29/fPSC0
010: 210/fPSC0
011: 211/fPSC0
100: 212/fPSC0
101: 213/fPSC0
110: 214/fPSC0
111: 215/fPSC0

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• TB1C Register
Bit 7 6 5 4 3 2 1 0
Name TB1ON — — — — TB12 TB11 TB10
R/W R/W — — — — R/W R/W R/W
POR 0 — — — — 0 0 0

Bit 7 TB1ON: Time Base 1 Control

0: Disable
1: Enable
Bit 6~3 Unimplemented, read as “0”
Bit 2~0 TB12~TB10: Select Time Base 1 Time-out Period
000: 28/fPSC1
001: 29/fPSC1
010: 210/fPSC1
011: 211/fPSC1
100: 212/fPSC1
101: 213/fPSC1
110: 214/fPSC1
111: 215/fPSC1

A/D Converter Interrupt

An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag,
ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch
to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt
enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D
conversion process has ended, a subroutine call to the A/D Interrupt vector, will take place. When
the A/D Converter Interrupt is serviced, the A/D Interrupt flag, ADF, will be automatically cleared.
The EMI bit will also be automatically cleared to disable other interrupts.

LVD Interrupt
An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which
occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the
program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and
the Low Voltage Interrupt enable bit, LVE, must first be set. When the interrupt is enabled, the stack
is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take
place. When the Low Voltage Interrupt is serviced, the LVF flag will be automatically cleared. The
EMI bit will also be automatically cleared to disable other interrupts.

EEPROM Interrupt
An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the EEPROM Interrupt vector will take place. When the EEPROM
Interrupt is serviced, the EEPROM Interrupt flag, DEF, will be automatically cleared. The EMI bit
will also be automatically cleared to disable other interrupts.

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Interrupt Wake-up Function

Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins or a low power supply voltage may cause their respective
interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if
spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then
the corresponding interrupt request flag should be set high before the device enters the SLEEP or
IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function.

Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service
routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.

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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device
during the programming process. During the development process, these options are selected using
the HT-IDE software development tools. As these options are programmed into the device using
the hardware programming tools, once they are selected they cannot be changed later using the
application program. All options must be defined for proper system function, the details of which are
shown in the table.
No. Option
1 HIRC Frequency Selection – fHIRC: 2MHz, 4MHz or 8MHz

Note: When the HIRC has been configured at a frequency shown in this table, it is recommended to
configure the HIRC1 and HIRC0 bits in the HIRCC register to select the same frequency to
ensure a higher HIRC frequency accuracy specified in the A.C. characteristics.

Application Circuits
VDD

VDD PA0~PA7
PB0~PB7 Control Device
100kΩ PC0~PC1
0.1µF RES
0.1µF
AN0~AN3 Analog Signals
VSS

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Instruction Set

Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.

Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.

Moving and Transferring Data

The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.

Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.

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Logical and Rotate Operation

The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.

Branches and Control Transfer

Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.

Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].i"
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.

Table Read Operations

Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.

Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.

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Instruction Set Summary

The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.

Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic Description Cycles Flag Affected
Arithmetic
ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV
ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV
ADD A,x Add immediate data to ACC 1 Z, C, AC, OV
ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV
ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV
SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV
SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV
SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV
SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV
DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C
Logic Operation
AND A,[m] Logical AND Data Memory to ACC 1 Z
OR A,[m] Logical OR Data Memory to ACC 1 Z
XOR A,[m] Logical XOR Data Memory to ACC 1 Z
ANDM A,[m] Logical AND ACC to Data Memory 1Note Z
ORM A,[m] Logical OR ACC to Data Memory 1Note Z
XORM A,[m] Logical XOR ACC to Data Memory 1Note Z
AND A,x Logical AND immediate Data to ACC 1 Z
OR A,x Logical OR immediate Data to ACC 1 Z
XOR A,x Logical XOR immediate Data to ACC 1 Z
CPL [m] Complement Data Memory 1Note Z
CPLA [m] Complement Data Memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment Data Memory with result in ACC 1 Z
INC [m] Increment Data Memory 1Note Z
DECA [m] Decrement Data Memory with result in ACC 1 Z
DEC [m] Decrement Data Memory 1Note Z
Rotate
RRA [m] Rotate Data Memory right with result in ACC 1 None
RR [m] Rotate Data Memory right 1Note None
RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C
RRC [m] Rotate Data Memory right through Carry 1Note C
RLA [m] Rotate Data Memory left with result in ACC 1 None
RL [m] Rotate Data Memory left 1Note None
RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C
RLC [m] Rotate Data Memory left through Carry 1Note C

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Mnemonic Description Cycles Flag Affected

Data Move
MOV A,[m] Move Data Memory to ACC 1 None
MOV [m],A Move ACC to Data Memory 1Note None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of Data Memory 1Note None
SET [m].i Set bit of Data Memory 1Note None
Branch Operation
JMP addr Jump unconditionally 2 None
SZ [m] Skip if Data Memory is zero 1Note None
SZA [m] Skip if Data Memory is zero with data movement to ACC 1Note None
SZ [m].i Skip if bit i of Data Memory is zero 1Note None
SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None
SIZ [m] Skip if increment Data Memory is zero 1Note None
SDZ [m] Skip if decrement Data Memory is zero 1Note None
SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None
SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read Operation
TABRD [m] Read table (specific page or current page) to TBLH and Data Memory 2Note None
TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear Data Memory 1Note None
SET [m] Set Data Memory 1Note None
CLR WDT Clear Watchdog Timer 1 TO, PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO, PDF
CLR WDT2 Pre-clear Watchdog Timer 1 TO, PDF
SWAP [m] Swap nibbles of Data Memory 1Note None
SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None
HALT Enter power down mode 1 TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then up to two cycles are required, if
no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2"
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

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Instruction Definition

ADC A,[m] Add Data Memory to ACC with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
Operation ACC ← ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADCM A,[m] Add ACC to Data Memory with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
Operation [m] ← ACC + [m] + C
Affected flag(s) OV, Z, AC, C

ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation ACC ← ACC + [m]
Affected flag(s) OV, Z, AC, C

ADD A,x Add immediate data to ACC

Description The contents of the Accumulator and the specified immediate data are added.
The result is stored in the Accumulator.
Operation ACC ← ACC + x
Affected flag(s) OV, Z, AC, C

ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
Operation [m] ← ACC + [m]
Affected flag(s) OV, Z, AC, C

AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″AND″ [m]
Affected flag(s) Z

AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bit wise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″AND″ x
Affected flag(s) Z

ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
Operation [m] ← ACC ″AND″ [m]
Affected flag(s) Z

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CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation Stack ← Program Counter + 1
Program Counter ← addr
Affected flag(s) None

CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.
Operation [m] ← 00H
Affected flag(s) None

CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.
Operation [m].i ← 0
Affected flag(s) None

CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.
Operation WDT cleared
TO ← 0
PDF ← 0
Affected flag(s) TO, PDF

CLR WDT1 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
Operation WDT cleared
TO ← 0
PDF ← 0
Affected flag(s) TO, PDF

CLR WDT2 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation WDT cleared
TO ← 0
PDF ← 0
Affected flag(s) TO, PDF

CPL [m] Complement Data Memory

Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
Operation [m] ← [m]
Affected flag(s) Z

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CPLA [m] Complement Data Memory with result in ACC

Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC ← [m]
Affected flag(s) Z

DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
Operation [m] ← ACC + 00H or
[m] ← ACC + 06H or
[m] ← ACC + 60H or
[m] ← ACC + 66H
Affected flag(s) C

DEC [m] Decrement Data Memory

Description Data in the specified Data Memory is decremented by 1.
Operation [m] ← [m] − 1
Affected flag(s) Z

DECA [m] Decrement Data Memory with result in ACC

Description Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC ← [m] − 1
Affected flag(s) Z

HALT Enter power down mode

Description This instruction stops the program execution and turns off the system clock. The contents of
the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
Operation TO ← 0
PDF ← 1
Affected flag(s) TO, PDF

INC [m] Increment Data Memory

Description Data in the specified Data Memory is incremented by 1.
Operation [m] ← [m] + 1
Affected flag(s) Z

INCA [m] Increment Data Memory with result in ACC

Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
Operation ACC ← [m] + 1
Affected flag(s) Z

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JMP addr Jump unconditionally

Description The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation Program Counter ← addr
Affected flag(s) None

MOV A,[m] Move Data Memory to ACC

Description The contents of the specified Data Memory are copied to the Accumulator.
Operation ACC ← [m]
Affected flag(s) None

MOV A,x Move immediate data to ACC

Description The immediate data specified is loaded into the Accumulator.
Operation ACC ← x
Affected flag(s) None

MOV [m],A Move ACC to Data Memory

Description The contents of the Accumulator are copied to the specified Data Memory.
Operation [m] ← ACC
Affected flag(s) None

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
Affected flag(s) None

OR A,[m] Logical OR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″OR″ [m]
Affected flag(s) Z

OR A,x Logical OR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″OR″ x
Affected flag(s) Z

ORM A,[m] Logical OR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
operation. The result is stored in the Data Memory.
Operation [m] ← ACC ″OR″ [m]
Affected flag(s) Z

RET Return from subroutine

Description The Program Counter is restored from the stack. Program execution continues at the restored
address.
Operation Program Counter ← Stack
Affected flag(s) None

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RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
Operation Program Counter ← Stack
ACC ← x
Affected flag(s) None

RETI Return from interrupt

Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the
RETI instruction is executed, the pending Interrupt routine will be processed before returning
to the main program.
Operation Program Counter ← Stack
EMI ← 1
Affected flag(s) None

RL [m] Rotate Data Memory left

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
Operation [m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
Affected flag(s) None

RLA [m] Rotate Data Memory left with result in ACC

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
Operation ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
Affected flag(s) None

RLC [m] Rotate Data Memory left through Carry

Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation [m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
Affected flag(s) C

RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
Affected flag(s) C

RR [m] Rotate Data Memory right

Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
Operation [m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
Affected flag(s) None

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RRA [m] Rotate Data Memory right with result in ACC

Description Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
Operation ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
Affected flag(s) None

RRC [m] Rotate Data Memory right through Carry

Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation [m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
Affected flag(s) C

RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
Affected flag(s) C

SBC A,[m] Subtract Data Memory from ACC with Carry

Description The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − [m] − C
Affected flag(s) OV, Z, AC, C

SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ← ACC − [m] − C
Affected flag(s) OV, Z, AC, C

SDZ [m] Skip if decrement Data Memory is 0

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ← [m] − 1
Skip if [m]=0
Affected flag(s) None

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SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
Operation ACC ← [m] − 1
Skip if ACC=0
Affected flag(s) None

SET [m] Set Data Memory

Description Each bit of the specified Data Memory is set to 1.
Operation [m] ← FFH
Affected flag(s) None

SET [m].i Set bit of Data Memory

Description Bit i of the specified Data Memory is set to 1.
Operation [m].i ← 1
Affected flag(s) None

SIZ [m] Skip if increment Data Memory is 0

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ← [m] + 1
Skip if [m]=0
Affected flag(s) None

SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC ← [m] + 1
Skip if ACC=0
Affected flag(s) None

SNZ [m].i Skip if bit i of Data Memory is not 0

Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation Skip if [m].i ≠ 0
Affected flag(s) None

SUB A,[m] Subtract Data Memory from ACC

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − [m]
Affected flag(s) OV, Z, AC, C

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SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ← ACC − [m]
Affected flag(s) OV, Z, AC, C

SUB A,x Subtract immediate data from ACC

Description The immediate data specified by the code is subtracted from the contents of the Accumulator.
The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − x
Affected flag(s) OV, Z, AC, C

SWAP [m] Swap nibbles of Data Memory

Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation [m].3~[m].0 ↔ [m].7~[m].4
Affected flag(s) None

SWAPA [m] Swap nibbles of Data Memory with result in ACC

Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
Affected flag(s) None

SZ [m] Skip if Data Memory is 0

Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation Skip if [m]=0
Affected flag(s) None

SZA [m] Skip if Data Memory is 0 with data movement to ACC

Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,
the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation ACC ← [m]
Skip if [m]=0
Affected flag(s) None

SZ [m].i Skip if bit i of Data Memory is 0

Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Operation Skip if [m].i=0
Affected flag(s) None

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TABRD [m] Read table (specific page or current page) to TBLH and Data Memory
Description The low byte of the program code addressed by the table pointer (TBHP and TBLP or only
TBLP if no TBHP) is moved to the specified Data Memory and the high byte moved to
TBLH.
Operation [m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s) None

TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ← program code (low byte)
TBLH ← program code (high byte)
Affected flag(s) None

XOR A,[m] Logical XOR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″XOR″ [m]
Affected flag(s) Z

XORM A,[m] Logical XOR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
operation. The result is stored in the Data Memory.
Operation [m] ← ACC ″XOR″ [m]
Affected flag(s) Z

XOR A,x Logical XOR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″XOR″ x
Affected flag(s) Z

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Package Information

Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.

Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.

• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)

• The Operation Instruction of Packing Materials

• Carton information

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8-pin SOP (150mil) Outline Dimensions

 
 
 

 

 

  

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.012 — 0.020
C′ — 0.193 BSC —
D — — 0.069
E — 0.050 BSC —
F 0.004 — 0.010
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°

Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.00 BSC —
B — 3.90 BSC —
C 0.31 — 0.51
C′ — 4.90 BSC —
D — — 1.75
E — 1.27 BSC —
F 0.10 — 0.25
G 0.40 — 1.27
H 0.10 — 0.25
α 0° — 8°

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10-pin MSOP (118mil) Outline Dimensions

 
 




  
 
     
   
        

Dimensions in inch
Symbol
Min. Nom. Max.
A — — 0.043
A1 0.000 — 0.006
A2 0.030 0.033 0.037
B 0.007 — 0.013
C 0.003 — 0.009
D — 0.118 BSC —
E — 0.193 BSC —
E1 — 0.118 BSC —
e — 0.020 BSC —
L 0.016 0.024 0.031
L1 — 0.037 BSC —
y — 0.004 —
θ 0° — 8°

Dimensions in mm
Symbol
Min. Nom. Max.
A — — 1.10
A1 0.00 — 0.15
A2 0.75 0.85 0.95
B 0.17 — 0.33
C 0.08 — 0.23
D — 3.00 BSC —
E — 4.90 BSC —
E1 — 3.00 BSC —
e — 0.50 BSC —
L 0.40 0.60 0.80
L1 — 0.95 BSC —
y — 0.10 —
θ 0° — 8°

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16-pin SSOP (150mil) Outline Dimensions

  

 

 

 

 

  

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.008 — 0.012
C’ — 0.193 BSC —
D — — 0.069
E — 0.025 BSC —
F 0.004 — 0.010
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°

Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.000 BSC —
B — 3.900 BSC —
C 0.20 — 0.30
C’ — 4.900 BSC —
D — — 1.75
E — 0.635 BSC —
F 0.10 — 0.25
G 0.41 — 1.27
H 0.10 — 0.25
α 0° — 8°

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16-pin NSOP (150mil) Outline Dimensions

  
 
 

 

 

  

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.012 — 0.020
C' — 0.390 BSC —
D — — 0.069
E — 0.050 BSC —
F 0.004 — 0.010
G 0.016 — 0.050
H 0.004 — 0.010
α 0° ― 8°

Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.000 BSC —
B — 3.900 BSC —
C 0.31 — 0.51
C' — 9.900 BSC —
D — — 1.75
E — 1.270 BSC —
F 0.10 — 0.25
G 0.40 — 1.27
H 0.10 — 0.25
α 0° ― 8°

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20-pin NSOP (150mil) Outline Dimensions

   

 

  

 

 

  

Dimensions in inch
Symbol
Min. Nom. Max.
A 0.228 0.236 0.244
B 0.146 0.154 0.161
C 0.009 — 0.012
C’ 0.382 0.390 0.398
D — — 0.069
E — 0.032 BSC —
F 0.002 — 0.009
G 0.020 — 0.031
H 0.008 — 0.010
α 0° — 8°

Dimensions in mm
Symbol
Min. Nom. Max.
A 5.80 6.00 6.20
B 3.70 3.90 4.10
C 0.23 — 0.30
C’ 9.70 9.90 10.10
D — — 1.75
E — 0.80 BSC —
F 0.05 — 0.23
G 0.50 — 0.80
H 0.21 — 0.25
α 0° — 8°

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Copyright© 2019 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.

Rev. 1.10 112 November 19, 2019