IHI0089C Amba Lti Protocol Spec
IHI0089C Amba Lti Protocol Spec
Protocol Specification
Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved.
ARM IHI0089C (ID070124)
AMBA LTI
Protocol Specification
Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved.
Release Information
Change history
26 September 2023 B Non-confidential Release with support for Realm Management Extension (RME) and
Memory Encryption Contexts (MEC)
01 July 2024 C Non-Confidential Release with support for Device Permission Table (DPT) and coherent
interfaces
This document is protected by copyright and other related rights and the use or implementation of the information contained in
this document may be protected by one or more patents or pending patent applications. No part of this document may be
reproduced in any form by any means without the express prior written permission of Arm Limited ("Arm"). No license, express
or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically
stated.
Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use
the information for the purposes of determining whether the subject matter of this document infringes any third party patents.
The content of this document is informational only. Any solutions presented herein are subject to changing conditions,
information, scope, and data. This document was produced using reasonable efforts based on information available as of the date
of issue of this document. The scope of information in this document may exceed that which Arm is required to provide, and such
additional information is merely intended to further assist the recipient and does not represent Arm's view of the scope of its
obligations. You acknowledge and agree that you possess the necessary expertise in system security and functional safety and that
you shall be solely responsible for compliance with all legal, regulatory, safety and security related requirements concerning your
products, notwithstanding any information or support that may be provided by Arm herein. In addition, you are responsible for
any applications which are used in conjunction with any Arm technology described in this document, and to minimize risks,
adequate design and operating safeguards should be provided for by you.
This document may include technical inaccuracies or typographical errors. THIS DOCUMENT IS PROVIDED "AS IS". ARM
PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING,
WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY,
NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the
avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the
scope and content of, any patents, copyrights, trade secrets, trademarks, or other rights.
TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES,
INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR
CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING
OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
Reference by Arm to any third party's products or services within this document is not an express or implied approval or
endorsement of the use thereof.
This document consists solely of commercial items. You shall be responsible for ensuring that any permitted use, duplication, or
disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any
portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word "partner" in reference to
Arm's customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes
to this document at any time and without notice.
This document may be translated into other languages for convenience, and you agree that if there is any conflict between the
English version of this document and any translation, the terms of the English version of this document shall prevail.
ii Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
The validity, construction and performance of this notice shall be governed by English Law.
The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its affiliates)
in the US and/or elsewhere. Please follow Arm's trademark usage guidelines at
http://www.arm.com/company/policies/trademarks. All rights reserved. Other brands and names mentioned in this document may
be the trademarks of their respective owners.
Copyright © 2016-2018, 2020-2024 Arm Limited or its affiliates. All rights reserved.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. iii
ID070124 Non-Confidential
AMBA SPECIFICATION LICENCE
THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A
SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF ARM'S
INTELLECTUAL PROPERTY (INCLUDING, WITHOUT LIMITATION, ANY COPYRIGHT) IN THE RELEVANT AMBA
SPECIFICATION ACCOMPANYING THIS LICENCE. ARM LICENSES THE RELEVANT AMBA SPECIFICATION TO
YOU ON CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE" OR
OTHERWISE USING OR COPYING THE RELEVANT AMBA SPECIFICATION YOU INDICATE THAT YOU AGREE TO
BE BOUND BY ALL THE TERMS OF THIS LICENCE.
"Subsidiary" means, if You are a single entity, any company the majority of whose voting shares is now or hereafter owned or
controlled, directly or indirectly, by You. A company shall be a Subsidiary only for the period during which such control exists.
1. Subject to the provisions of Clauses 2, 3 and 4, Arm hereby grants to LICENSEE a perpetual, non-exclusive,
non-transferable, royalty free, worldwide licence to:
(i) use and copy the relevant AMBA Specification for the purpose of developing and having developed products
that comply with the relevant AMBA Specification;
(ii) manufacture and have manufactured products which either: (a) have been created by or for LICENSEE under
the licence granted in Clause 1(i); or (b) incorporate a product(s) which has been created by a third party(s)
under a licence granted by Arm in Clause 1(i) of such third party's AMBA Specification Licence; and
(iii) offer to sell, sell, supply or otherwise distribute products which have either been (a) created by or for
LICENSEE under the licence granted in Clause 1(i); or (b) manufactured by or for LICENSEE under the
licence granted in Clause 1(ii).
2. LICENSEE hereby agrees that the licence granted in Clause 1 is subject to the following restrictions:
(i) where a product created under Clause 1(i) is an integrated circuit which includes a CPU then either: (a) such
CPU shall only be manufactured under licence from Arm; or (b) such CPU is neither substantially compliant
with nor marketed as being compliant with the Arm instruction sets licensed by Arm from time to time;
(ii) the licences granted in Clause 1(iii) shall not extend to any portion or function of a product that is not itself
compliant with part of the relevant AMBA Specification; and
(iii) no right is granted to LICENSEE to sublicense the rights granted to LICENSEE under this Agreement.
3. Except as specifically licensed in accordance with Clause 1, LICENSEE acquires no right, title or interest in any Arm
technology or any intellectual property embodied therein. In no event shall the licences granted in accordance with Clause
1 be construed as granting LICENSEE, expressly or by implication, estoppel or otherwise, a licence to use any Arm
technology except the relevant AMBA Specification.
6. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the Arm
tradename, or AMBA trademark in connection with the relevant AMBA Specification or any products based thereon.
Nothing in Clause 1 shall be construed as authority for LICENSEE to make any representations on behalf of Arm in respect
of the relevant AMBA Specification.
7. This Licence shall remain in force until terminated by you or by Arm. Without prejudice to any of its other rights if
LICENSEE is in breach of any of the terms and conditions of this Licence then Arm may terminate this Licence
immediately upon giving written notice to You. You may terminate this Licence at any time. Upon expiry or termination
iv Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
of this Licence by You or by Arm LICENSEE shall stop using the relevant AMBA Specification and destroy all copies of
the relevant AMBA Specification in your possession together with all documentation and related materials. Upon expiry
or termination of this Licence, the provisions of clauses 6 and 7 shall survive.
8. The validity, construction and performance of this Agreement shall be governed by English Law.
PRE-21451 version 3
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in
accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
Product Status
Web Address
http://www.arm.com
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. v
ID070124 Non-Confidential
vi Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Contents
AMBA LTI Protocol Specification
Preface
About this specification .............................................................................................. xii
Intended audience ....................................................................................... xii
Using this specification ................................................................................ xii
Conventions ................................................................................................ xiii
Typographic conventions ............................................................................ xiii
Timing diagrams ......................................................................................... xiii
Signals ........................................................................................................ xiv
Numbers ..................................................................................................... xiv
Additional reading ..................................................................................................... xv
Arm publications ......................................................................................... xv
Other publications ....................................................................................... xv
Feedback .................................................................................................................. xvi
Inclusive terminology commitment .............................................................. xvi
Chapter 1 Introduction
1.1 About the LTI protocol ............................................................................................ 1-18
1.2 Use cases .............................................................................................................. 1-19
1.2.1 In-line integration ..................................................................................... 1-19
1.2.2 Lookaside integration ............................................................................... 1-20
1.2.3 Cached integration ................................................................................... 1-20
1.3 Differences between DTI and LTI .......................................................................... 1-21
1.4 Supported translation flows .................................................................................... 1-22
1.4.1 Stall flow ................................................................................................... 1-22
1.4.2 ATST flow ................................................................................................ 1-22
1.4.3 NoStall flow .............................................................................................. 1-22
1.4.4 PRI flow .................................................................................................... 1-23
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. vii
ID070124 Non-Confidential
Chapter 2 Channels
2.1 Transaction flow ..................................................................................................... 2-26
2.2 Virtual Channels ..................................................................................................... 2-28
2.3 Flow control ............................................................................................................ 2-29
2.4 Reserved encodings .............................................................................................. 2-30
2.5 Signal validity ......................................................................................................... 2-31
Chapter 3 Properties
3.1 LTI properties ......................................................................................................... 3-34
Chapter 9 Pipelining
9.1 Pipelining between Manager and Subordinate interfaces ...................................... 9-72
Chapter 10 Interoperability
10.1 LTI-A compatibility ................................................................................................ 10-74
10.2 LTI_MMU and LTI_GPC properties ..................................................................... 10-75
10.3 MPAM compatibility .............................................................................................. 10-76
10.4 LAMECID and LAHWATTR signals compatibility ................................................ 10-77
viii Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
A.6 Transactions that are legal in AXI5 and illegal in LTI ............................................ A-85
A.7 Memory Tagging ................................................................................................... A-86
Appendix F Revisions
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ix
ID070124 Non-Confidential
x Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Preface
This preface introduces the AMBA® LTI Protocol Specification. It contains the following sections:
• About this specification on page xii
• Additional reading on page xv
• Feedback on page xvi
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. xi
ID070124 Non-Confidential
Preface
About this specification
Intended audience
This specification is written for hardware engineers who wish to design components that implement Local
Translation Interface (LTI).
Chapter 2 Channels
Describes LTI information flow.
Chapter 3 Properties
Describes the set of LTI properties that specify the supported behavior and interface signaling
requirements.
Chapter 9 Pipelining
Defines pipelining requirements for LTI.
Chapter 10 Interoperability
Describes how to connect LTI interfaces with different properties.
Appendix F Revisions
Describes the technical changes between issues of this specification.
xii Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Preface
About this specification
Conventions
The following sections describe conventions that this specification can use:
• Typographic conventions
• Timing diagrams
• Signals on page xiv
• Numbers on page xiv
Typographic conventions
The typographical conventions are:
italic Highlights important notes, introduces special terminology, and denotes internal
cross-references and citations.
bold Denotes signal names, and is used for terms in descriptive lists, where appropriate.
monospace Used for assembler syntax descriptions, pseudocode, and source code examples.
Also used in the main text for instruction mnemonics and for references to other items
appearing in assembler syntax descriptions, pseudocode, and source code examples.
SMALL CAPITALS Used for a few terms that have specific technical meanings.
Timing diagrams
The components used in timing diagrams are explained in figure Key to timing diagram conventions. Variations
have clear labels, when they occur. Do not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that
time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus change
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar to
the bus change shown in Key to timing diagram conventions. If a timing diagram shows a single-bit signal in this
way then its value does not affect the accompanying description.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. xiii
ID070124 Non-Confidential
Preface
About this specification
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means:
• HIGH for active-HIGH signals
• LOW for active-LOW signals.
Lowercase x At the second letter of a signal name denotes a collective term for both Read and Write. For
example, AxCACHE refers to both the ARCACHE and AWCACHE signals.
Numbers
Numbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x.
Both are written in a monospace font.
xiv Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Preface
Additional reading
Additional reading
This section lists relevant publications from Arm.
Arm publications
• AMBA ® AXI Protocol Specification (ARM IHI 0022)
• AMBA ® DTI Protocol Specification (ARM IHI 0088)
• AMBA ® CHI Architecture Specification (ARM IHI 0050)
• AMBA ® CHI Chip-to-Chip (C2C) Architecture Specification (ARM IHI 0098)
• Arm® System Memory Management Unit Architecture Specification (ARM IHI 0070)
• Arm® Architecture Reference Manual for A-profile Architecture (ARM DDI 0487)
Other publications
• PCIe Express Base Specification, Revision 6, PCI-SIG
• Compute Expresss Link (CXL), CXL Consortium
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. xv
ID070124 Non-Confidential
Preface
Feedback
Feedback
Arm welcomes feedback on its documentation.
If you have any comments or suggestions for additions and improvements, create a ticket at
https://support.developer.arm.com. As part of the ticket, include:
• The title, AMBA LTI Protocol Specification.
• The number, ARM IHI0089C.
• The section name to which your comments refer.
• The page number(s) to which your comments apply.
• A concise explanation of your comments.
Previous issues of this document included language that can be offensive. We have replaced this language. To report
offensive language in this document, email [email protected].
xvi Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 1
Introduction
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 1-17
ID070124 Non-Confidential
1 Introduction
1.1 About the LTI protocol
LTI is a point-to-point protocol and defines the communication between an IO Manager and a Translation Buffer
Unit (TBU). LTI enables devices to directly request a translation for each transaction while leaving the TBU to
manage the Translation Lookaside Buffer (TLB). This enables translations to be requested before ordering
requirements are met and avoiding the need to pass transactions through the TBU. This provides improved
performance and reduced silicon area.
This specification describes the LTI protocol and the components of an LTI-compliant implementation. The LTI
protocol is used by implementations of the Arm System MMUv3 (SMMUv3) Architecture Specification.
1-18 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
1 Introduction
1.2 Use cases
• A Bus Interface Unit (BIU), which fetches a translation for each transaction using LTI.
• A TLB Unit (TLBU) caches translations in a TLB. TLBU receives translation requests using LTI, and if the
requested translation is not available in its TLB, it requests translations from a TCU using DTI.
• A Translation Control Unit (TCU), which calculates translations, reading translation tables when required.
Typically, the BIU and TLBU are packaged together as a TBU. Alternatively, the TBU might consist of just the
TLBU.
SMMU components
Device
AXI
Page table
AXI AXI walks
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 1-19
ID070124 Non-Confidential
1 Introduction
1.2 Use cases
SMMU components
Page table
AXI walks
SMMU components
Device TCU
DTI
TLB
Page table
AXI walks
1-20 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
1 Introduction
1.3 Differences between DTI and LTI
LTI DTI
Topology Designed for connecting to a single, local Designed for connecting multiple TBUs to a
TLBU over a short distance. TCU over a longer distance.
Invalidation No invalidation is required, because The DTI Translation Buffer Unit (TBU) or
translations are not cached. PCIe Root Port (RP) must support
invalidation messages to invalidate
translations that are previously returned.
Mapping Provides the translated transaction Requires the TBU or PCIe RP to follow
translations to information directly, making it simple to rules on how to map configuration cache
transactions use. entries and TLB entries on to each
transaction.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 1-21
ID070124 Non-Confidential
1 Introduction
1.4 Supported translation flows
• Immediately terminate the transaction and optionally record an error record that informs software that the
transaction was terminated.
• Stall the translation and inform software that the translation is stalled. Software can then terminate the
transaction, or update the translation tables and retry the translation. The LTI Manager is not aware of the
stall.
Stall flow enables software to manage translation faults and demand paging without the client device being aware.
However, it has some limitations:
• The LTI Manager can see long translation times, potentially triggering timeouts.
• Due to the dependence of software activity, the Stall flow can cause deadlocks in some systems.
For example, Stall flow is not recommended for use with PCIe, because of dependencies between outgoing
transactions to PCIe from a CPU, and incoming transactions from PCIe through the SMMU.
Enabling the Stall flow does not necessarily cause a stall when a translation fault occurs. Stalls only occur when
enabled by software. Software does not normally enable stalling for PCIe endpoints.
1. A PCIe endpoint requests a translation over ATS, which is passed to the SMMU by the PCIe RP using the
DTI-ATS protocol.
2. The SMMU responds to the ATS request over DTI-ATS, which is passed back to the PCIe endpoint by the
PCIe RP. If a translation fault occurs, then the response indicates the condition, and does not make any
software-visible record.
3. The PCIe endpoint uses the ATS translation to translate the address of transaction, and then issues a
transaction that is marked as ATS Translated.
An ATS Translated transaction uses the ATST flow. In all other respects, it is translated the same way as any other
transaction. Normally this translation is fast because it is already translated by ATS, but some additional translation
might still occur. For example, the SMMU can be configured to perform stage 1 translation when an ATS request is
made, and perform stage 2 translation when the ATS Translated transaction is presented to the SMMU.
ATS translations are cached in the PCIe endpoint Address Translation Cache (ATC), for future use. These
translations can be invalidated by ATS invalidation messages, which is conveyed over DTI-ATS.
If a translation fault occurs, the PCIe endpoint can issue a page request using the Page Request Interface (PRI),
before retrying the ATS translation request if the PRI request is successful. PRI is an extension to ATS, and is also
conveyed to the SMMU using DTI-ATS. The fault is not visible to LTI.
1-22 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
1 Introduction
1.4 Supported translation flows
• The SMMU ATS features are not required and not used, even though ATS is enabled in software.
Transactions are translated on-demand.
• If a translation fault occurs, no error is reported to software by the SMMU. Instead, a PRI fault response is
returned to the LTI Manager.
• When the LTI Manager receives a PRI fault response, it uses a DTI-ATS connection to issue a page request.
If the PRI response is successful, then the LTI Manager retries the transaction.
A device using this flow uses DTI-ATS for PRI requests only and does not make any ATS requests. In DTIv2, a
device can implement a DTI-ATS connection that just performs PRI requests and does not receive ATS invalidation
messages.
A device must be assigned page request credits by system software before it can issue PRI requests. These credits
are not visible to the LTI or DTI protocols and are managed by PCIe software.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 1-23
ID070124 Non-Confidential
1 Introduction
1.4 Supported translation flows
1-24 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 2
Channels
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 2-25
ID070124 Non-Confidential
2 Channels
2.1 Transaction flow
Additionally, interface management signals are included with the prefix LM.
In this specification, the term, Lx, is used to collectively refer to LA, LR, and LC.
There are no flows where any of these three stages can be skipped.
The relationship between LTI messages and the translated transaction are shown in Figure 2-1.
LA channel request
LR channel response
Transaction request
Transaction completion
LC channel completion
The LTI Subordinate does not correlate the completion messages to a specific LTI transaction, but instead counts
the number of completions corresponding to each completion tag. The purpose of the Completion channel is to
enable the LTI Subordinate to determine when all transactions with a completion tag have completed. This checking
of the number of completions for a tag is part of the translation invalidation process. There are two completion tags
to enable invalidation to take place without stopping the transaction flow.
An LTI response is permitted in the same cycle that the corresponding request is made. This response timing enables
tightly coupled TLBs with low latency.
An LTI completion is not permitted in the same cycle that the corresponding response is returned. An LTI response
can be followed by its completion in the following cycle or later.
All signals are driven by the channel TX, except LxCREDIT signals, which are driven by the channel RX.
2-26 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
2 Channels
2.1 Transaction flow
An LTI transaction is considered to be outstanding from the cycle in which the LA request is used until the cycle in
which the LC completion is issued.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 2-27
ID070124 Non-Confidential
2 Channels
2.2 Virtual Channels
The LC channel does not support multiple Virtual Channels. The LTI Subordinate must always be able to provide
a credit on the LC channel without dependence on progress of other channels.
In an LTI transaction, messages on the LA and LR channels must use the same Virtual Channel (VC).
Because LC messages are not associated with a particular VC, it is necessary that any counter in the LTI Subordinate
that is counting outstanding completions does not overflow. The LTI Subordinate must be able to track at least
65535 translation responses awaiting a completion. When this number is exceeded, the LTI Subordinate is permitted
to introduce dependencies between Virtual Channels, by not returning a translation response until translation
completions from previous translations are returned.
The intent of Virtual Channels is to enable one VC to progress when another is blocked, to avoid deadlock scenarios.
Components implementing LTI must ensure that if progress is blocked on one VC it does not result in progress being
blocked on a different VC.
In some cases, the forward progress properties of a single Virtual Channel is sufficient for an implementation.
Within a VC, LTI must make independent forward progress on all LTI transactions when:
2. The LTI Manager is able to provide a credit to the LR channel without dependence on the progress of any
other transaction.
3. The total number of translations that have sent an LTI request but haven't sent the LTI completion must not
exceed the completion tracking limit of the LTI Subordinate.
2-28 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
2 Channels
2.3 Flow control
• Each channel includes LxVALID and LxCREDIT signals. If more than one VC is supported, the LA and
LR channels include LxVC signals.
• Each cycle that LxCREDIT[n] is asserted grants one credit on VC n to the channel TX.
• The channel TX consumes a credit on VC n each cycle that LxVALID is asserted with LxVC = n.
• LxVALID cannot be asserted with LxVC = n when the channel TX has zero credits for VC n.
• The maximum number of credits that the channel RX can grant the channel TX for each VC is 15.
In addition, there must not be combinatorial paths between LxCREDIT and other signals on a channel in either
direction, such as LxVALID. This restriction has the following consequences:
• A credit cannot be used by LxVALID in the same cycle that it is granted by LxCREDIT when there are no
other credits granted.
• A credit cannot be returned on LxCREDIT in the same cycle that it is used by LxVALID when the maximum
number of credits that are permitted to be granted is reached.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 2-29
ID070124 Non-Confidential
2 Channels
2.4 Reserved encodings
Use of a Reserved encoding in a field that is not ignored is a protocol error and can lead to UNPREDICTABLE behavior.
2-30 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
2 Channels
2.5 Signal validity
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 2-31
ID070124 Non-Confidential
2 Channels
2.5 Signal validity
2-32 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 3
Properties
This chapter describes the set of LTI properties that specifies the supported behavior and interface signaling
requirements:
• LTI properties on page 3-34
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 3-33
ID070124 Non-Confidential
3 Properties
3.1 LTI properties
All LTI properties have a minimum value of 0 and have no defined maximum value, unless otherwise specified.
3-34 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
3 Properties
3.1 LTI properties
When the value of a property results in a signal being zero bits in width, that signal is omitted from the interface.
Table 3-2 shows how translations are affected by the combinations of properties LTI_GPC and LTI_MMU, and the
signal LAMMUV.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 3-35
ID070124 Non-Confidential
3 Properties
3.1 LTI properties
3-36 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 4
Request channel
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 4-37
ID070124 Non-Confidential
4 Request channel
4.1 Signals
4.1 Signals
Table 4-1 describes the signals in the LA channel.
Note
If an LTI Manager uses LAFLOW = Stall for transactions
issued downstream with order requirements, it is
recommended for the LTI Manager to set LAOGV = 1 and use
LTI order group instead of using unordered LTI requests. This
prevents reordering the LTI responses and avoids deadlock. It
is permitted to use unordered LTI requests for transactions
issued downstream without order requirements.
4-38 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
4 Request channel
4.1 Signals
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 4-39
ID070124 Non-Confidential
4 Request channel
4.1 Signals
4-40 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
4 Request channel
4.1 Signals
LAPROT Transaction LTI_MMU == True ? 3:1 Protection information. LAPROT uses the same encoding as
the AXI AxPROT signals.
LAPROT[0]: PnU
0 Unprivileged access
1 Privileged access
LAPROT[1]: NS
Used in conjunction with LANSE to define
Physical Address Space (PAS) of the
transaction.
LAPROT[2]: InD
0 Data access
1 Instruction access
When LTI_GPC is False, the PAS is encoded as LAPROT[1]
and is defined by the following:
0 Secure
1 Non-secure
When LTI_GPC is True, the PAS encoded as {LANSE
LAPROT[1]} and is defined as followed:
00 Secure
01 Non-secure
10 Root
11 Realm
If LAMMUV is HIGH and LASECSID is Non-secure, the
PAS must be Non-secure.
If LAMMUV is HIGH and LASECSID is Secure, the PAS
must be Non-secure or Secure.
If LAMMUV is HIGH and LASECSID is Realm, the PAS
must be Non-secure or Realm.
If LATRANS is SPEC or UNSPEC, LAPROT[0] must be 0.
If LATRANS is W, RW, SPEC, UNSPEC, W-CMO,
DHCMO, DCP, or W-DCP, LAPROT[2] must be 0.
If LAFLOW is ATST and LASSIDV = 0, LAPROT[0] must
be 0.
If LAFLOW is ATST and LASSIDV = 0, LAPROT[2] must
be 0.
LAPROT[0] and LAPROT[2] are not valid when
LAMMUV is LOW.
LAPROT[0] and LAPROT[2] is present only when
LTI_MMU is True.
When LTI_MMU is False, LAPROT is 1b wide and contains
the NS bit.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 4-41
ID070124 Non-Confidential
4 Request channel
4.1 Signals
LATRANS Transaction 4 Type of the transaction that the LTI request is translating.
See Transaction types on page 4-43.
4-42 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
4 Request channel
4.2 Transaction types
Note
The AMBA DTI specification permits speculative translation
requests being used for speculative read transactions in some
circumstances.
The LTI SPEC transaction type cannot be used for speculative read
transactions. The LTI SPEC transaction type prefetches a translation
into translation caches and the translation that is returned cannot be
used by transactions.
If an LTI Manager requires a speculative read transaction that is
guaranteed not to fault, then it should issue an LTI request with
LATRANS = R, LAFLOW = PRI.
1 R Read.
2 W Write.
5 R-CMO Read with Cache Maintenance Operation. R-CMO is a read that also
performs a Cache Maintenance Operation.
7 UNSPEC Hint that the translation can be deallocated and is no longer required.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 4-43
ID070124 Non-Confidential
4 Request channel
4.2 Transaction types
14 W-DCP Write with Directed Cache Prefetch. W-DCP is a write that includes
a request to stash the written data into a particular cache.
4-44 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
4 Request channel
4.3 Transaction attributes
Encoding Type
0 Device-nGnRnE
1 Device-nGnRE
2 Device-nGRE
3 Device-GRE
4 Normal Non-cacheable
Most transactions should use the value 7 for LAATTR, Normal Write-Back Allocate Outer Shareable. This value
is the common type for accessing normal memory locations when the translation tables have not selected a different
set of transaction attributes.
Table 4-4 shows the attribute restrictions for specific transaction types.
Note
No-allocate is treated as Allocate for CMO, DCMO, and DHCMO.
There is no attribute restriction for LAATTR when LATRANS is R, W, RW, SPEC, W-CMO, or UNSPEC.
Note
In Issue A and Issue B, W-CMO had attribute restrictions on LAATTR. This is no longer required for Issue C.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 4-45
ID070124 Non-Confidential
4 Request channel
4.4 Transaction scope
4-46 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 5
Response channel
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 5-47
ID070124 Non-Confidential
5 Response channel
5.1 Signals
5.1 Signals
Table 5-1 describes the signals in the LR channel.
5-48 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
5 Response channel
5.1 Signals
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 5-49
ID070124 Non-Confidential
5 Response channel
5.1 Signals
5-50 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
5 Response channel
5.1 Signals
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 5-51
ID070124 Non-Confidential
5 Response channel
5.1 Signals
5-52 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
5 Response channel
5.1 Signals
a. This rule does not apply to an LTI-B interface which has a different rule for LRHWATTR value when LAMMUV is LOW. For more details,
see Issue B.
b. This rule does not apply to an LTI-B interface which has a different rule for LRMECID value when LAMMUV is LOW. For more details,
see Issue B.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 5-53
ID070124 Non-Confidential
5 Response channel
5.2 LRRESP details
a. This is always FaultRAZWI because the transaction is always terminated without an error response. No fault is reported in the SMMU.
Translated
LATRANS LRRESP transaction Effect
type
5-54 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
5 Response channel
5.2 LRRESP details
Translated
LATRANS LRRESP transaction Effect
type
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 5-55
ID070124 Non-Confidential
5 Response channel
5.3 Attribute restrictions for specific transaction types
SPEC Device-nGnRnE
Device-nGnRE
Device-nGRE
Device-GRE
Normal Non-cacheable
There is no attribute restriction for LRATTR when LATRANS is R, W, RW, W-CMO, or UNSPEC.
Note
In Issue A and Issue B, W-CMO had attribute restrictions on LRATTR. This is no longer required for Issue C.
5-56 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 6
Completion channel
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 6-57
ID070124 Non-Confidential
6 Completion channel
6.1 Signals
6.1 Signals
Table 6-1 describes the signals in the LC channel.
6-58 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
6 Completion channel
6.2 Completion channel characteristics
All transactions using the translation must be globally observed before the completion message is sent by the LTI
Manager.
CPU barrier instructions that must wait for completion of an invalidation might block while awaiting LC messages.
The block may occur even if the translation used for that transaction has not been invalidated. If LC messages take
a long time to return, it can impact CPU performance.
It is recommended that a single LTI response is only shared between transactions that can be issued together and are
all outstanding at the same time, so that the overall latency to return the LC message is not substantially larger than
the DRAM access latency. In most situations, it is better for the LTI Manager to rely on the translation caching of
the LTI Subordinate and use a separate LTI request for each transaction, even if the LTI Manager knows that the
translation is likely to be reused.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 6-59
ID070124 Non-Confidential
6 Completion channel
6.2 Completion channel characteristics
6-60 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 7
Interface management
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 7-61
ID070124 Non-Confidential
7 Interface management
7.1 Interface management overview
7-62 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
7 Interface management
7.2 Open and close handshake
ST_CLOSED 0 0
ST_OPENING 1 0
ST_OPEN 1 1
ST_CLOSING 0 1
The LTI interface transitions through the states in the following order:
1. LMOPENREQ can transition from LOW to HIGH only if LMOPENACK is LOW.
2. LMOPENREQ can transition from HIGH to LOW only if LMOPENACK is HIGH.
3. LMOPENACK can transition from LOW to HIGH only if LMOPENREQ is HIGH.
4. LMOPENACK can transition from HIGH to LOW only if LMOPENREQ is LOW.
There must be no combinatorial paths between LMOPENACK and LMOPENREQ in either direction. A
consequence of this is that the interface must spend at least one cycle in each state before moving to the next state.
Figure 7-1 shows how LMOPENREQ and LMOPENACK correspond to the interface states.
LMOPENREQ
LMOPENACK
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 7-63
ID070124 Non-Confidential
7 Interface management
7.3 Properties of interface states
The Manager must wait for all outstanding responses on the LR channel and send all outstanding completions on
the LC channel before transitioning from state ST_OPEN to state ST_CLOSING. LMOPENREQ must be asserted
while there are outstanding transactions on the interface. The Manager must not deassert LMOPENREQ until the
cycle after it has asserted LCVALID for the completion.
LACREDIT and LCCREDIT can only be asserted in states ST_OPEN and ST_CLOSING. LACREDIT and
LCCREDIT must be deasserted when LMOPENACK is deasserted.
LRCREDIT can only be asserted in state ST_OPEN. LRCREDIT must be deasserted when LMOPENREQ or
LMOPENACK are deasserted.
All credits on all channels are lost when in state ST_CLOSED. When the state ST_OPEN is entered, each channel
TX has zero credits.
7-64 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
7 Interface management
7.4 Management Signals
7.4.1 LMASKCLOSE
The LMASKCLOSE signal enables the Subordinate to request that the interface is to be closed. For example,
LMASKCLOSE may be asserted in response to a quiescence request on a Q-Channel interface on the Subordinate.
When LMASKCLOSE is asserted by the Subordinate and LMACTIVE is deasserted by the Manager, the
Manager must, in a timely manner, either:
• Assert LMACTIVE, to enable the Manager to issue new LTI requests. The Subordinate will usually then
deassert LMASKCLOSE.
7.4.2 LMACTIVE
The LMACTIVE signal serves two purposes:
• When asserted while the interface is closed, it indicates that the system should provide clock and power to
the Subordinate and the interface can be opened.
• When asserted while the interface is opened, it indicates that the Subordinate should not request closing the
interface.
There are no protocol rules linking LMACTIVE to outstanding LTI requests, however LMACTIVE is normally
asserted while any LTI requests are outstanding.
LMACTIVE must be glitch-free and suitable for sampling in a different clock domain.
The Subordinate is permitted to remain in state ST_OPENING indefinitely when LMACTIVE is not asserted.
The Subordinate is permitted to assert LMASKCLOSE when LMACTIVE is asserted. This is because there might
be a delay between LMASKCLOSE being asserted and it affecting LMACTIVE. However, it is expected that the
Subordinate deasserts LMASKCLOSE when it detects that LMACTIVE is asserted.
The Manager is permitted to assert and deassert LMACTIVE without asserting LMOPENREQ. This is because
LMACTIVE might be driven combinatorially, before LMOPENREQ can be asserted.
• LMASKCLOSE might be asserted by the Subordinate when LMACTIVE is deasserted, but the new
activity begins at the Manager before it begins to close the LTI interface. In this case, it asserts LMACTIVE
and ignores LMASKCLOSE.
• The Manager might assert LMACTIVE to give early notice to the Subordinate to start its clocks, before the
Manager is ready for the interface to be opened.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 7-65
ID070124 Non-Confidential
7 Interface management
7.4 Management Signals
1. The Manager asserts LMACTIVE and LMOPENREQ to request opening the interface.
a. The Manager might assert LMACTIVE before LMOPENREQ.
b. It is permitted, but not expected, for the Manager to assert LMACTIVE after asserting
LMOPENACK.
2. The Subordinate asserts LMOPENACK to accept opening the interface, and asserts LACREDIT and
LCCREDIT to send request and completion credits. These can be asserted in any cycle that LMOPENACK
is asserted.
3. The Manager sees that LMOPENACK is asserted and in the next cycle, asserts LRCREDIT to send
response credits and starts providing LR credits. It also uses LA credits to start issuing requests on the LA
channel.
0 1 2 3 4
CLK
LMACTIVE
LMOPENREQ
LMOPENACK
LACREDIT[n]
LCCREDIT[n]
LRCREDIT[n]
LAVALID
1. The Subordinate observes LMACTIVE is not asserted and requests that the interface be closed by asserting
LMASKCLOSE.
2. The Manager accepts the request to close the interface by deasserting LMOPENREQ.
3. The Subordinate completes the close sequence by deasserting LMOPENACK and LMASKCLOSE.
7-66 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
7 Interface management
7.4 Management Signals
0 1 2 3 4
CLK
LMASKCLOSE
LMACTIVE
LMOPENREQ
LMOPENACK
2. The Subordinate observes LMACTIVE and withdraws the interface closing request by deasserting
LMASKCLOSE.
0 1 2 3
CLK
LMASKCLOSE
LMACTIVE
LMOPENREQ
LMOPENACK
The assertion of LMACTIVE and LMASKCLOSE are independent events, with no fixed relationship between
them. Figure 7-4 shows them being asserted in the same cycle, but this is coincidental. A combinatorial path
between the signals is not permitted.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 7-67
ID070124 Non-Confidential
7 Interface management
7.4 Management Signals
7-68 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 8
Clock and reset
This section describes the mapping strategy for the clock and reset. It contains the following section:
• Clock and reset on page 8-70
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 8-69
ID070124 Non-Confidential
8 Clock and reset
8.1 Clock and reset
Typically, an LTI interface shares its clock and reset with other interfaces on a component. For this reason, the clock
and reset signals do not have an LTI-specific prefix in this specification.
An implementation might give the clock and reset signals different names from those signals used in the
specification, or employ a different clock and reset strategy. It is recommended that there is a mapping between the
clock and reset signals in an implementation and the signals that are defined here.
The signals that are not defined as asynchronous are sampled on the rising edge of CLK.
On the first rising edge of CLK where RESETn is HIGH, the following signals must be 0:
• LxVALID
• LxCREDIT
• LMOPENREQ
• LMOPENACK
• LMASKCLOSE
8-70 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 9
Pipelining
This chapter defines pipelining requirements for LTI. It contains the following section:
• Pipelining between Manager and Subordinate interfaces on page 9-72
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 9-71
ID070124 Non-Confidential
9 Pipelining
9.1 Pipelining between Manager and Subordinate interfaces
• All signals on each of the LA, LR, and LC channels must be pipelined by the same number of cycles as all
other signals in the same channel going in the same direction.
• LMOPENREQ must be pipelined by at least as many cycles as LAVALID, LRCREDIT, and LCVALID.
• LMOPENACK and LMASKCLOSE must each be pipelined by the same number of cycles, and both by at
least as many cycles as LACREDIT, LRVALID and LCCREDIT.
It is expected that in most implementations that require pipelining, all LTI signals that go in the same direction are
pipelined by the same number of cycles.
9-72 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Chapter 10
Interoperability
This appendix describes how to connect interfaces with different properties. It contains the following sections:
• LTI-A compatibility on page 10-74
• LTI_MMU and LTI_GPC properties on page 10-75
• MPAM compatibility on page 10-76
• LAMECID and LAHWATTR signals compatibility on page 10-77
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 10-73
ID070124 Non-Confidential
10 Interoperability
10.1 LTI-A compatibility
Table 10-1 Compatibiltiy between LTI-A Manager and Subordinate with LTI-B and onwards
LTI-A
Subordinate with LTI-B and onwards
Subordinate
Manager with LTI-B Not compatible See Table 10-2 on page 10-75.
and onwards
a. The LAMECID and LAHWATTR signals are only defined on an LTI-B interface. These signals are not described in this issue of the
specification. For more details, see Issue B.
10-74 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
10 Interoperability
10.2 LTI_MMU and LTI_GPC properties
LTI Subordinate
LTI Manager
LTI_MMU = True LTI_MMU = True LTI_MMU = False
LTI_GPC = False LTI_GPC = True LTI_GPC = True
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 10-75
ID070124 Non-Confidential
10 Interoperability
10.3 MPAM compatibility
When connecting a LTI Manager with LTI_MPAM_SUPPORT = MPAM_9_1 to a LTI Subordinate with
LTI_MPAM_SUPPORT = MPAM_12_1:
• The connection of the PARTID space field LRMPAM.MPAM_SP or LRMPAM.MPAM_NS is also affected
by LTI_GPC property. See Compatibility between LTI Manager and Subordinate interfaces on page 10-75
for more details.
When connecting a LTI Manager with LTI_MPAM_SUPPORT = MPAM_12_1 to a LTI Subordinate with
LTI_MPAM_SUPPORT = MPAM_9_1:
• The connection of the PARTID space field LRMPAM.MPAM_SP or LRMPAM.MPAM_NS is also affected
by LTI_GPC property. See Compatibility between LTI Manager and Subordinate interfaces on page 10-75
for more details.
When connecting a LTI Manager with LTI_MPAM_SUPPORT != False to a LTI Subordinate with
LTI_MPAM_SUPPORT = False, the system must add MPAM information. The default is IMPLEMENTATION
DEFINED, but one option is:
• When Manager LTI_GPC is True, copy the physical address space {LRNSE, LRPROT[1]} onto Manager
LRMPAM.MPAM_SP input.
• When Manager LTI_GPC is False, copy the physical address space LRPROT[1] onto Manager
LRMPAM.MPAM_NS input.
When connecting a LTI Manager with LTI_MPAM_SUPPORT = False to a LTI Subordinate with
LTI_MPAM_SUPPORT != False, Subordinate LRMPAM output is unconnected.
10-76 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
10 Interoperability
10.4 LAMECID and LAHWATTR signals compatibility
For the compatibility of LAMECID and LAHWATTR signals between LTI-A and LTI-B interfaces, see Table 10-1
on page 10-74.
Note
The LAMECID and LAHWATTR signals are only defined on the LTI-B interface. These signals are not described
in this issue of the specification. For more details, see Issue B.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. 10-77
ID070124 Non-Confidential
10 Interoperability
10.4 LAMECID and LAHWATTR signals compatibility
10-78 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix A
Considerations for AXI5
This appendix describes how to map LTI concepts onto an AXI5 interface. It contains the following sections:
• LATRANS mapping on page A-80
• LAATTR mapping on page A-81
• LAIDENT mapping on page A-82
• LRATTR mapping on page A-83
• xRESP mapping on page A-84
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. A-79
ID070124 Non-Confidential
Appendix A Considerations for AXI5
A.1 LATRANS mapping
- StashTranslation SPEC
ReadNoSnoop, ReadOnce - R
- WriteNoSnoop, WriteUniquePtl, W
WriteUniqueFull,
WriteNoSnoopFull,
WriteDeferrable, WriteZero
- AtomicLoad, AtomicSwap, RW
AtomicCompare, AtomicStorea
ReadOnceCleanInvalid - R-CMO
- WritePtlCMO,WriteFullCMO W-CMO
MakeInvalid - DCMO
ReadOnceMakeInvalid - R-DCMO
- InvalidateHint DHCMO
- StashOnceShared, DCP
StashOnceUnique
- WriteUniquePtlStash, W-DCP
WriteUniqueFullStash
- UnstashTranslation UNSPEC
a. AtomicStore operations are defined as type RW, not W, even though no read data is returned. This is required by
the SMMUv3 architecture.
The following AXI5 transactions are not supported for mapping to LTI:
• ReadShared
• ReadClean
• WriteBackFull
• WriteEvictFull
• Prefetch
• DVM Complete
A-80 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix A Considerations for AXI5
A.2 LAATTR mapping
Table A-2 shows the recommended mapping of the AXI5 AxCACHE and AxDOMAIN signals to LAATTR
values.
When LATRANS is DCP, W-CMO, W-DCP, R-CMO, or R-DCMO, the allocation hint in LAATTR is Allocate if
the memory type in AxCACHE is Normal Non-cacheable or Write-Through.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. A-81
ID070124 Non-Confidential
Appendix A Considerations for AXI5
A.3 LAIDENT mapping
A-82 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix A Considerations for AXI5
A.4 LRATTR mapping
Table A-3 shows the recommended mapping of the LRATTR values to the AXI5 AxCACHE and AxDOMAIN
signals.
Device-nGRE
Device-GRE
It is recommended that transactions with AxBURST = FIXED are terminated with a SLVERR response. It is
recommended that Managers which are translated by an SMMU do not use the FIXED burst type.
If AxLOCK = 1, AxCACHE is not permitted to indicate a Cacheable type without additional knowledge of the
structure of the downstream interconnect. If an AXI5 transaction with AxLOCK = 1 translates to any Normal
Write-Back memory type, it is recommended that it be output with AxLOCK = 0. It is recommended that Managers
requiring semaphore-type operations use the AXI5 atomic transactions.
For WritePtlCMO and WriteFullCMO, AxDOMAIN is required to be Non-shareable or Shareable which is only
possible when LRATTR is Normal Write-Back. If LRATTR is not Normal Write-Back, WritePtlCMO and
WriteFullCMO should be converted to WriteNoSnoop.
If AWSNOOP = WriteDeferrable, AWDOMAIN is required to be SYS. If the memory type in LRATTR is Normal
Write-Back, it is recommended that the Manager terminates the transaction with a SLVERR response.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. A-83
ID070124 Non-Confidential
Appendix A Considerations for AXI5
A.5 xRESP mapping
LRRESP xRESP
FaultAbort SLVERR
FaultRAZWI OKAY
FaultPRI TRANSFAULT
A-84 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix A Considerations for AXI5
A.6 Transactions that are legal in AXI5 and illegal in LTI
• Write transactions marked as Instruction (AWPROT[2] = 1) are converted to Data (AWPROT[2] = 0).
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. A-85
ID070124 Non-Confidential
Appendix A Considerations for AXI5
A.7 Memory Tagging
When a transaction is received on the AR channel with ARMMUVALID HIGH, ARTAGOP must be 0b00, Invalid.
A-86 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix B
Considerations for DTI
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. B-87
ID070124 Non-Confidential
Appendix B Considerations for DTI
B.1 DTI_TBU_TRANS_REQ.PERM mapping
LATRANS DTI_TBU_TRANS_REQ.PERM
W, W-DCP W
RW, W-CMO RW
B-88 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix B Considerations for DTI
B.2 Special handling for specific LATRANS values
If DCP permission is not granted, convert LRRESP = Success into LRRESP = FaultRAZWI.
If neither R, W, or X permissions are not granted at the appropriate privilege level, convert LRRESP = Success into
LRRESP = FaultRAZWI.
If DCP permission is not granted, convert LRRESP = Success into LRRESP = Downgrade1.
If either W permission is not granted at the appropriate privilege level or DRE permission is not granted, convert
LRRESP = Success into LRRESP = Downgrade2.
Otherwise, if either W permission is not granted at the appropriate privilege level or DRE permission is not granted,
convert LRRESP = Success into LRRESP = Downgrade2.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. B-89
ID070124 Non-Confidential
Appendix B Considerations for DTI
B.2 Special handling for specific LATRANS values
The context for computing whether or not the permissions are legal is as follows, where resp represents the
DTI_TBU_TRANS_RESP message or the DTI_TBU_TRANS_RESPEX message:
allow_r = ‘1’;
else
dre = resp.DRE;
allow_r = effective_PnU ? resp.ALLOW_PR : resp.ALLOW_UR;
allow_w = effective_PnU ? resp.ALLOW_PW : resp.ALLOW_UW;
allow_x = effective_PnU ? resp.ALLOW_PX : resp.ALLOW_UX;
Within this context, LRRESP = Success is converted into LRRESP = FaultRAZWI if the following expressions is
true:
LAMMUV && ((!effective_InD && !allow_r) || (effective_InD && !allow_x) || !allow_w || !dre)
B-90 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix B Considerations for DTI
B.3 Attribute mapping
Table B-2 shows the meanings of the abbreviations used in this section.
Abbreviation Meaning
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. B-91
ID070124 Non-Confidential
Appendix B Considerations for DTI
B.3 Attribute mapping
For transactions with Armv8 memory type Normal-iWB-oWB, Table B-5 shows how the choice between
No-allocate and Allocate in LTI is chosen.
Although this section defines an allocation hint for all transaction types, it is ignored by the system for many
transactions. For example:
• SPEC transactions are terminated after translation is complete, and so the allocation hint is ignored.
• CMO, R-CMO, DCMO, R-DCMO, DHCMO, and W-CMO transactions are designed to de-allocate memory
locations from caches and so the allocation hint is expected to be ignored by the system.
B-92 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix B Considerations for DTI
B.3 Attribute mapping
• DCP and W-DCP transactions are explicit cache allocating transactions, so the allocation hint is expected to
be ignored by the system.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. B-93
ID070124 Non-Confidential
Appendix B Considerations for DTI
B.4 DTI_TBU_TRANS_FAULT.FAULT_TYPE mapping
DTI_TBU_TRANS_FAULT.FAULT_TYPE LRRESP
NonAbort FaultRAZWI
Abort FaultAbort
This value of DTI_TBU_TRANS_FAULT.FAULT_TYPE does
not occur when LATRANS = SPEC, DCP, or DHCMO.
TranslationPRI FaultPRI
This value of DTI_TBU_TRANS_FAULT.FAULT_TYPE does
not occur when LATRANS = SPEC, DCP, or DHCMO.
B-94 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix C
Considerations for PCIe
This appendix describes the integration for PCIe. It contains the following sections:
• PCIe integration on page C-96
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. C-95
ID070124 Non-Confidential
Appendix C Considerations for PCIe
C.1 PCIe integration
The LTI_MMU property must be True for PCIe Root Ports (RP).
Table C-1 describes how a PCIe RP should drive certain LA channel signals.
Signal Description
LAVC A PCIe RP implementation is permitted, but not required, to use multiple LTI Virtual Channels
to help break protocol dependencies. See Virtual Channels on page 2-28.
Root Ports implementing LTI interfaces can be one of two types:
1. Fully Buffered. A Fully Buffered implementation can temporarily backpressure for flow
control reasons but must not require progress of downstream transactions before it can
accept responses on the LR channel. This requires implementing a buffer large enough
to accept all outstanding LR responses.
2. Backpressuring. Backpressure implementation can stop granting credits on the LR
channel when the RP cannot issue downstream transactions into the system. As a result,
LR responses are prevented from being accepted for LA requests that have already been
issued.
It is recommended that the LTI request is performed before the point of ordering in the PCIe RP,
typically using Fully Buffered implementation.
For Fully Buffered LTI implementations, posted and non-posted requests can use the same VC.
For Backpressuring LTI implementations, different Virtual Channels are used for posted and
non-posted requests to ensure that posted requests can forward progress when non-posted
requests cannot.
Different Virtual Channels can also be used for different traffic classes.
LAOGV For Fully Buffered implementations this signal is 0, because they can accept LR channel
responses in any order.
Backpressuring implementations must use order groups to ensure that posted writes remain in
order where required.
LAFLOW If the request is an ATS translated request, this signal is 1, ATST. Otherwise this signal is 2,
NoStall.
LASID LASID[15:0] is the Requester ID, otherwise known as BDF (Bus, Device, Function).
Higher-order bits of LASID uniquely identify the PCIe segment in the StreamID space that is
used by the SMMU.
LASSIDV If the request has a PASID header, this signal is 1. Otherwise, the signal is 0.
C-96 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix C Considerations for PCIe
C.1 PCIe integration
Signal Description
LANSE This signal is the same as the T bit in the TLP. If T is 0, the PAS will be Non-secure. If T is 1,
the PAS will be Realm.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. C-97
ID070124 Non-Confidential
Appendix C Considerations for PCIe
C.1 PCIe integration
C-98 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D
Considerations for coherent interfaces
This appendix describes using LTI for transactions originated from devices with coherent interfaces, such as
CXL.cache or CHI. The requests from CXL.cache are converted to the CHI protocol before they use LTI for
translation. The coherent interfaces are expected to use translated addresses to enable the coherency protocol. The
snoop request does not come to LTI and is not covered in this specification. The transaction request comes to LTI
and does not require stage 1 or stage 2 translation. The SMMU only performs permission checks if it is configured
in such a way, including Granule Protection Checks (GPC) and Device Permission Table (DPT) checks. It contains
the following sections:
• LTI properties on page D-100
• LA mapping from CHI on page D-101
• LATRANS mapping on page D-102
• LAATTR mappings on page D-104
• LRATTR mappings on page D-105
• CHI completion response flit opcode mapping on page D-106
• Transaction flow examples on page D-107
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-99
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.1 LTI properties
D-100 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D Considerations for coherent interfaces
D.2 LA mapping from CHI
Table D-2 shows the recommended mapping of CHI request fields to LA channel signals, depending on the value
of LAMMUV.
When LAMMUV is
LA signal
0 1
LASID Not valid. LASID[15:0] is the CHI request flit, StreamID. Higher-order bits of
LASID uniquely identify the host port Segment Number in the
StreamID space that is used by the SMMU.
LAOGV It is recommended for the Host Port to maintain the order and set LAOGV to 0.
However, if the Host Port expects the LTI responses to be in order, this bit can be driven
to 1 to create a single order group for such transactions.
LAIDENT Set to 1.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-101
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.3 LATRANS mapping
ReadNoSnp R
ReadOnce
ReadOnceCleanInvalid R-CMO
ReadOnceMakeInvalid R-DCMO
WriteNoSnp W
WriteNoSnpDef
WriteNoSnpZero
WriteUniquePtl
WriteUniqueFull
WriteUniqueZero
WriteNoSnpPtl+(P)CMO W-CMO
WriteNoSnpFull+(P)CMO
WriteUniquePtl+(P)CMO
WriteUniqueFull+(P)CMO
WriteUniquePtlStash W-DCP
WriteUniqueFullStash
StashOnce* DCP
CleanShared CMO
CleanSharedPersist*
CleanInvalid
CleanInvalidPoPA
MakeInvalid DCMO
AtomicStore RW
AtomicLoad
AtomicSwap
AtomicCompare
Table D-4 on page D-103 shows the recommended mappings of the CHI request flit, Opcode, to the LATRANS
values in fully coherent transactions.
D-102 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D Considerations for coherent interfaces
D.3 LATRANS mapping
When DPT is enabled, the write access check in DPT is not enforced for fully coherent tranactions in this issue of
the specification.
ReadShared R
ReadClean
ReadNotSharedDirty
ReadUnique
ReadPreferUnique
MakeReadUnique
MakeUnique
CleanUnique
Evict
WriteEvictFull
WriteEvictOrEvict
WriteCleanFull
WriteCleanFull+(P)CMO
WriteBack
WriteBackFull+(P)CMO
The CHI protocol transaction, PrefetchTgt, is not supported for mappings to LTI.
If a PrefetchTgt transaction is received, it is recommended that the request is discarded.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-103
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.4 LAATTR mappings
Table D-5 shows the recommended mappings of the CHI request fields, MemAttr, SnpAttr, and Order to LAATTR
values.
MemAttr[3:0]
Order[1:0]
Allocate
SnpAttr
Device
EWA
D-104 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D Considerations for coherent interfaces
D.5 LRATTR mappings
Table D-6 shows the recommended mappings of the CHI request fields, MemAttr, SnpAttr, and Order to LRATTR
values.
MemAttr[3:0]
Cacheable
Order[1:0]
Allocate
SnpAttr
Device
EWA
Device-nGnRnE 1 0 0 0 0 11 Device nRnE
In instances where WriteEvictFull and WriteEvictOrEvict transactions require MemAttr to be Allocate, the LTI
Manager is recommended to ignore the allocation hint in LRATTR and output MemAttr as Allocate.
In instances where the ReadOnceMakeInvalid transaction requires MemAttr to be No-allocate, the LTI Manager is
recommended to ignore the allocation hint in LRATTR and output MemAttr as No-allocate.
When LATRANS != CMO or DCMO, the CHI transaction issued downstream is recommended to retain the
incoming SnpAttr and MemAttr attributes for Device and Cacheable.The MemAttr attributes for Allocate and EWA
can be modified by the translation.
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-105
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.6 CHI completion response flit opcode mapping
FaultAbort NDERR
FaultRAZWI OK
D-106 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D Considerations for coherent interfaces
D.7 Transaction flow examples
The examples described in these subsections do not include interactions between the HN-F and Request Node or
Subordinate Node.
The examples use PCIe ATS to translate the Virtual Address from the Device.
ATS translation
ATS Request
(Requester ID,
Untranslated Address,
T)
DTI_ATS_TRANS_REQ
(SID, IA, T, CXL)
DTI_ATS_TRANS_RESP
(OA, TE, CXL_IO) GPC
ATS Response
(Translated Address,
TE, CXL.io)
Memory transaction
ReadNotSharedDirty
(SECSID, RID, PA, NSE,NS)
LA
(SECSID, SID, PA, NSE, NS)
(MMUV=1, FLOW=ATST, IDENT=1)
DTI_TBU_TRANS_REQ
(SECSID, SID, PA, NSE, NS)
(MMUV=1, FLOW=ATST, IDENT=1)
LR
(MECID, MPAM, NSE, NS)
ReadNotSharedDirty
(PA)
(MECID, MPAM, NSE, NS)
CompData_SC
LC
CompData_SC
CompAck
CompAck
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-107
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.7 Transaction flow examples
4. The TCU sends the DTI-ATS translation response to the PCIe or CXL.io RP. The PCIe or CXL.io RP.
provides the translated PA, TO, and CXL_IO.
If CXL_IO is 0, the transaction is permitted to be presented as a CHI snoopable request.
5. The PCIe or CXL.io RP sends the ATS response to the CHI C2C Device.
6. The CHI C2C Device sends a ReadNotSharedDirty request to the Coherent Host Port.
7. The Coherent Host Port sends an LA message to the TBU with LAMMUV = 1, LAFLOW = ATST, and
LAIDENT = 1.
8. The TBU converts the LA message into a DTI-TBU translation request and sends it to the TCU.
9. The TCU performs a GPC and DPT check.
If both checks pass, the TCU sends the DTI-TBU translation response to the TBU with the translated
MECID, MPAM, and PAS information, where PAS is encoded as {NSE, NS}.
10. The TBU converts the DTI-TBU translation response to an LR message and sends it to the Coherent Host
Port.
11. The Coherent Host Port sends a ReadNotSharedDirty request to the HN-F.
12. The HN-F resolves coherency and returns a CompData_SC response to the Coherent Host Port.
13. The Coherent Host Port sends an LC message to the TBU to complete the translation.
In parallel, the Coherent Host Port also sends a CompData_SC response to the CHI C2C Device.
14. The CHI C2C Device sends a CompAck response to the Coherent Host Port.
15. The Coherent Host Port sends a CompAck response to the HN-F.
D-108 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix D Considerations for coherent interfaces
D.7 Transaction flow examples
PCIe or Coherent
CXL Device CXL.io RP Host Port TBU TCU HN-F
ATS translation
ATS Request
(Requester ID,
Untranslated Address,
T)
DTI_ATS_TRANS_REQ
(SID, IA, T, CXL)
DTI_ATS_TRANS_RESP
(OA,TE,CXL_IO) GPC
ATS Response
(Translated Address,
TE, CXL.io)
Memory Transaction
D2H DirtyEvict
(Address)
LA
(PA, NSE, NS)
(MMUV=0)
DTI_TBU_TRANS_REQ
(PA, NSE, NS)
(MMUV=0)
DTI_TBU_TRANS_RESP
(partid/pmg=0, NSE, NS) GPC
LR
(MECID=0, partid or pmg=0, NSE, NS)
WriteBackFull
(PA, NSE, NS)
(MECID, MPAM)
CompDBIDResp
LC
H2D GO+WritePull
D2H Data
CopyBackWriteData_UD_PD
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. D-109
ID070124 Non-Confidential
Appendix D Considerations for coherent interfaces
D.7 Transaction flow examples
10. The TBU converts the DTI-TBU translation response to an LR message and sends it to the Coherent Host
Port, with MECID = 0, MPAM PARTID = 0, and PMG = 0.
11. The Coherent Host Port sends a WriteBackFull request to the HN-F.
12. The HN-F resolves coherency and returns a CompDBIDResp response to the Coherent Host Port.
13. The Coherent Host Port sends an LC message to the TBU to complete the translation.
In parallel, the Coherent Host Port also sends a H2D combined GO_WritePull message to the CHI C2C
Device.
14. The CHI C2C Device sends a D2H Data message to the Coherent Host Port.
15. The Coherent Host Port sends a CopyBackWriteData_UD_PD response to the HN-F.
D-110 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix E
Signal list
This appendix describes which signals are present on LTI-A and LTI-B interfaces. It contains the following sections:
• Signal list on page E-112
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. E-111
ID070124 Non-Confidential
Appendix E Signal list
E.1 Signal list
LTI issue
Signal Presence
A
B C
A.b
CLK - O O O
RESETn - O O O
LAVALID - Y Y Y
LACREDIT - Y Y Y
LAOGV - Y Y Y
LAMMUV - N Y Y
LAFLOW LTI_MMU Y O O
LAIDENT LTI_MMU N O O
LASECSID LTI_MMU Y O O
LAPROT[2] LTI_MMU Y O O
LAPROT[1] - Y Y Y
LAPROT[0] LTI_MMU Y O O
LANSE LTI_GPC N O O
LAADDR - Y Y Y
LATRANS - Y Y Y
LAATTR - Y Y Y
E-112 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix E Signal list
E.1 Signal list
Table E-1 Summary of signal presence for each LTI version (continued)
LTI issue
Signal Presence
A
B C
A.b
LAHWATTRa LTI_LAHWATTR_PRESENTa N O N
LRVALID - Y Y Y
LRCREDIT - Y Y Y
LRCTAG - Y Y Y
LRRESP - Y Y Y
LRPROT[2] LTI_MMU Y O O
LRPROT[1] - Y Y Y
LRPROT[0] LTI_MMU Y O O
LRNSE LTI_GPC N O O
LRADDR - Y Y Y
LRATTR - Y Y Y
LRHWATTR - Y Y Y
LCVALID - Y Y Y
LCCREDIT - Y Y Y
LCCTAG - Y Y Y
LMOPENREQ - Y Y Y
LMOPENACK - Y Y Y
LMACTIVE - Y Y Y
LMASKCLOSE - Y Y Y
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. E-113
ID070124 Non-Confidential
Appendix E Signal list
E.1 Signal list
E-114 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124
Appendix F
Revisions
This appendix describes the technical changes between related issues of this specification.
Change Location
Change Location
Support for Realm Management Extension (RME): Table 3-1 on page 3-34
• Root and Realm address spaces Chapter 4 Request channel
• Granule Protection Check (GPC) Chapter 5 Response channel
Support for Memory Encryption Contexts (MEC) Table 3-1 on page 3-34
Chapter 4 Request channel
Chapter 5 Response channel
ARM IHI0089C Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. F-115
ID070124 Non-Confidential
Appendix F Revisions
Change Location
Change Location
LRMPAM is extended for more Partition ID values Table 5-1 on page 5-48
Memory attributes tightened for an ATST transaction Table 5-1 on page 5-48
with LAIDENT = 1
F-116 Copyright © 2020, 2021, 2023, 2024 Arm Limited or its affiliates. All rights reserved. ARM IHI0089C
Non-Confidential ID070124