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Phase-Locked Loops
 IEEE Press
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IEEE Press Editorial Board

Sarah Spurgeon, Editor in Chief

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Anjan Bose Jim Lyke Diomidis Spinellis
James Duncan Hai Li Adam Drobot
Amin Moeness Brian Johnson Tom Robertazzi
Desineni Subbaram Naidu Ahmet Murat Tekalp
Phase-Locked Loops

System Perspectives and Circuit Design Aspects

Woogeun Rhee and Zhiping Yu

Tsinghua University
Beijing, China
Copyright © 2024 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved.

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Library of Congress Cataloging-in-Publication Data Applied for:

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Cover Design: Wiley

Cover Image: © Tuomas A. Lehtinen/Getty Images

Set in 9.5/12.5pt STIXTwoText by Straive, Chennai, India

 To my parents and my wife, Soojung, and
To my acacemic adviser Prof. Bang-Sup Song
Woogeun Rhee

To my academic advisers Prof. Zhijian Li of Tsinghua University, and

Prof. Robert W. Dutton of Stanford University
Zhiping Yu
 vii

Contents

Preface xiii
About Authors xv

1 Introduction 1
1.1 Phase-Lock Technique 1
1.2 Key Properties and Applications 2
1.2.1 Frequency Synthesis 3
1.2.2 Clock-and-Data Recovery 3
1.2.3 Synchronization 4
1.2.4 Modulation and Demodulation 5
1.2.5 Carrier Recovery 6
1.2.6 Frequency Translation 6
1.3 Organization and Scope of the Book 6
Bibliography 7

Part I Phase-Lock Basics 9

2 Linear Model and Loop Dynamics 11

2.1 Linear Model of the PLL 11
2.2 Feedback System 13
2.2.1 Basics of Feedback Loop 13
2.2.2 Stability 15
2.3 Loop Dynamics of the PLL 16
2.3.1 First-Order Type 1 PLL 16
2.3.2 Second-Order Type 1 PLL 17
2.3.3 Second-Order Type 2 PLL 19
2.3.4 Natural Frequency and Damping Ratio 21
viii Contents

2.3.5 High-Order PLLs 23

2.3.6 Bandwidth of PLL 23
2.3.7 Loop Gain and Natural Frequency 24
2.3.8 3-dB Bandwidth 25
2.3.9 Noise Bandwidth 25
2.4 Noise Transfer Function 26
2.5 Charge-Pump PLL 29
2.5.1 High-Order CP-PLL 32
2.5.2 Control of Loop Parameters 34
2.5.3 Another Role of Shunt Capacitor 34
2.6 Other Design Considerations 39
2.6.1 Time-Continuous Approximation 39
2.6.2 Practical Design Aspects 39
References 41

3 Transient Response 43
3.1 Linear Transient Performance 44
3.1.1 Steady-State Phase Response 44
3.1.2 Transient Phase Response 46
3.1.3 Settling Time 48
3.2 Nonlinear Transient Performance 52
3.2.1 Hold-In Range 53
3.2.2 Pull-In Range 53
3.2.3 Lock-In Range 55
3.2.4 Nonlinear Phase Acquisition 55
3.3 Practical Design Aspects 56
3.3.1 Type 1 and Type 2 PLLs with Frequency-Step Input 57
3.3.2 State-Variable Model 58
3.3.3 Two-Path Control in the CP-PLL 59
3.3.4 Two-Path Control in DPLL 61
3.3.5 Slew Rate of CP-PLL 62
3.3.6 Effect of the PFD Turn-On Time 64
References 65

Part II System Perspectives 67

4 Frequency and Spectral Purity 69

4.1 Spur Generation and Modulation 69
4.1.1 Spurious Signal (Spur) 69
4.1.2 Reference Spur 77
 Contents ix

4.2 Phase Noise and Random Jitter 87

4.2.1 Phase Noise Generation and Measurement 87
4.2.2 Integrated Phase Noise 93
4.2.3 Optimum Loop Bandwidth for Phase Noise 96
References 100

5 Application Aspects 101

5.1 Frequency Synthesis 102
5.1.1 Direct Frequency Synthesis 102
5.1.2 Indirect Frequency Synthesis by Phase Lock 103
5.1.3 Frequency Synthesizer Architectures for Fine Resolution 106
5.1.4 System Design Aspects for Frequency Synthesis 108
5.2 Clock-and-Data Recovery 112
5.2.1 Wireline Transceiver with Serial Link 112
5.2.2 Clock Recovery and Data Retiming by PLL 114
5.3 Clock Generation 120
5.3.1 System Design Aspects 120
5.3.2 Clock Jitter for Wireline Systems 123
5.4 Synchronization 127
5.4.1 PLL for Clock De-skewing 127
5.4.2 Delay-Locked Loop 128
References 132

Part III Building Circuits 135

6 Phase Detector 137

6.1 Non-Memory Phase Detectors 137
6.1.1 Multiplier PD 137
6.1.2 Exclusive-OR PD 139
6.1.3 Flip-Flop PD 139
6.1.4 Sample-and-Hold PD 140
6.1.5 Sub-Sampling PD 141
6.2 Phase-Frequency Detector 142
6.2.1 Operation Principle 143
6.2.2 Dead-Zone Problem 145
6.2.3 Effect of the PFD Turn-On Time on PLL Settling 147
6.2.4 Noise Performance of PFD 147
6.3 Charge Pump 149
6.3.1 Circuit Design Considerations 149
6.3.2 Single-Ended Charge Pump Circuits 154
x Contents

6.3.3 Semi- and Fully Differential Charge Pump Circuits 157

6.3.4 Design of Differential Loop Filter 160
References 164

7 Voltage-Controlled Oscillator 165

7.1 Oscillator Basics 166
7.1.1 Oscillation Condition 166
7.1.2 Quality Factor 167
7.1.3 Frequency Stability 170
7.1.4 Effect of Circuit Noise 171
7.1.5 Leeson’s Model and Figure-of-Merit 173
7.1.6 Effect of Noise Coupling 174
7.2 LC VCO 175
7.2.1 Design Considerations 175
7.2.2 LC VCO Circuit Topologies 184
7.3 RING VCO 190
7.3.1 Design Aspects 191
7.3.2 Phase Noise 192
7.3.3 Circuit Implementation 196
7.4 Relaxation VCO 201
7.4.1 Relaxation Oscillator with Ground Capacitor 201
7.4.2 Relaxation Oscillator with Floating Capacitor 202
References 205

8 Frequency Divider 209

8.1 Basic Operation 209
8.1.1 Frequency Division with Prescaler 209
8.1.2 Standard Configuration of Prescaler-based Frequency
Divider 212
8.1.3 Operation Principle of Dual-Modulus Divider 215
8.2 Circuit Design Considerations 219
8.2.1 Frequency Divider with Standard Logic Circuits 219
8.2.2 Frequency Divider with Current-Mode Logic
Circuits 220
8.2.3 Critical Path of Modulus Control 226
8.3 Other Topologies 229
8.3.1 Phase-Selection Divider 229
8.3.2 Phase-Interpolated Fractional-N Divider 230
8.3.3 (2k + M) Multi-Modulus Divider 231
8.3.4 Regenerative Divider 232
References 234
 Contents xi

Part IV PLL Architectures 237

9 Fractional-N PLL 239

9.1 Fractional-N Frequency Synthesis 239
9.1.1 Basic Operation 239
9.1.2 Spur Reduction Methods 243
9.1.3 Multi-Loop Hybrid Frequency Synthesis 248
9.2 Frequency Synthesis with Delta-Sigma Modulation 249
9.2.1 ΔΣ Modulation 250
9.2.2 All-Digital ΔΣ Modulators for Fractional-N Frequency
Synthesis 255
9.2.3 Phase Noise by Quantization Error 261
9.2.4 Dynamic Range and Bandwidth 265
9.2.5 Nonideal Effects 267
9.2.6 Practical Design Aspects for the ΔΣ Fractional-N PLL 270
9.3 Quantization Noise Reduction Methods 271
9.3.1 Phase Compensation 272
9.3.2 Noise Filtering 273
9.4 Frequency Modulation by Fractional-N PLL 278
9.4.1 One-Point Modulation 278
9.4.2 Two-Point Modulation 279
References 281

10 Digital-Intensive PLL 287

10.1 DPLL with Linear TDC 288
10.1.1 Loop Dynamics 289
10.1.2 TDC 295
10.1.3 DCO 299
10.2 DPLL with 1-Bit TDC 304
10.2.1 Loop Behavior of BB-DPLL 304
10.2.2 Fractional-N BB-DPLL 308
10.2.3 Different Design Aspects of BB-DPLL 310
10.3 Hybrid PLL 315
10.3.1 Hybrid Loop Control 316
10.3.2 Design Aspects of the HPLL 318
References 320

11 Clock-and-Data Recovery PLL 325

11.1 Loop Dynamics Considerations for CDR 325
11.1.1 JGEN and Noise Sources 325
11.1.2 JTRAN and Jitter Peaking 326
11.1.3 JTOR and Jitter Tracking 327
xii Contents

11.2 CDR PLL Architectures Based on Phase Detection 329

11.2.1 CDR with Linear Phase Detection 329
11.2.2 CDR with Binary Phase Detection 333
11.2.3 CDR with Baud-Rate Phase Detection 338
11.3 Frequency Acquisition 340
11.3.1 Frequency Detector 341
11.3.2 CDR PLL with Frequency Acquisition Aid Circuits 343
11.4 DLL-assisted CDR Architectures 344
11.4.1 Delay- and Phase-Locked Loop (D/PLL) 345
11.4.2 Phase- and Delay-Locked Loop (P/DLL) 348
11.4.3 Digital DLL with Phase Rotation 349
11.5 Open-Loop CDR Architectures 351
11.5.1 Blind Oversampling CDR 352
11.5.2 Burst-Mode CDR 353
References 355

Index 359
 xiii

Preface

Over 15 years of giving a phase-locked loop (PLL) course to graduate students,

the authors felt a strong need for one textbook that covers PLL basics, system per-
spectives, practical design aspects for integrated circuits, and PLL architecture for
both wireless and wireline communication systems. Without such a book, the PLL
lecture had to be given based on several textbooks. Even though there are many
PLL books available for circuit designers, most of them can be classified into three
types. The first one is a theory-oriented book that describes the PLL based on con-
trol and communication theories but lacks circuit details. The second type of book
deals with more circuits but is mostly based on discrete circuits, not covering prac-
tical design issues over on-chip variability or modern PLL architectures such as
fractional-N PLLs. The last one is a circuit-oriented book but does not describe a
PLL from system basics to circuit design aspects for diverse applications with an
integrated step-by-step format.
This book combines bottom-to-top and top-to-bottom approaches to address
the system and circuit design aspects of the PLL, covering essential materials for
circuit designers, from fundamentals to practical design aspects. Compared with
circuit-oriented PLL books, this book has substantial material on system design
considerations in addition to circuit design aspects for wireless and wireline
applications. Unlike other PLL books from the area of communication systems,
this book mainly focuses on the linear behaviors of the PLL and describes them in
an intuitive way without deriving mathematical analyses and equations in detail,
while touching system analyses tailored for circuit designers. Below are some
examples.
● Is the critical damping ratio of loop dynamics ever used for on-chip PLL design?

● Is the natural frequency 𝜔 from control theory as meaningful as the loop gain
n
to circuit designers?
● Is the type 2 PLL with other phase detectors as well as the phase-frequency detec-

tor (PFD) able to provide the infinite range of frequency acquisition if not limited
xiv Preface

by circuits? Does the PFD behave like other phase detectors after frequency
acquisition?
● Do we implement the second-order type 2 charge-pump PLL in practice? Why
should we consider third-order or fourth-order type 2 charge-pump PLLs in
most cases?
● How to consider a peak-to-peak jitter budget from random jitter if the random
jitter is unbounded in theory?
● How to analyze clock jitter in the frequency domain? How to relate phase noise
and sidebands to the time-domain jitter?
● Do we care about frequency-domain sidebands for clock generation if their level
is lower than the carrier power by 40 dB?
● Is the digital-intensive phase-locked loop (DPLL) totally a new PLL architecture
that requires z-domain analysis?
The first half of the book covers system basics, while the second half deals with
hardware implementation. In the first half, PLL basics and system design consid-
erations are discussed. In addition to the linear and transient behaviors of the PLL,
analyzing clock jitter in the frequency domain is deeply explained. In addition,
the book addresses system design trade-offs for three key applications: frequency
synthesis, clock-and-data recovery, and clock generation/synchronization. In the
second half, building circuits and PLL architectures for the three applications
are discussed by considering system and circuit design aspects. Also, frequency
generation and modulation circuits based on analog, digital-intensive, and hybrid
PLL architectures are described. Learning system architectures and circuit design
trade-offs in wireless and wireline systems, readers will gain the knowledge of
where and how to design the PLL for a broad range of applications.
The authors would like to thank Su Han, Xuansheng Ji, Luhua Lin, Longhao
Kuang, Qianxian Liao, and Liqun Feng in the School of Integrated Circuits at
Tsinghua University for a lot of help drawing figures. Special thanks to Liqun Feng
who not only reviewed technical details with valuable comments but also provided
many simulation plots.

Beijing, China Woogeun Rhee

Zhiping Yu
 xv

About Authors

Woogeun Rhee, Ph.D., is a Professor at the School of Integrated Circuits,

Tsinghua University, Beijing. He has over 25 years of professional career in inte-
grated circuit design with nearly 10 years in industry and 17 years in academia.
Dr. Rhee has worked on PLL architectures and circuits not only with different
careers (academia and industry) but also over different fields (wireless and
wireline systems). He is an IEEE Fellow.

Zhiping Yu, Ph.D., is a Professor at the School of Integrated Circuits, Tsinghua

University, Beijing. He is an IEEE Life Fellow with over 400 published papers on
subjects related to ICCAD, nanoelectronics, and RF circuit design.
 1

Introduction

1.1 Phase-Lock Technique

A basic concept of a phase-locked feedback system for frequency generation was
proposed in the early 1930s, but the use of a phase-locked loop (PLL) circuit for
mass production began with analog television systems in the 1940s. Since then, the
PLL has been one of the most critical building blocks in modern communication
IC systems, covering both wireless and wireline applications.
What is the main function of the PLL? From the name and a block diagram
shown in Fig. 1.1, it can be deduced that it is the loop that performs a phase lock
between a reference clock and an output clock. In the coherent communication
systems that use the amplitude and phase information of a signal for modulation
and demodulation, interestingly, the phase-lock has not been the primary goal of
the PLL in most cases. Let us look at some descriptions of the PLL in other books.
● A circuit synchronizing an output signal (generated by an oscillator) with a
reference or input signal in frequency as well as in phase [Best].
● A circuit that synchronizes the signal from an oscillator with a second input
signal, so that they operate at the same frequency [Egan].
● When the loop is (phase) locked, the control voltage sets the average frequency
of the oscillator exactly equal to the average frequency of the input signal
[Gardner].
● Basically, an oscillator whose frequency is locked onto some frequency compo-
nent of an input signal, which is done with a feedback control loop [Wolaver].
The first description addresses the basic function of the PLL both in phase and
frequency domains. In the second or the third description, the goal of the PLL is
to achieve the same frequency as the input frequency by using a phase-lock tech-
nique. In the last description, the phase lock was not even mentioned, and the
PLL was simply defined as an oscillator whose frequency is locked to the input
frequency. As implied by those descriptions, we can see that the primary goal of

Phase-Locked Loops: System Perspectives and Circuit Design Aspects, First Edition.
Woogeun Rhee and Zhiping Yu.
© 2024 The Institute of Electrical and Electronics Engineers, Inc. Published 2024 by John Wiley & Sons, Inc.
2 1 Introduction

Figure 1.1 Accurate frequency control by a phase-lock technique.

the PLL is not the phase-lock but the frequency-lock. This is because the frequency
offset between an input signal and a local oscillator in the coherent receiver system
is much more serious than the phase offset problem.
If the main goal of the PLL is to achieve the frequency-lock, we may wonder if a
frequency-locked loop (FLL) should be used instead of the PLL. The reason is that
the FLL still generates a static frequency error if there exist circuit mismatches,
a limited loop gain at DC, or a limited resolution in a frequency detector. To the
contrary, the PLL generates a static phase error rather than the frequency error
in the presence of a limited loop gain at DC or imperfect matching in a phase
detector circuit. Since the frequency error f e is the derivative of the phase error 𝜃 e ,
the PLL always achieves a zero-frequency error even with the presence of a static
phase error illustrated in Fig. 1.1. In other words, the PLL guarantees that the
accuracy of an output frequency is the same as that of a source frequency based
on the phase-lock technique. From that point of view, the PLL can be referred
as a phase-locking loop rather than the phase-locked loop since the phase-lock is
not the goal but an active method to achieve the frequency-lock. This explains
why the PLL has been dominantly employed in the coherent communication
system where the frequency offset between a carrier and a local oscillator is
critical. When the PLL is used for frequency generation, we may regard the PLL
as the oscillator circuit that generates an adaptive DC control voltage V ctr to an
internal voltage-controlled oscillator (VCO) so that a stable output frequency
is maintained over process-voltage-temperature (PVT) variations as depicted
in Fig. 1.1.

1.2 Key Properties and Applications

In addition to the zero-frequency error, there is another important property.
The PLL is the only device that performs auto-tracking band-pass filtering with
 1.2 Key Properties and Applications 3

high-quality factor Q and wide tunability. The high-Q band-pass filtering with
wide tunability is possible since the bandwidth of a PLL can be independently
set without limitation to an output frequency, while the tunability is determined
by the tuning range of a VCO regardless of the PLL bandwidth. This feature is
well utilized for clock-and-data recovery (CDR) systems to extract a clean clock
from a noisy input data. In the CDR system, the phase-lock property is also used
to define an optimum edge-of-clock position for data retiming. Besides those
two properties, the inherent property of the PLL, phase-lock, makes the PLL
play an important role in modern wireline communication systems. As data rate
or clock frequency increases, clock de-skewing or phase synchronization has
become critical to enhance the data throughput of serial I/O interfaces since the
advent of the monolithic PLL implemented with complementary metal-oxide
semiconductor (CMOS) technology in the late 1980s. Below is the summary of
three fundamental properties of the PLL:
● Zero-frequency error
● High-Q auto-tracking BPF
● Phase synchronization
With those three features, the PLL has been employed for diverse communica-
tion systems. We briefly introduce several applications of the PLL, and some key
applications will be discussed in detail in later chapters.

1.2.1 Frequency Synthesis

Since the PLL enables the zero-frequency offset between a reference clock and a
feedback clock, this feature can be used to generate multiple output frequencies
by adding counters in the reference clock path and the feedback clock path of the
PLL. As depicted in Fig. 1.2(a), with a fixed reference frequency f ref , the output
frequency f out can be set by simply changing the counting values of the digital
counters, that is, M and N in the reference-path and the feedback-path counters,
respectively. Then, we obtain f out given by N × (f ref /M) since the feedback fre-
quency (= f out /N) must be equal to the phase-detector frequency f PD (= f ref /M)
after the phase-lock. Therefore, the frequency accuracy of the PLL is as good as
that of the stable reference source which is typically a crystal oscillator.

1.2.2 Clock-and-Data Recovery

There are three main roles of the PLL for CDR systems. Firstly, a phase detector
of the PLL directly extracts a clock information from a non-return-to-zero (NRZ)
data without requiring other nonlinear circuits such as a differentiator followed by
a squarer as done in traditional CDR systems. Secondly, the PLL acts as a high-Q
4 1 Introduction

Figure 1.2 Three key applications of the PLL: (a) frequency synthesis; (b) CDR; and
(c) synchronization.

auto-tracking band-pass filter to recover a clean clock from noisy incoming data
by rejecting high-frequency jitter. Thirdly, the PLL recovers the data by re-timing
the data with the extracted clean clock. The data retiming is normally performed
with a D-type flip-flop (DFF). The phase-lock feature is also utilized for the data
re-timing. For example, the falling edge of a recovered clock is used to trigger the
DFF when the transition edge of the NRZ data is synchronized to the rising edge of
the recovered clock, which gives an optimum clock position for bit slicing, i.e. data
retiming as illustrated in Fig. 1.2(b).

1.2.3 Synchronization
Clock jitter has become more important than ever for input/output (I/O) links
in recent chip-to-chip communications as clock speed increases. In addition to
the clock jitter, a clock skew between an internal clock and an external clock is
a concern with high clock frequency. The delay variation due to a big clock tree
in a chip significantly increases a worst-case clock skew, making available phase
margin much less than expected. By having the clock tree as the part of a PLL,
the clock skew variation between the external clock CK ext and the internal clock
CK int due to the clock tree can be minimized as illustrated in Fig. 1.2(c). Since the
 k

1.2 Key Properties and Applications 5

frequency offset is negligible in the chip-to-chip communication, a delay-locked

loop (DLL) having a voltage-controlled delay line can also be used to achieve better
power supply rejection and more flexible clock control than the PLL.

1.2.4 Modulation and Demodulation

In modern transceiver systems, the PLL plays an important role not only as a
local oscillator but also as a frequency/phase modulator. These days, digital fre-
quency/phase modulation based on a fractional-N PLL, as shown in Fig. 1.3(a),
greatly simplifies the transmitter architecture. We will discuss how a direct-digital
modulation is achieved by the PLL in Chapter 9. Figure 1.3(b) also shows two
cases of an FM demodulator and a PM demodulator. For the modulations and the
frequency demodulation, the bandwidth of the PLL needs to be wide enough to
track the frequency/phase variation. To the contrary, a very narrow bandwidth of
the PLL is required to provide an averaged reference phase over a frequency drift
for the phase demodulation. The narrow-bandwidth PLL is not desirable for an
on-chip design as the phase noise contribution of a VCO becomes too high, which
will be learned later.

k k

Figure 1.3 Other applications: (a) modulation; (b) demodulation; (c) carrier recovery and
(d) frequency translation.

k
6 1 Introduction

1.2.5 Carrier Recovery

A good example of a PLL-based carrier recovery system can be found in analog
television systems. Figure 1.3(c) shows the simplified block diagram of a color-
signal demodulator. A color-burst signal is embedded as a sub-carrier and used
as a reference phase for the color-signal demodulation. The PLL generates a
reference clock whose phase is synchronized to that of the color-burst signal.
The phase difference between each color signal and the reference clock is used
to provide different color information. Therefore, a narrow-bandwidth PLL using
a highly stable VCO such as a voltage-controlled crystal oscillator (VCXO) is
designed. In addition to the carrier recovery, additional PLLs are used for horizon-
tal synchronization (H-sync) and vertical synchronization (V-sync) in the analog
television system. Since the PLL was a versatile building block in the television
system for mass production, many practical architectures and circuit techniques
were developed, including a phase-frequency detector (PFD), a charge-pump
PLL, an all-digital PLL with a numerically controlled oscillator (NCO), and so on.

1.2.6 Frequency Translation

A frequency-translation circuit offers a flexible frequency planning for frequency
generation systems. As shown in Fig. 1.3(d), instead of having a large-value
frequency divider, a mixer is put in a feedback path with another local oscillator
(LO), making a phase-detector frequency f PD become an intermediate fre-
quency f IF . Therefore, an LO frequency (f LO ) is effectively translated to a desired
output frequency. With a high f PD and the absence of a frequency divider, a
wide-bandwidth PLL can be designed with low phase noise contribution from the
LO and the reference source. Figure 1.3(d) shows an example of how a low-noise
frequency synthesizer is implemented with the frequency-translation loop where
fine frequency resolution is achieved by having another PLL or a direct-digital
frequency synthesizer as the LO.

1.3 Organization and Scope of the Book

This book consists of four major parts, covering basic theories, system and appli-
cation perspectives, circuit design aspects, and PLL architectures. In the first part,
the essential basics of the PLL for circuit designers are described. The linear and
transient behaviors of the PLL are discussed in Chapters 2 and 3, respectively. In
the second part, Chapter 4 describes system design parameters by discussing the
relationship between clock and frequency in the time and frequency domains.
Based on the system knowledge gained from previous chapters, Chapter 5
 Bibliography 7

discusses system perspectives for three key applications; frequency synthesis,

clock-and-data recovery, and synchronization. The content of Chapter 5 is rather
advanced and can be considered a reference for Chapters 9 and 11. Chapters 6–8
of the third part describe building blocks, putting emphasis on basic operation
principles and practical design aspects for integrated circuit design. In the last
part, various PLL architectures for different applications are discussed. We begin
with fractional-N PLL architectures in Chapter 9, move to digital-intensive PLL
architectures in Chapter 10, and discuss CDR PLL architectures in Chapter 11.
This book puts more weight on the traditional PLL architectures and their
analyses for frequency generation and expands the discussion of circuits and
design trade-offs for other PLL architectures. This is not the thick PLL book that
contains all details of system theories and circuit details but could be one of the
PLL books that cover essential materials with balanced system perspectives and
circuit design aspects for circuit and system designers. Other valuable resources
are listed below.

Bibliography

1 R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, 5th ed.,

McGraw-Hill, New York, 2003.
2 W. Egan, Frequency Synthesis by Phase Lock, 2nd ed., Wiley, New York, 2000.
3 W. Egan, Phase-Locked Basics, 2nd ed., Wiley, Hoboken, NJ, 2008.
4 K. Feher, Telecommunications Measurements, Analysis, and Instrumentation,
Prentice-Hall, Englewood Cliffs, NJ, 1987.
5 F. M. Gardner, Phaselock Techniques, 3rd ed., Wiley, Hoboken, NJ, 2005.
6 V. F. Kroupa, Frequency Synthesis: Theory, Design et Applications, Wiley, New
York, 1973.
7 V. F. Kroupa, Phase Lock Loops and Frequency Synthesis, Wiley, Hoboken, NJ,
2007.
8 T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge
University Press, United Kingdom, 1997.
9 W. C. Lindsey and C. M. Chie (eds), Phase-Locked Loops, IEEE Press, New
York, 1986.
10 V. Manassewitsch, Frequency Synthesizers, Theory and Design, 3rd ed., Wiley,
New York, NY, 1987.
11 H. Meyr and G. Ascheid, Synchronization in Digital Communications, Phase-,
Frequency-Locked Loops, and Amplitude Control, Wiley, New York, 1990.
12 B. Razavi (ed.), Monolithic Phase-Locked Loops and Clock Recovery Circuits,
IEEE Press, New York, 1996.
8 1 Introduction

13 B. Razavi (ed.), Phase-Locking in High-Performance Systems, IEEE Press, New

York, and Hoboken, NJ: Wiley, 2003.
14 B. Razavi, RF Microelectornics, 2nd ed., Prentice Hall, Upper Saddle River, NJ,
2012.
15 B. Razavi, Design of Integrated Circuits for Optical Communications, Wiley,
New York, 2012.
16 B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architec-
ture Level, Cambridge University Press, United Kingdom, 2020.
17 W. Rhee (ed.), Phase-Locked Frequency Generation and Clocking: Architec-
tures and Circuits for Modern Wireless and Wireline Systems, The Institution of
Engineering and Technology, United Kingdom, 2020.
18 U. L. Rohde, Microwave and Wireless Frequency Synthesizers: Theory and
Design, Wiley, New York, 1997.
19 K. Shu and E. Sanchez-Sinencio, CMOS PLL Synthesizers; Analysis and Design,
Springer, New York, 2005.
20 R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in
Deep-Submicron CMOS, Wiley, Hoboken, NJ, 2006.
21 D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, Englewood
Cliffs, NJ, 1991.
 9

Part I

Phase-Lock Basics
 11

Linear Model and Loop Dynamics

For circuit designers, it would be more meaningful to consider the practical design
aspects of a PLL for various applications than understanding complete mathemat-
ical descriptions originated from communication systems (knowing those would
be useful though). It is because desired loop parameters for the on-chip PLL design
over process, temperature, and voltage (PVT) variations could be different from
what we would have obtained based on theoretical analyses. Indeed, designing
a robust PLL with optimum system parameters is valuable in integrated-circuit
systems rather than designing a best PLL under ideal conditions. Experienced PLL
circuit designers seldom design a critically damped loop but consider either an
overdamped or underdamped loop in practice.

2.1 Linear Model of the PLL

A feedback system is basically a nonlinear system. Then, why are we interested
in the linear model of a PLL? It is because most system performances in which
we are interested are determined when the PLL operates within a lock-in range,
that is, the PLL maintains a small phase error and does not exceed the linear
range of a phase detector. Good examples are phase noise and static phase error
performances. In the design of a PLL circuit, nonlinear analyses are used mainly
to describe the transient response of the PLL before fully settled. In other words,
we are mostly interested in the small-signal behavior of a PLL after a large-signal
transient response is fully settled.
Figure 2.1 shows the basic linear model of a PLL. A phase detector (PD) com-
pares the phases of an input signal and a VCO signal, and it generates the voltage
that is proportional to the phase difference. The PD gain K d is measured in units of
volts per radian, that is V/rad. Depending on the PD type, a free-running voltage
V do , that is, a fixed DC voltage generated with a zero-phase error appears in the PD

Phase-Locked Loops: System Perspectives and Circuit Design Aspects, First Edition.
Woogeun Rhee and Zhiping Yu.
© 2024 The Institute of Electrical and Electronics Engineers, Inc. Published 2024 by John Wiley & Sons, Inc.
12 2 Linear Model and Loop Dynamics

Figure 2.1 Linear model of the PLL.

transfer function as depicted in Fig. 2.1. In the linear model of the PLL, only the
slope and the linear range of the PD transfer function are considered. A loop filter
is the low-pass filter (LPF) that rejects high-frequency noise in the loop. Ultimately,
we need a very narrow bandwidth to tune the output frequency of a VCO with a
DC-like voltage, but the 3-dB corner frequency of the loop filter cannot be too low
because of other noise considerations. The transfer function of the loop filter F(s)
determines the type and order of a PLL. A VCO is the oscillator that modulates
the frequency in response to a control voltage. The VCO gain K v is defined by a
frequency change to an input-voltage change, measured in units of radians per
second per volt, that is rad/s/V, or hertz per volt, that is Hz/V. A free-running fre-
quency 𝜔c is the output frequency of the VCO with a floating control voltage but
often refers to the center frequency of the VCO tuning range.
In the linear model, we note that there is an integrator, 1/s, in the VCO model. It
is not because the VCO performs integration during voltage-to-frequency conver-
sion but because the phase is used as an error estimate in the loop. Figure 2.2 shows
an equivalent liner model of the PLL and explains how the integrator is embedded
in the VCO. For example, let us consider a frequency-locked loop (FLL) where a
frequency detector generates a frequency error to control the VCO. In the linear
model of the FLL shown in Fig. 2.3, the integrator is not put in the VCO even if the
same VCO circuit is used. Accordingly, the FLL is more stable than the PLL for a
 2.2 Feedback System 13

Figure 2.2 Understanding 1/s in the linear model of the PLL.

Figure 2.3 Linear model of the FLL.

given loop bandwidth. However, the FLL suffers from the frequency error problem
as discussed in Chapter 1.

2.2 Feedback System

Feedback is essential in analog circuit design. One of the reasons is the variation of
analog parameters. Therefore, desensitizing the analog parameters is important,
which can be done by a feedback topology with a stable reference. In the voltage
domain, a bandgap reference voltage is a good reference, while a crystal oscillator
is the one in the frequency domain.

2.2.1 Basics of Feedback Loop

An open-loop gain (or open-loop transfer function) is highly useful to analyze the
loop dynamics of a feedback system. In Fig. 2.1, the open-loop gain G(s) is
Kd Kv F(s)
G(s) = (2.1)
s
The order of a loop is defined by the number of poles in G(s). The number of
integrators, that is, the number of poles at the origin (s = 0) determines the type
of the loop. Since the VCO inherently contains 1/s, the loop type of a PLL is at
least one. If the loop filter contains another integrator, we call it a type 2 PLL.
14 2 Linear Model and Loop Dynamics

A closed-loop transfer function (also called a system transfer function) H(s) from
an input phase to an output phase is given by
𝜃o G(s) Kd Kv F(s)
H(s) = = = (2.2)
𝜃i 1 + G(s) s + Kd Kv F(s)
For the first-order PLL, the 3-dB corner frequency of H(s) is the same as the
unity-gain frequency of G(s). Similarly, an error transfer function H e (s) from an
input phase to a phase error is expressed as
𝜃e 1 s
He (s) = = = (2.3)
𝜃i 1 + G(s) s + Kd Kv F(s)
Note that H e (s) exhibits a high-pass filter (HPF) transfer function with the same
3-dB corner frequency of H(s). It means that the PLL tracks the low-frequency
components of an input phase, while untracked high-frequency components of
the input phase are shown as phase errors.
For the frequency synthesizer that generates multiple frequencies from a low
reference frequency, a feedback factor needs to be considered in the linear model
of the PLL because a frequency divider is used in the feedback path. For a division
ratio N, a feedback factor of N −1 is to be used. Figure 2.4 shows the linear model
that includes a feedback factor. Since N is constant over frequency, it only plays as
a scaling factor in the open-loop gain. Now, we consider a feedforward gain Gf (s)
given by (2.1). Then, the system transfer function is expressed as
𝜃o Gf (s)
H(s) = = (2.4)
𝜃i 1 + Gf (s)∕N

Figure 2.4 Linear model of the PLL including a frequency divider.

 2.2 Feedback System 15

The 3-dB frequency is reduced by N, while the DC gain is increased by 20logN.

Note that the division ratio N not only multiplies the input frequency but also
amplifies the input phase variation. For the sake of simplicity, we will exclude the
feedback factor to analyze the loop dynamics of the PLL in the rest of this chapter.

2.2.2 Stability
In the negative feedback system, stability is one of the most important things
to be considered. For stability analysis, graphical methods are commonly used,
including Nyquist diagrams, Evans (root locus) plots, Nicholas charts, and Bode
plots. Among them, the Bode plot is well adopted for the stability analysis of a PLL
because it gives a straightforward interpretation of the loop dynamics with the
distinctive locations of poles and zeros. In addition, circuit designers who know
how to design a stable operational amplifier should be familiar with the Bode plot.
For the quantitative analysis of stability, a phase margin or gain margin obtained
from the open-loop gain is used. To understand the physical meaning of the phase
margin and gain margin, let us consider how a negative feedback system becomes
unstable. A negative feedback system becomes a positive feedback system when
there is a 180∘ phase-shift in the negative feedback loop with an open-loop gain
equal to or higher than unity as illustrated in Fig. 2.5. Because of the 1/s term in
the VCO, a phase shift of 90o is already made in the loop. Therefore, the maxi-
mum allowable phase margin is 90∘ with a first-order PLL. If a second-order PLL
is designed, additional phase delay occurs due to the pole of a loop filter. The phase
margin is defined by an excess phase available from the 180∘ phase shift when the
open-loop gain is unity. For example, a phase margin of 30∘ means that there is a
total phase delay of 150∘ in the loop at the unity-gain frequency. The less the phase

Figure 2.5 Phase margin and gain margin.

16 2 Linear Model and Loop Dynamics

Figure 2.6 Type 2 system with a system zero.

margin is, the less stable is the feedback system. Similarly, the gain margin is an
excess gain available from the unity gain when the total phase shift of the loop is
180∘ . The phase margin is more often used in practice than the gain margin since
the gain margin cannot be evaluated if the phase delay in the loop does not reach
180∘ , for example the first-order PLL. Even though the Nyquist plot or root locus
plot shows the detailed information of how a system becomes unstable, the Bode
plot is good enough as a starting point for the loop analysis.
Figure 2.6 illustrates why the type 2 feedback system must have a zero in the loop
dynamics. Each integrator lags the phase by 90∘ in the loop, causing a total phase
delay of 180∘ . Accordingly, the type 2 system cannot be stable since the phase mar-
gin is 0∘ , oscillating at a frequency so-called as natural frequency 𝜔n . By providing
a fast path in the system, that is, bypassing the integrator, a system zero is formed,
and a non-zero phase margin is obtained. Depending on the gain (or strength) of
the fast path, the phase margin of the loop is determined.

2.3 Loop Dynamics of the PLL

Depending on the LPF configuration, a PLL has different types and orders. Despite
various types and orders, having a good knowledge of the second-order type 2
PLL is enough in the design of PLL circuits for most commercial applications, the
grounds of which will be discussed in this chapter.

2.3.1 First-Order Type 1 PLL

The simplest PLL would be a first-order type 1 PLL with a constant LPF gain.
Assuming F(s) = K f , the open-loop gain becomes
K d Kf Kv
G(s) = (2.5)
s
 2.3 Loop Dynamics of the PLL 17

Figure 2.7 Open-loop gain of the first-order PLL with F(s) = 1.

In the first-order PLL, a loop gain K is defined by

K = Kd K f K v (2.6)

Then, the closed-loop transfer function is given by

K
H(s) = (2.7)
s+K
In the first-order feedback system, the unity-gain frequency of G(s) is the same as
the 3-dB corner frequency of H(s). The first-order type 1 PLL is unconditionally
stable with a constant phase margin of 90∘ as illustrated in Fig. 2.7. The unity-gain
frequency 𝜔u in G(s) is given by

𝜔u = K (2.8)

We can see that the unity-gain frequency and the loop gain are related with each
other. That is, to have a wide bandwidth, a high loop gain is required. With a
finite loop gain, transient behaviors such as a lock-in or pull-in range exhibit worse
performance than those of higher-order PLLs. More importantly, the type 1 PLL
has the problem of a static phase error for the change of an input frequency. There-
fore, the use of the first-order PLL by itself is limited in many applications. Those
problems will be discussed in the next chapter.

2.3.2 Second-Order Type 1 PLL

An easy way of implementing a second-order PLL is to add an RC LPF in the loop.
When the 3-dB corner frequency of the RC filter is put outside the bandwidth
of the PLL, the overall behavior of the second-order PLL is similar to that of the
18 2 Linear Model and Loop Dynamics

Figure 2.8 Second-order type 1 PLL with a lead-lag filter.

first-order type 1 PLL except second-order filtering outside the bandwidth. In other
words, the unity-gain frequency and loop gain are still related with each other.
Now let us consider the case of putting the 3-dB corner frequency of the RC filter
within the bandwidth of the PLL. To compensate for the degraded phase margin
due to a pole within the bandwidth, a zero should be added. A lead-lag RC filter
shown in Fig. 2.8 is commonly used to realize a second-order PLL as a passive
filter. The transfer function of the loop filter is
1 + s∕𝜔z 1 + sR2 C
F(s) = = (2.9)
1 + s∕𝜔p 1 + s(R1 + R2 )C

where
1 1
𝜔p = , 𝜔z = (2.10)
(R1 + R2 )C R2 C
Then, the open-loop gain is given by
Kd Kv 1 + s∕𝜔z K K 1 + sR2 C
G(s) = = d v (2.11)
s 1 + s∕𝜔p s 1 + s(R1 + R2 )C

Since there is only one integrator in G(s), the loop is a second-order type 1 loop. In
the second-order PLL, the loop gain K is defined by

K = Kd Kfh Kv (2.12)

where K f,h is the high-frequency loop gain and given by

R2 𝜔p
Kf ,h = = (2.13)
R1 + R2 𝜔z
 2.3 Loop Dynamics of the PLL 19

For the given 𝜔p and 𝜔z , the closed-loop transfer function is obtained from
(2.2), or
Kd Kv 𝜔p (1 + s∕𝜔z ) K𝜔z (1 + s∕𝜔z )
H(s) = = (2.14)
s2 + 𝜔p (1 + Kd Kv ∕𝜔z )s + Kd Kv 𝜔p s2 + (K + 𝜔p )s + K𝜔z
A Bode plot is shown in Fig. 2.8 with 𝜔p < 𝜔u < 𝜔z . As illustrated, 𝜔z helps increase
the phase margin. Compared with the simple case of the second-order PLL with
𝜔u < 𝜔p , the loop dynamics shown in Fig. 2.8 offers a way of controlling 𝜔u inde-
pendently for the given loop gain K. Note that the use of the passive filter cannot
create a pole at DC to realize a type 2 PLL regardless of the order of the loop.

2.3.3 Second-Order Type 2 PLL

To have a type 2 PLL, an active loop filter should be designed to realize an integra-
tor. An example of an active loop filter is shown in Fig. 2.9. The transfer function
of the loop filter is
1 + s∕𝜔z 1 + sR2 C
F(s) = = (2.15)
s∕𝜔p sR1 C
where
1 1
𝜔p = , 𝜔z = (2.16)
R1 C R2 C
Then, the open-loop gain becomes
Kd Kv 1 + sR2 C
G(s) = (2.17)
s2 R1 C
As shown in a Bode plot in Fig. 2.9, the open-loop gain has a slope of −40 dB/dec
from DC. If a system zero is not added, the loop will be unstable with a zero phase

Figure 2.9 Second-order type 2 PLL with an active integrator.

20 2 Linear Model and Loop Dynamics

margin and oscillate at a natural frequency 𝜔n . The loop gain of the second-order
type 2 PLL is given by
R 𝜔p
K = Kd Kf ,h Kv = Kd Kv 2 = Kd Kv (2.18)
R1 𝜔z
where
R2
Kf ,h = (2.19)
R1
The closed-loop transfer function is
Kd Kv 𝜔p (1 + s∕𝜔z ) K𝜔z (1 + s∕𝜔z )
H(s) = = (2.20)
s2 + Kd Kv (𝜔p ∕𝜔z )s + Kd Kv 𝜔p s2 + Ks + K𝜔z
In the second-order type 2 PLL, the loop filter transfer function can be expressed
as the combination of two transfer functions as shown in Fig. 2.10, that is,
1 + sR2 C R 1 𝛽
F(s) = = 2 + =𝛼+ (2.21)
sR1 C R1 sR1 C s
where
R2 1
𝛼= , 𝛽= (2.22)
R1 R1 C
It implies that two separate control paths in parallel can be defined in the loop
filter; a proportional-gain path with a gain of 𝛼 and an integral path with a gain
of 𝛽. Note that the loop gain K is determined by 𝛼 from (2.18) and (2.19). Even
though both the single-path and the two-path configurations bring the same loop
transfer function, the two-path configuration makes it easy to understand the tran-
sient behavior of the second-order type 2 PLL, which will be discussed in the next
chapter.

Figure 2.10 Two-path control of the type 2 PLL.

 2.3 Loop Dynamics of the PLL 21

2.3.4 Natural Frequency and Damping Ratio

In the control theory, the closed-loop transfer function of a second-order feedback
system can be fully characterized by two loop parameters, a natural frequency 𝜔n
and a damping ratio 𝜁 with the form of a standard equation given by
1 + s∕𝜔z
H(s) = 𝜔2n (2.23)
s2 + 2𝜁𝜔n s + 𝜔2n
For a second-order type 2 PLL, 𝜔n and 𝜁 are obtained from (2.20) and (2.23), or
( )
√ 1 𝜔n
𝜔n = K𝜔z , 𝜁 = (2.24)
2 𝜔z
Then, we will have the following relation as
K
𝜔n = or K = 2 𝜁𝜔n (2.25)
2𝜁
In the second-order feedback system, the properties of a pole pair can be described
based on 𝜁. For example, poles are obtained as a complex conjugate pair for 𝜁 < 1
(underdamped), while poles are real and located apart for 𝜁 > 1 (overdamped).
When 𝜁 = 1 (critically damped), poles are real and merged.
Figure 2.11 shows different transient behaviors with 𝜁 = 0.25, 0.5, 0.707, 1, and
2. For 𝜁 < 0.5, the loop exhibits clear overshooting. For 𝜁 > 1, the overshooting is
not observed, but the loop takes a longer time to be settled. Table 2.1 shows the
relationship among the unity-gain frequency 𝜔u , the loop gain K, and the phase
margin. For 𝜁 > 0.707, the phase is margin greater than 65∘ , and 𝜔u is close to K.

Figure 2.11 Transient behavior with 𝜁 = 0.25, 0.5, 0.707, 1, and 2.

22 2 Linear Model and Loop Dynamics

Table 2.1 Relationship among 𝜁, 𝜔u , and K.

Damping 𝜻 𝝎u /K Phase Margin (deg)

0.25 2.13 28.0

0.5 1.27 51.8
0.707 1.10 65.5
1 1.03 76.3
2 1.002 86.4

Figure 2.12 Visual insight on loop dynamics of the type 2 PLL.

For an intuitive understanding, the loop dynamics of a second-order type 2 PLL

could be considered based on the gain partition of the proportional-gain path and
integral path. Figure 2.12 shows the illustrative diagram of the second-order type
2 PLL. If the proportional-gain path is removed, the second-order feedback sys-
tem contains two integrators without any zero compensation, becoming unstable
with 0∘ phase margin. As a result, the feedback system oscillates with a natural
frequency 𝜔n . If the integral path is removed, there is no other integration block
except the VCO, resulting in a type 1 PLL. When the proportional-gain path is
dominant over the integral path, the loop behavior is close to that of the type 1
PLL, showing an overdamped loop behavior. If the proportional-gain path is not
dominant over the integral path, two separate paths compete for the control of the
VCO, exhibiting overshooting and rippling. As the integral path becomes domi-
nant, the overshooting becomes larger, and the rippling period gets close to 1/𝜔n .
Below is the summary.
● When 𝛼 is zero, the loop becomes an oscillator with an oscillation frequency of
𝜔n .
● When 𝛽 is zero, the loop becomes a type 1 PLL.
● When 𝛼 is bigger than 𝛽, the loop becomes an overdamped loop.
● When 𝛽 is much bigger than or similar to 𝛼, the loop becomes an underdamped
loop.
Another random document with
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„Wel Casati, heb je lust om nog eens te duiken, voordat de vloed
komt opzetten?” vroeg Edmonds den duiker.

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Lord Lister, alias Casati, deed wat hem gezegd was.

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Het anker werd gelicht en, vergezeld van een heele flottielje kleinere
en grootere vaartuigen, stoomde de boot naar de veilige haven terug.
[24]

[Inhoud]
VIJFDE HOOFDSTUK.
 DE SCHAT VAN DE „TASMANIA”

In een Hotel van den derden rang te Plymouth, vlak bij de haven, had
Charly Brand een kamer gehuurd, waarvan de vensters uitkeken op
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Thans vervolgde hij:

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„Ja”.
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hoofd. [25]

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Lister drukte zijn vriend met warmte de hand.

„Kom kerel, maak je niet ongerust. Alles komt op zijn pootjes terecht.
En laat ons nu in de eetzaal een flesch Sect gaan drinken.”

Het was een wondermooie, heldere nacht, met een schitterenden

sterrenhemel. De vuren van de havenstad Plymouth rijden zich in een
lange keten langs den oever; aan den horizon schitterde de vuurtoren
van Eddystone en wierp zijn lange stralenbundels ver over de zee.
Uit de herbergen aan de haven klonk woest gezang van matrozen,
vroolijk lachen, en schetterende muziek. Morgen was het Zondag, en
die rustdag moest feestelijk worden ingezet, want op Zondag waren
de kroegen gesloten, en geen lawaai mocht de heilige rust verstoren.

Lord Lister had het wèl overdacht, om dézen nacht voor zijn avontuur
te gebruiken.

Het bootje, waarin hij met zijn vriend Charly had plaats genomen, had
de haven reeds langen tijd verlaten, en dobberde nu op de baren der
eindelooze zee.

Middernacht was reeds voorbij, toen zij langzaam het doel van den
tocht naderden.

De machines stopten, en werkten nu bijna onhoorbaar, en in de verte

doemde reeds de ton op, het kenteeken van de plaats, waar het wrak
was gezonken.

Lord Lister ging thans nog eenige voorbereidende maatregelen

treffen. Hij maakte het bootje stevig vast met ankerkettingen, deed
zijn duikerspak aan, voorzag zich van alle mogelijke werktuigen en
had het geheel zóó ingericht, dat hij zelf het apparaat met
gecomprimeerde lucht op de schouders torste.
Nu ontstak hij de electrische lantaarn langzaam en, als een meteoor,
zonk hij langzaam in de diepte.

Charly keek hem bezorgd na en hield de telephoon aan zijn oor.

Eenigen tijd later meldde lord Lister hem, dat hij den zeebodem had
bereikt, waardoor Charly, die trilde van zenuwachtigheid, alweer wat
kalmer was.

Daar beneden, op den bodem der zee, werd lord Lister door de
heerschende duisternis leelijk belemmerd in de uitoefening van zijn
werk.

Hij moest het smallere achterschip zien binnen te komen, waarin zich
de goudkistjes bevonden.

Zijn electrische lamp verlichtte de omgeving thans voldoende. De

duiker wrong zich nu door een opening in het achterschip en
verbrijzelde daar met heftige bijlslagen een deur, waardoor hij in eene
grootere ruimte kwam.

Hier lagen wederom verscheidene lijken, bij den aanblik waarvan hij
wederom hevig ontstelde.

Maar manmoedig overwon hij alle gevoelens en met zijn werktuigen

arbeidde hij steeds voorwaarts.

In een ruime kajuit gekomen, stiet hij op een groot aantal koffers en
kisten en het kostte hem reusachtig veel moeite om deze allemaal uit
den weg te ruimen. Toen hij dat gedaan had, zag hij weer een deur,
en opnieuw beukten zijn hamerslagen met geweldige kracht op het
vochtige hout. Maar toen ook zag de duiker acht niet al te groote
cassettes, met ijzer beslagen, en voorzien van initialen der Engelsche
Bank. Dat was dus de groote schat. Acht kistjes. En ieder hield voor
ongeveer 3 millioen gulden aan goudstaven in. Dat maakte dus
samen het niet onaardig sommetje van 2 millioen pond sterling of 24
millioen gulden.

Lister telephoneerde nu naar zijn vriend, die in ademlooze spanning

luisterde, dat hij den schat gevonden had, en toen probeerde hij een
der kistjes op te tillen.

Tevergeefs!

Het enorme gewicht der goudstaven en van het ijzeren kistje maakte
het onmogelijk deze van hun plaats te brengen. [26]

Toen Lister met zijn lantaarn de ruimte verlichtte, zag hij plotseling
achter de kistjes de afschuwelijke gedaante van een inktvisch, die
zijn vangarmen naar alle kanten kronkelde, en plotseling een zwarte
vloeistof in het water spoot, waardoor elk uitzicht werd belemmerd.

Enkele oogenblikken keek Lister met verbazing en afschuw naar het

weerzinwekkende beest, maar toen begreep hij ook, dat hij voor het
oogenblik niets meer hier te doen had.

Den schat kon hij immers toch niet meenemen, en hij voelde er bitter
weinig voor, om louter voor zijn genoegen nog langer te blijven in
deze onderzeesche ruimte met zulk een afschuwelijk zeemonster tot
gezelschap.

Spoedig besloten telephoneerde hij nu naar Charly, dat deze het

touw langzaam moest opwinden en toen Lister een tijd later weer aan
boord van het bootje was aangeland, maakte Charly zoo spoedig
mogelijk den zwaren duikershelm los.

„Ben je erg vermoeid, Edward?” vroeg zijn vriend.

„Heelemaal niet. Ik had het best nog langer kunnen uithouden, maar
vond het beter, om eerst eens even naar boven te komen.”
„Je gaat toch niet weer duiken?”

„Maar natuurlijk!”

„Neen, Edward, ik wil het niet!”

Charly maakte zich boos.

„Hou je kalm, vriendje”, spotte Lister en hij klopte den jongen man
eens vriendelijk op den schouder.

Charly moest wel gehoor geven aan de bevelen van zijn vriend.

Hij bracht spoedig een en ander in orde, en een paar minuten later
zakte lord Lister wederom naar den bodem der zee.

Daar aangekomen legde hij een groote hoeveelheid touw, dat hij had
meegenomen, ter zijde.

Toen ging hij opnieuw door de opening kruipen en bereikte weer

langs denzelfden weg de schatkamer.

Hij had een handig apparaat meegenomen, voorzien van een

hefboom. Hij bevestigde nu een der uiteinden van het geweldige
zware kabeltouw aan een der millioenenkistjes, hief de cassette van
den grond en nu viel het hem niet meer moeilijk om het kistje van den
grond te heffen en een oogenblik later zweefde bet langs het wrak.
Nu ontvouwde lord Lister een groot stuk linnen, dat hij had
meegebracht. Hij maakte daar van dit waterdichte linnen,
waaromheen een stevig net zat, een ballon, liet daarin de
gecomprimeerde lucht uit het apparaat ontsnappen en ten slotte kon
de groote, omvangrijke ballon het gewicht van het kistje mee naar
boven nemen door het water.
Nu telephoneerde Lister naar Charly, op welke wijze het hem gelukt
was, het kistje naar boven te krijgen.

Charly riep terug, dat de maan juist was opgekomen en dat hij zich
moest haasten terug te komen, want dat de vloed kwam. Ook had hij
van Eddystone lichten zien naderen.

Eindelijk dan had Lister zijn duikerspak weer uit en stond hij aan
boord van het bootje, naast zijn trouwen vriend Charly, die zich zoo
ongerust had gemaakt, maar nu den koning te rijk was.

Ook Edward lachte.

En geen wonder!

Hij had er alle reden voor.

„Drie millioen voor ons, Charly, wat zeg je ervan?” De rest moeten we
voor de Bank laten, jammer genoeg, maar wij hebben geen tijd meer
om die andere zware kisten nog omhoog te halen.

„En nu, Charly, voortgemaakt!

„Gooi het vischtuig uit, opdat iedereen meent, dat we op de vangst

zijn geweest en niemand achterdocht gaat koesteren.”

Aldus geschiedde.

Langzaam voer het scheepje naar de kust en de groote [27]ballon, die

den goudschat naar boven had gebracht, zweefde aan het achterdek.

Zuidelijk van Plymouth werd het schip gemeerd.

Hier was het eenzaam.

Voordat het scheepje aan de kust kwam, beproefden de beide
vrienden de zware cassette, die onder den ballon meevoer, aan
boord te hijschen.

Het bleek onmogelijk!

Het kistje was zoo zwaar, dat de boot op levensgevaarlijke wijze ging
overhellen naar den kant, waar men het binnen boord wou halen.

Lord Lister zocht nu tusschen de rotsen naar een geschikte plaats om

te landen en vond deze ook al spoedig.

Door verscheiden klippen werd een beschutten driehoek gevormd,

die een waterbassin insloot en in deze natuurlijke haven bracht Lister
het scheepje.

„Als nu de vloed komt”, sprak Lister, „drijft de ballon vanzelf met zijn
kostbaren last deze haven binnen. Dan laten wij de lucht eruit en
alles zinkt op den bodem, totdat wij bij ebbe den schat kunnen
meenemen.

„Morgen is het Zondag. Dan hebben wij tijd in overvloed.” [28]

[Inhoud]
ZESDE HOOFDSTUK.
 VIJF MILLIOEN GULDEN.

Des Maandagsmiddags was heel Plymouth in rep en roer.

Als een loopend vuurtje had het zich door de stad verbreid, dat
duikers den schat van de „Tasmania” hadden gevonden. Deze zou bij
eb naar boven worden gehaald.

De wonderlijkste verhalen deden de rondte van millioenen, die in de

hut van een Australiër waren gevonden.

Een heele vloot van booten en bootjes verliet Plymouth om het

zeldzame schouwspel te gaan bijwonen, dat een schat uit de diepte
werd geheschen.

Wat was er waar van deze verhalen?

Het volgende:

Casati zou in den middag probeeren om den schat naar boven te

brengen, dien hij des morgens ontdekt had; onder Baxter’s leiding
zou de politie toezicht komen houden op het kostbare werk.

Mr. Fergusson was aan boord van het duikerschip, waar zich ook
twee directeuren van de Engelsche Bank bevonden, voorts Baxter en
rechercheur Marholm.

De heeren spraken natuurlijk druk over de gezonken millioenen en

den duikersarbeid.

Edmonds zou met de drie duikers tegelijk naar beneden gaan, opdat
Casati hun duidelijk de schatkamer zou kunnen toonen.
Met z’n vieren zouden zij gemakkelijker den schat kunnen naar boven
brengen.

De duikers waren in de beste stemming door het vooruitzicht op de

premie.

De spanning werd algemeen, toen het viertal ging duiken.

Eindelijk, na twintig minuten, kwam het viertal weer boven en

Edmonds deelde mede, dat het ’t beste zou zijn, als het schip vlak
boven het wrak ging liggen.

Zoo gezegd zoo gedaan.

Kapitein Brown manoeuvreerde aldus met het vaartuig en liet den

kraan plaatsen, waarmee aan lange kettingen de ijzeren kistjes
konden worden opgetakeld.

’t Werd doodstil in het rond.

De nieuwsgierigen in hun booten hadden een grooten kring gevormd

en keken toen in ademlooze spanning. [29]

Millioenen, vele millioenen zouden straks worden opgeheschen.

Ieder der omstanders wenschte op dit oogenblik duiker te zijn om

vele duizenden van de premie te kunnen opstrijken.

En allen keken—en zwegen.

De arbeid had een geregeld verloop.

Twee uur later kon het signaal gegeven worden: de eerste kist
ophalen!—

Dat gebeurde!
Knersend sloegen de ketenen, de stoommachine proestte en
pruttelde.

Toen—een plassen—een ijzeren kistje werd opgeheven—de kraan

draaide—en nu lagen de eerste 250,000 pond—drie millioen gulden
—op dek.

De Engelsche Bank had een dubbel stel sleutels van de

goudcassettes;—een der directeuren had ze meegenomen, het kistje
werd geopend en daar schitterde het gele, glanzende metaal in
duizendvoudigen gloed.

In zijn groote vreugde ging de eerste Bankdirecteur naar Casati toe:

„U, signor”, sprak hij, „danken wij deze vondst. Wilt ge hier maar de
premie van duizend pond voor den ontdekker in ontvangst nemen?
De Bank zal u steeds groote dankbaarheid blijven toekennen!”

Met deze woorden overhandigde hij Casati een enveloppe.

Deze was opgestaan.

Hij sprak eenige woorden van dank en stak de enveloppe in den zak.

Toen strekte hij zich weer uit op den ruststoel, alsof er niets
bijzonders gebeurd was.—

Tot den avond werd doorgewerkt.

De zevende kist lag reeds op dek, toen door de duikers gemeld werd,
dat dit de laatste was.

De Bankdirecteuren keken elkaar verstomd aan.

Zij hadden hier geen cijfer genoemd, maar het stond vast, dat in
Sydney acht kistjes aan boord waren geheschen.
Edmonds werd nu ontboden.

„Hebt gij het aantal kistjes ook geteld?” vroeg hij een der
Bankdirecteuren.

„Zeker. Toen ik het laatst beneden lag, waren er nog vier kistjes. Drie
waren toen al opgeheschen. Er moeten dus zeven kistjes geweest
zijn.”

„Juist—zeven kistjes zijn aan boord. Maar acht werden indertijd

verscheept. Dat is wel heel merkwaardig! Waar kan dat achtste kistje
zijn?”—

Edmonds keek den spreker verbluft aan.

„Hoe zou ik dat weten, sir! Mijn duikers en ik kunnen u verklaren, dat
er maar zeven kistjes in de schatkamer waren.”

„Dan is het achtste kistje waarschijnlijk in een ander deel van het
schip, of— —”

Hij voltooide niet.

Zijn collega keek hem vragend aan, maar de ander zei slechts:

„Merkwaardig—heel merkwaardig!”

De andere Bankdirecteur zei thans:

„Waarde heer Edmonds, zeg niets van alles wat ik u meedeelde,

maar laat het wrak nog eens nauwkeurig onderzoeken. Het achtste
kistje moet er toch ook zijn, want geen uwer duikers kan zoo’n
centenaarslast verdonkeremanen en 250,000 pond is geen bagatel.”

Edmonds antwoordde:
„Ik ga dadelijk met Casati, mijn besten duiker, weer naar beneden.
Dadelijk!” [30]

Edmonds ging naar Lord Lister.

Zij bereidden zich terstond voor op een nieuwen tocht.

Een oogenblik later doken zij opnieuw.

Na een uur was de tocht afgeloopen. Er was geen achtste kistje

gevonden en Edmonds geloofde, dat dit kistje bij het vergaan van het
schip was verloren gegaan.

Bovendien was achter in de schatkamer een groot gat, waardoor de

kist heel makkelijk kon zijn heengegleden.

Deze verklaring was heel aannemelijk.

Baxter alleen schudde ongeloovig het hoofd.

Toen Edmonds hem voorstelde om zich dan eens persoonlijk te gaan

overtuigen, wees hij dit aanbod met groote beslistheid van de hand.

De directeuren moesten zuchtend constateeren, dat 250,000 pond

sterling voor de Bank waren verloren gegaan.

Hun taak was hier echter thans afgeloopen en het schip van kapitein
Brown kon naar Plymouth terugkeeren.

Onderweg kon rechercheur Marholm niet nalaten om tegen Baxter te

beweren:

„Als de geschiedenis zich niet op den bodem der zee had afgespeeld,
zou ik er op zweren, dat Raffles die 250,000 pond had gestolen.”
„Herinner mij niet aan dien man, die de vloek is van mijn leven”, zei
Baxter op giftigen toon.

„Maar Raffles heeft ons toch een dienst bewezen, door ons
opmerkzaam te maken op het helershol van dien Fox.”

„Dat is waar!”

„Hij is zoo kwaad nog niet!”

„Wie niet?”

„Wel, Raffles!”

„Maar Marholm, je bent gek, stapelgek. Zou je dien Raffles niet een
premie willen toekennen?”

„Hij zal zich wel een en ander zelf hebben genomen, chef!”

„Zoo, denk je?”

„Natuurlijk!”

„En je vindt hem zoo kwaad nog niet!”

„Hij zal nooit menschen benadeelen, die eerlijk en braaf zijn. Alleen
schurken besteelt hij.”

„Hou op, Marholm, hou op over Raffles!”

——————————————

Toen de stoomboot in Plymouth was binnengeloopen, bracht een

postbode een spoedbrief voor Baxter.

Deze opende haastig het epistel, maar nauw had hij het gelezen, of
hij stiet een kreet van woede uit.
„Wat is er?” vroeg een der directeuren.

Bleek van opwinding overhandigde Baxter hem het schrijven.

En de directeur las met groote oogen luid-op:

„Ik deel den politie-inspecteur Baxter door dezen mede, dat het achtste
vermiste kistje met goudstaven van de Engelsche Bank zich bevindt in den
bekenden driehoek bij de molenrotsen. Als het ebbe is, kan het kistje heel
gemakkelijk van daar worden weggehaald. De plaats is dan droog.

Hoogachtend,
JOHN C. RAFFLES.”

[31]

Marholm deed alle moeite, om een opkomenden lach te verbergen.

Maar hij bedwong zich en zei met onschuldig gelaat tot Baxter:

„Dat is een gladde vogel, die Raffles, nietwaar, chef?”

Baxter antwoordde niet en draaide zich om.

De zonderlinge brief ging van hand tot hand en Edmonds zei:

„Ik denk, dat iemand hier een heel flauwe grap heeft willen uithalen,
maar in elk geval moet de aangeduide plaats nader onderzocht
worden!”

Nu las Brown den brief.

Hij lachte en maakte de opmerking, dat op de aangeduide plek

inderdaad een driehoek door rotsen was gevormd. Met een boot kan
men heel makkelijk deze plek bereiken.
Besloten werd om denzelfden nacht bij ebbe naar de plaats te varen.
Kapitein Brown zou voor dien tocht een boot beschikbaar houden.

Terwijl de heeren het schip verlieten, had lord Lister zich omgekleed
en nu deelde hij kapitein Edmonds mee, dat hij zich wat in Plymouth
wilde gaan vermaken na al dien inspannenden arbeid.

De duikerchef gaf daartoe gaarne verlof en Lister verliet het schip om

er nooit op terug te keeren.

Toen de boot zich gereed maakte om naar den rots-driehoek te

varen, zaten Lister en Charly Brand al in een coupé eerste klasse, op
weg naar Ramsgate, om vandaar Oostende te bereiken.

De heeren in de boot zaten allen met mistroostige gezichten te kijken.

Zij hadden een gevoel, alsof zij een vreemde gebeurtenis tegemoet
voeren.

Kapitein Brown had het bevel op de boot.

Hij wist uitstekend den weg in deze plekken, vol verborgen klippen.
De eb had thans alle rotsen blootgelegd en bij het schijnsel van
lantaarns en fakkels manoeuvreerde de boot handig overal tusschen
door.

Daar werd reeds de driehoek zichtbaar.

Groote onrust greep de inzittenden aan.

Toen het schip stil lag, was Baxter de eerste, die uitsprong, spoedig
gevolgd door de anderen.

Waarlijk!

Daar lag, op den rotsbodem, het vermiste kistje en de bankdirecteur

haastte zich, het zware deksel op te lichten.
Een kreet van verrassing en schrik steeg op uit alle kelen.

Het kistje was leeg!

Maar aan het deksel was aan de binnenzijde een stuk perkament
bevestigd, waarop in groote letters stond geschreven:

„Ik geef de Engelsche Bank het achtste kistje gaarne terug. Met haar
inhoud hoop ik nog heel wat ellende in de wereld te lenigen. Mijn aandeel
in de winst sta ik graag af aan mijn drie collega’s. Ik heb dat geld niet
noodig. Met een vriendelijken groet aan den heer Baxter.

JOHN C. RAFFLES,
de gewezen duiker Casati.”

De uitwerking van dezen brief was inderdaad hevig.

Baxter was razend. Want het was heel wat voor iemand, die zoozeer
met zichzelven is ingenomen als deze inspecteur der recherche, om
voor den zooveelsten keer te moeten erkennen, dat hij bij den neus
genomen is door een inbreker van beroep. En Baxter bekende [32]het
niet graag, als hij een nederlaag had geleden. Hij smoorde een
zwaren vloek tusschen de lippen, bedwong zich met de meest
mogelijke moeite en bracht er eindelijk uit, daar aller oogen op hem
gericht waren:

„Die Raffles—die Raffles! Ik zal niet veel meer zeggen, maar tòch
moet mij van het harte, dat ik hoop, dat dit nu de laatste maal zal zijn,
de allerlaatste maal!”

Toen zweeg hij, inwendig diep gegriefd.

En detective Marholm?

Die kon zijn lachen niet bedwingen, maar proestte het uit toen men
wat bekomen was van den algemeenen schrik.