ROUTER 1X3 PROJECT REPORT

Rohan S WBPD04
Router FIFO
//fifo router project

module
router_fifo(clk,rst,write_en,soft_reset,read_enb,data_in,lfd_state,empty,data_out,full);

parameter depth = 16;

parameter width=9 ; //9th bit is for header

input clk,rst,write_en,soft_reset,read_enb,lfd_state; //soft_reset is time

,,,,,Ifd_state detects the header byte
input [7:0] data_in;
output reg [7:0] data_out;
output empty,full;

reg [4:0] wr_ptr,rd_ptr;

reg [width-1:0] mem [depth-1:0];
reg [6:0] fifocounter;
reg temp;
integer i;
reg [4:0] incrementer;
//--------------------------------------------------------------------------------------
----------------------------------------------
//lfd_state as we are getting data in from register we have to delay by 1 clk pulse

always@(posedge clk)
begin
if(!rst)
temp<=1'b0;
else
temp<=lfd_state;
end
//--------------------------------------------------------------------------------------
----------------------------------------------
//empty or full
assign full = (wr_ptr=={~rd_ptr[4],rd_ptr[3:0]})?1'b1:1'b0;
assign empty = (wr_ptr==rd_ptr)?1'b1:1'b0;
//--------------------------------------------------------------------------------------
----------------------------------------------
//pointer logic

always@(posedge clk)
begin
if(!rst || soft_reset)
begin
rd_ptr<=5'b00000;
wr_ptr<=5'b00000;
end
else
begin
if(!full && write_en)
wr_ptr <= wr_ptr+1;
else
wr_ptr <= wr_ptr;

if(!empty && read_enb)

rd_ptr <= rd_ptr+1;
else
rd_ptr <= rd_ptr;
end
end
//--------------------------------------------------------------------------------------
----------------------------------------------
//counter logic
always@(posedge clk)
begin
if(rd_ptr & ~empty)
begin
if(mem[rd_ptr[3:0]][8])
fifocounter <= mem[rd_ptr[3:0]][7:2]+1'b1;
else if(fifocounter !=0)
fifocounter<= fifocounter-1'b1;
end

end
//--------------------------------------------------------------------------------------
----------------------------------------------
//1. read opertation

always@(posedge clk)
begin
if(!rst)
data_out<=8'd0;
else if(soft_reset)
data_out<=8'dz;
else
begin
if(fifocounter==0)
data_out<=8'dz;
if(read_enb && !empty)
data_out <= mem[rd_ptr[3:0]];
end

end
//--------------------------------------------------------------------------------------
----------------------------------------------
//2. write operation

always@(posedge clk)
begin
if(!rst)
begin
for(i=0;i<16;i=i+1)
begin
mem[i]<=0;
end
end

else if(soft_reset)
begin
for(i=0;i<16;i=i+1)
begin
mem[i]<=0;
end
end

else if(write_en && !full)

{mem[wr_ptr[3:0]][8],mem[wr_ptr[4:0]][7:0]}<={temp,data_in};

end

endmodule
ROUTER FIFO TEST BENCH
module router_fifo_tb();

parameter depth = 16;

parameter width=9 ;

reg clk,rst,write_en,soft_reset,read_enb,lfd_state;
reg [7:0] data_in;
wire [7:0] data_out;
wire empty,full;

integer i;

router_fifo
dut(clk,rst,write_en,soft_reset,read_enb,data_in,lfd_state,empty,data_out,full);

initial
begin
clk=1'b1;
forever #5 clk=~clk;
end

//test for write operation

task write(input we);

begin
@(negedge clk)
data_in= $random;
write_en=we;
end
endtask

//test for read operation

task read(input re);

begin
@(negedge clk)
read_enb=re;
end
endtask

//initilize
task initilize();
begin
@(negedge clk)
rst=0;#5;
soft_reset=1;#5;
rst=1;soft_reset=0;
lfd_state=1;
read_enb=0;
write_en=0;
end
endtask

//test
initial
begin
initilize;
write(0);
read(0);#20;
repeat(17)
begin
write(1);
#10;
end
write(0);#5;
read(1);#100;
end
endmodule
ROUTER SYNCHRONIZER:
//router synchronizer
module
router_sync(clk,rst,detect_add,write_en_reg,data_in,full_0,full_1,full_2,empty_0,empty_1
,empty_2,read_enb_0,read_enb_1,read_enb_2,write_en,vld_out_0,soft_reset_0,
vld_out_1,soft_reset_1, vld_out_2,soft_reset_2, fifo_full);

input clk,rst,detect_add,write_en_reg;
input[1:0]data_in;
input full_0,full_1,full_2,empty_0,empty_1,empty_2,read_enb_0,read_enb_1,read_enb_2;
output reg [2:0] write_en;
output vld_out_0, vld_out_1, vld_out_2;
output reg soft_reset_0,soft_reset_1,soft_reset_2;
output reg fifo_full;

reg [1:0]temp;
integer timer0,timer1,timer2;

//5. timer for 30 clk cycles

//timer 0
always@(posedge clk)
begin
if(!rst)
begin
timer0 <=5'b0;
soft_reset_0 <=0;
end
else if(vld_out_0 )
begin
if(!read_enb_0)
begin
if(timer0==5'd29)
begin
soft_reset_0<=1'b1;
timer0<=1'b0;
end
else
begin
soft_reset_0<=1'b0;
timer0<=timer0+1'b1;
end
end
end
end

always@(posedge clk)
begin
if(!rst)
begin
timer1 <=5'b0;
soft_reset_1 <=0;
end
else if(vld_out_1 )
begin
if(!read_enb_1)
begin
if(timer1==5'd29)
begin
soft_reset_1<=1'b1;
timer1<=1'b0;
end
else
begin
soft_reset_1<=1'b0;
timer1<=timer1+1'b1;
end
end
end
end

always@(posedge clk)
begin
if(!rst)
begin
timer2 <=5'b0;
soft_reset_2 <=0;
end
else if(vld_out_2 )
begin
if(!read_enb_2)
begin
if(timer2==5'd29)
begin
soft_reset_2<=1'b1;
timer2<=0;
end
else
begin
soft_reset_2<=0;
timer2<=timer2+1'b1;
end
end
 end
end

//1. detect_add and data_in

always@(posedge clk)
begin
if(!rst)
temp<=0;
else if(detect_add)
temp<=data_in;
end

//2. fifo full

always@(*)
begin
case(temp)
2'b00 :fifo_full=full_0;
2'b01 :fifo_full=full_1;
2'b10 :fifo_full=full_2;
default fifo_full=0;
endcase
end

//3. valid out

assign vld_out_0 = ~empty_0;

assign vld_out_1 = ~empty_1;
assign vld_out_2 = ~empty_2;

//4. write enable

always@(*)
begin
if(write_en_reg)
begin
case(temp) //address register
2'b00 :write_en =3'b001;
2'b01: write_en =3'b010;
2'b10: write_en =3'b100;
default:write_en=3'b000;
endcase
end
else
write_en=3'b000;
end

endmodule

ROUTER SYNCHRONIZER TEST BENCH:

module router_sync_tb();

reg clk,rst,detect_add,write_en_reg;
reg [1:0]data_in;
reg full_0,full_1,full_2,empty_0,empty_1,empty_2,read_enb_0,read_enb_1,read_enb_2;
wire[2:0] write_en;
wire vld_out_0,soft_reset_0, vld_out_1,soft_reset_1, vld_out_2,soft_reset_2;
wire fifo_full;
realtime t1,t2;

router_sync
dut(clk,rst,detect_add,write_en_reg,data_in,full_0,full_1,full_2,empty_0,empty_1,empty_2
,read_enb_0,read_enb_1,read_enb_2,write_en,vld_out_0,soft_reset_0,
vld_out_1,soft_reset_1, vld_out_2,soft_reset_2, fifo_full);

initial
begin
clk=1'b1;
forever #5
clk=~clk;
end

task initialize();
begin
@(negedge clk)
{empty_0,empty_1,empty_2}=3'bzzz;
rst=1'b1;
empty_0=1'b0;
detect_add=1'b0;
data_in=2'bzz;
write_en_reg=1'b1;
read_enb_0=1'b1;
end
endtask

task reset;
begin
rst=1'b0;
#10;
rst=1'b1;
end
endtask

task run();
begin
@(negedge clk)

detect_add=1'b1;
data_in=2'b10;
read_enb_0=1'b0;
read_enb_1=1'b1;
read_enb_2=1'b0;
write_en_reg =1'b1;
full_0=1'b0;
full_1=1'b1;
full_2=1'b1;
empty_0=1'b1;
empty_1=1'b0;
empty_2=1'b0;

@(posedge clk) t1= $realtime;

end
endtask

task run1();
begin
@(negedge clk)
detect_add=1'b1;
data_in=2'b00;
read_enb_1=1'b1;
read_enb_2=1'b0;
write_en_reg =1'b1;
full_0=1'b0;
full_1=1'b1;
full_2=1'b1;
empty_0=1'b0;
empty_1=1'b0;
empty_2=1'b0;
read_enb_0=1'b0;#70;

@(posedge clk) t1= $realtime;

end
endtask
initial
begin
initialize;
reset;
run;
run1;
end

initial #1000 $finish();

endmodule

ROUTER REGISTER RTL:

module router_reg
(rst,clk,pkt_valid,data_in,fifo_full,rst_int_reg,detect_add,ld_state,laf_state,full_stat
e,lfd_state,parity_done,low_pkt_valid,error,dout);
input rst,clk;
input
pkt_valid,fifo_full,rst_int_reg,detect_add,ld_state,laf_state,full_state,lfd_state;
input [7:0] data_in;
output reg [7:0] dout;
output reg parity_done,error,low_pkt_valid;

reg [7:0] header_byte;

reg full_state_reg, internal_parity, packet_parity;
//laf_state is load after full
//parity done
always@(posedge clk)
begin
if(!rst)
parity_done<=1'b0;
else if((ld_state&& ~fifo_full && ~pkt_valid)||(laf_state && low_pkt_valid &&
~parity_done))
begin
parity_done<=1'b1;
end
else if(detect_add==1'b1) //reciving header but not parity
parity_done<=1'b0;
else
parity_done<=parity_done; //avoid unessary latch creation
end

//low packet valid logic

always@(posedge clk)
begin
if(!rst)
low_pkt_valid<=1'b0;
else if(ld_state && ~pkt_valid)
low_pkt_valid<=1'b1;
else if(rst_int_reg)
low_pkt_valid<=1'b0;
end

//internal parity register logic

always@(posedge clk)
begin
if(!rst)
internal_parity<=8'b0;
else if (detect_add)
internal_parity<=8'b0;
else if(lfd_state)
internal_parity <=internal_parity ^ header_byte;
else if(ld_state && low_pkt_valid && !full_state)
internal_parity<= internal_parity ^ data_in;
else
internal_parity<=internal_parity;
end

//packet_parity

always@(posedge clk)
begin
if(!rst)
packet_parity<=1'b0;
else if(detect_add)
packet_parity<=1'b0;
else if((ld_state&& ~fifo_full && ~pkt_valid)||(laf_state && low_pkt_valid &&
~parity_done))
packet_parity<=data_in;
else
packet_parity<=packet_parity;
end

//error output logic

always@(posedge clk)
begin
if(!rst)
error<=1'b0;
else if(!parity_done)
error<=1'b0;
else if(internal_parity != packet_parity)
error<=1'b1;
else if(internal_parity == packet_parity)
 error<=1'b0;
end

//finding header bite

always@(posedge clk)
begin
if(!rst)
header_byte <=8'b0;
else if(detect_add && pkt_valid && data_in[1:0]!==2'b11)
header_byte <=data_in;
else
header_byte <= header_byte;
end

//data out

always@(posedge clk)
begin
if(!rst)
dout<=header_byte;
else if(ld_state && !fifo_full)
dout<= data_in;
else if(ld_state && fifo_full)
full_state_reg <= data_in;
else if(laf_state)
dout<=fifo_full;
end

endmodule

ROUTER REGISTER TEST BENCH:

module router_reg_tb();
reg rst,clk;
reg pkt_valid,fifo_full,rst_int_reg,detect_add,ld_state,laf_state,full_state,lfd_state;
reg [7:0] data_in;
wire [7:0] dout;
wire parity_done,error,low_pkt_valid;
integer i;

router_reg
utt(rst,clk,pkt_valid,data_in,fifo_full,rst_int_reg,detect_add,ld_state,laf_state,full_s
tate,lfd_state,parity_done,low_pkt_valid,error,dout);

//clk

initial
begin
clk=1'b0;
forever #5 clk=~clk;
end

//reset

task reset;
begin
rst=1'b0;
rst_int_reg=1'b1;
#10;
rst=1'b1;
rst_int_reg=1'b0;
end
endtask

task intilise;
begin
ld_state=1'b1;
fifo_full=1'b1;
pkt_valid=1'b0;
#5 fifo_full=1'b0;
data_in=$random;
end
endtask

task din;
begin
detect_add=1'b1;
pkt_valid=1'b1;
data_in=$random;
lfd_state=1'b1;
fifo_full=1'b0;
end
endtask

task packet1();

reg [7:0]header, payload_data, parity;

reg [5:0]payloadlen;
begin
@(negedge clk);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in = header;
parity=parity^data_in;

@(negedge clk);
detect_add=1'b0;
lfd_state=1'b1;

for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clk);
lfd_state=0;
ld_state=1;

payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end

@(negedge clk);
pkt_valid =0;
data_in=parity;

@(negedge clk);
ld_state=0;
end

endtask

task packet2();

reg [7:0]header, payload_data, parity;

reg [5:0]payloadlen;
begin
@(negedge clk);
payloadlen=8;
parity=0;
detect_add=1'b1;
pkt_valid=1'b1;
header={payloadlen,2'b10};
data_in=header;
parity=parity^data_in;
 @(negedge clk);
detect_add=1'b0;
lfd_state=1'b1;

for(i=0;i<payloadlen;i=i+1)
begin
@(negedge clk);
lfd_state=0;
ld_state=1;

payload_data={$random}%256;
data_in=payload_data;
parity=parity^data_in;
end

@(negedge clk);
pkt_valid=0;
data_in=!parity;

@(negedge clk);
ld_state=0;
end
endtask

initial
begin
reset;
intilise;
din;
fifo_full=1'b0;
laf_state=1'b0;
full_state=1'b0;
reset;
packet1;
packet2;
$finish;
end

endmodule
ROUTER FSM RTL:
module router_fsm(input clk,rst,pkt_valid,parity_done,input [1:0] data_in,input
fifo_empty_0,fifo_empty_1,fifo_empty_2,soft_reset_0,soft_reset_1,soft_reset_2,fifo_full,
low_pkt_valid,
output
busy,detect_add,ld_state,laf_state,full_state,write_enb_reg,rst_int_reg,lfd_state);

reg [3:0] present_state,next_state;

parameter decode_address = 4'b0001;

parameter wait_till_empty = 4'b0010;
parameter load_first_data = 4'b0011;
parameter load_data = 4'b0100;
parameter fifo_full_state = 4'b0101;
parameter load_after_full = 4'b0110;
parameter load_parity = 4'b0111;
parameter check_parity_error= 4'b1000;

/*declaring additonal reg to store header value for

data_in .... at the moment we are keeping in temp coz we dont need to check for the
address for now
later use this condition for fsm part*/

//fsm is written by project specification

reg [1:0] fsm_data_in;

//temp logic

always@(posedge clk)
begin
if(~rst)
fsm_data_in<=2'b00;
else if(detect_add)
fsm_data_in<=data_in;
end

/* 1. first block present state logic*/

always@(posedge clk)
begin
if(~rst)
present_state<=decode_address;
else if(((soft_reset_0) && (fsm_data_in==2'b00))||((soft_reset_1) &&
(fsm_data_in==2'b01))||((soft_reset_2) && (fsm_data_in==2'b10)))
 present_state <=decode_address;
else
present_state<=next_state;
end

always@(*)
begin
next_state=decode_address;
case(present_state)
//.1
decode_address :
begin
next_state=decode_address;
if(((pkt_valid) && (data_in==2'b00) && (fifo_empty_0))||((pkt_valid)
&& (data_in==2'b01) && (fifo_empty_1))||((pkt_valid) && (data_in==2'b10) &&
(fifo_empty_1)))
next_state= load_first_data;
else if(((pkt_valid) && (data_in==2'b00) &&
(!fifo_empty_0))||((pkt_valid) && (data_in==2'b01) && (!fifo_empty_1))||((pkt_valid) &&
(data_in==2'b10) && (!fifo_empty_1)))
next_state= wait_till_empty;
else
next_state=decode_address;
end
//.3
load_first_data : next_state = load_data;

//.2
wait_till_empty :begin
next_state=wait_till_empty;
if((fifo_empty_0 &&
(fsm_data_in[1:0]==2'b00))||(fifo_empty_0 && (fsm_data_in[1:0]==2'b01))||(fifo_empty_0
&& (fsm_data_in[1:0]==2'b10)))
next_state=load_first_data;
end
//.4
load_data :begin
next_state=load_data;
if(fifo_full)

next_state= fifo_full_state;
else
begin
if(!fifo_full && !pkt_valid)
next_state=load_parity;
else
next_state=load_data;
end
end
//.5
fifo_full_state :begin
next_state=fifo_full_state;
if(!fifo_full)
next_state=load_after_full;
else if(fifo_full)
next_state=fifo_full_state;
end
//.6
load_after_full : begin
next_state=load_after_full;
if(!parity_done && low_pkt_valid)
next_state=load_parity;
else if(!parity_done && !low_pkt_valid)
next_state=load_data;

else begin
if(parity_done)
next_state=decode_address;
else
next_state = load_after_full;
 end
end
//.7
load_parity : begin

next_state=check_parity_error; end
//.8
check_parity_error:begin
next_state=check_parity_error;
if(fifo_full)
next_state=fifo_full_state;
else if(!fifo_full)
next_state=decode_address;
end

default: next_state=decode_address;
endcase
end

//output logic

assign lfd_state= (present_state==load_first_data)?1'b1:1'b0;

assign ld_state= (present_state==load_data)?1'b1:1'b0;
assign full_state= (present_state==fifo_full_state)?1'b1:1'b0;
assign laf_state =((present_state==load_after_full))?1'b1:1'b0;
assign rst_int_reg =((present_state==check_parity_error))?1'b1:1'b0;
assign detect_add= ((present_state==decode_address))?1'b1:1'b0;

assign write_enb_reg=
((present_state==load_after_full)||(present_state==load_parity)||(present_state==load_da
ta))?1'b1:1'b0;
assign busy =
((present_state==load_first_data)||(present_state==fifo_full_state)||(present_state==loa
d_after_full)||(present_state==load_parity)||(present_state==wait_till_empty)||(present_
state==check_parity_error))?1'b1:1'b0;

endmodule

//load == write en ==1

ROUTER FSM TEST BENCH:

module router_fsm_tb();

reg clk,rst,pkt_valid,parity_done;
reg [2:0] data_in;
reg
soft_reset_0,soft_reset_1,soft_reset_2,fifo_full,low_pkt_valid,fifo_empty_0,fifo_empty_1
,fifo_empty_2;
wire busy,detect_add,ld_state,laf_state,full_state,write_enb_reg,rst_int_reg,lfd_state;

router_fsm
dut(clk,rst,pkt_valid,parity_done,data_in,fifo_empty_0,fifo_empty_1,fifo_empty_2,soft_re
set_0,soft_reset_1,soft_reset_2,fifo_full,low_pkt_valid,busy,detect_add,ld_state,laf_sta
te,full_state,write_enb_reg,rst_int_reg,lfd_state);

initial
begin
clk=1'b1;
forever #5 clk=~clk;
end

//reset

task reset;
begin
@(negedge clk)
rst=1'b0;
@(negedge clk)
 rst=1'b1;
end
endtask

task initilize;
begin
@(negedge clk)
pkt_valid=1'b1;
data_in=2'b00;
fifo_full=1'b0;
fifo_empty_0=1'b1;
fifo_empty_1=1'b0;
fifo_empty_2=1'b0;
soft_reset_0=1'b0;
soft_reset_1=1'b1;
soft_reset_2=1'b0;
parity_done=1'b0;
low_pkt_valid=1'b0;
end
endtask

task DA_LFD_LD_LP_CPE_DA;
begin
rst=1'b0;#20;
rst=1'b1;#20;
@(negedge clk)
pkt_valid=1'b1;
data_in=2'b00;
fifo_empty_0=1;
#50; @(negedge clk)
fifo_full=1'b0;
pkt_valid=1'b0;
#20;@(negedge clk)
fifo_full=1'b0;
end
endtask

task DA_LFD_LD_FFS_LAF_LP_CPE_DA;
begin
rst=1'b0;#20;
rst=1'b1;#20;
@(negedge clk)
parity_done=1'b1;
data_in=2'b01;
fifo_empty_1=1'b1;
#50;@(negedge clk)
fifo_full=1'b1;
#50;@(negedge clk)
fifo_full=1'b0;
#30;@(negedge clk)
parity_done=1'b0;
low_pkt_valid=1'b1;
#30;@(negedge clk)
fifo_full=1'b0;
end
endtask

task DA_LFD_LD_FFS_LAF_LD_LP_CPE_DA;
begin
rst=1'b0;#20;
rst=1'b1;#20;@(negedge clk)
parity_done=1'b1;
data_in=2'b01;
fifo_empty_1=1'b1;
#50;@(negedge clk)
fifo_full=1'b1;
#50;@(negedge clk)
fifo_full=1'b0;
#30;@(negedge clk)
parity_done=1'b0;
low_pkt_valid=1'b0;
#30;@(negedge clk)
fifo_full=1'b0;
pkt_valid=1'b0;
#30;@(negedge clk)
fifo_full=1'b0;
end
endtask

task DA_LFD_LD_LP_CPE_FFS_LAF_DA;
begin
rst=1'b0;#20;
rst=1'b1;#20;@(negedge clk)
parity_done=1'b1;
data_in=2'b01;
fifo_empty_1=1'b1;
#50;@(negedge clk)
fifo_full=1'b0;
pkt_valid=1'b0;
#50;@(negedge clk)
fifo_full=1'b1;
#50;@(negedge clk)
fifo_full=1'b0;
#50;@(negedge clk)
parity_done=1'b1;
end
endtask

initial
begin
reset;#20;
initilize;
DA_LFD_LD_LP_CPE_DA;#20;
initilize;
reset;
DA_LFD_LD_FFS_LAF_LP_CPE_DA;#20;
initilize;
reset;
DA_LFD_LD_FFS_LAF_LD_LP_CPE_DA;#20;
initilize;
reset;
DA_LFD_LD_LP_CPE_FFS_LAF_DA;
$finish;
end

endmodule
ROUTER TOP RTL:
module router_top(input clk,rst,read_en_0,read_en_1,read_en_2,pkt_valid,input [7:0]
data_in,
output [7:0] data_out_0,data_out_1,data_out_2,output
vld_out_0,vld_out_1,vld_out_2,error,busy);

wire [2:0]write_en;
wire [7:0]dout;

router_fsm fsm(.clk(clk),.rst(rst),.pkt_valid(pkt_valid),.parity_done(parity_done),
.data_in(data_in[1:0]),.fifo_empty_0(empty_0),.fifo_empty_1(empty_1),.fifo_empty_2(empty
_2),
.soft_reset_0(soft_reset_0),.soft_reset_1(soft_reset_1),.soft_reset_2(soft_reset_2),.fif
o_full(fifo_full),
.low_pkt_valid(low_pkt_valid),.busy(busy),.detect_add(detect_add),.ld_state(ld_state),.l
af_state(laf_state),
.full_state(full_state),.write_enb_reg(write_en_reg),.rst_int_reg(rst_int_reg),.lfd_stat
e(lfd_state));

router_sync
syn(.clk(clk),.rst(rst),.detect_add(detect_add),.write_en_reg(write_en_reg),.data_in(dat
a_in[1:0]),
.full_0(full_0),.full_1(full_1),.full_2(full_2),.empty_0(empty_0),.empty_1(empty_1),.emp
ty_2(empty_2),
.read_enb_0(read_en_0),.read_enb_1(read_en_1),.read_enb_2(read_en_2),
.write_en(write_en),.vld_out_0(vld_out_0),.soft_reset_0(soft_reset_0),.vld_out_1(vld_out
_1),
.soft_reset_1(soft_reset_1),.vld_out_2(vld_out_2),
.soft_reset_2(soft_reset_2),.fifo_full(fifo_full));

router_reg
reg1(.rst(rst),.clk(clk),.pkt_valid(pkt_valid),.data_in(data_in),.fifo_full(fifo_full),.
rst_int_reg(rst_int_reg),
.detect_add(detect_add),.ld_state(ld_state),.laf_state(laf_state),.full_state(full_state
),.lfd_state(lfd_state),
.parity_done(parity_done),.low_pkt_valid(low_pkt_valid),.error(error),.dout(dout));

router_fifo
fifo0(.clk(clk),.rst(rst),.write_en(write_en[0]),.soft_reset(soft_reset_0),.read_enb(rea
d_en_0),.data_in(dout),
.lfd_state(lfd_state),.empty(empty_0),.data_out(data_out_0),.full(full_0));

router_fifo
fifo1(.clk(clk),.rst(rst),.write_en(write_en[1]),.soft_reset(soft_reset_1),.read_enb(rea
d_en_1),.data_in(dout),
.lfd_state(lfd_state),.empty(empty_1),.data_out(data_out_1),.full(full_1));

router_fifo
fifo2(.clk(clk),.rst(rst),.write_en(write_en[2]),.soft_reset(soft_reset_2),.read_enb(rea
d_en_2),.data_in(dout),
.lfd_state(lfd_state),.empty(empty_2),.data_out(data_out_2),.full(full_2));

Endmodule

ROUTER TOP TEST BENCH:

module router_top_tb();

reg clk,rst,read_en_0,read_en_1,read_en_2,pkt_valid;
reg [7:0] data_in;
wire [7:0] data_out_0,data_out_1,data_out_02;
wire vld_out_0,vld_out_1,vld_out_2,error,busy;
integer i;

router_top
dut(clk,rst,read_en_0,read_en_1,read_en_2,pkt_valid,data_in,data_out_0,data_out_1,data_o
ut_02,vld_out_0,vld_out_1,vld_out_2,error,busy);

initial
begin
clk=1'b1;
forever
#5 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst=1'b0;
@(negedge clk)
rst=1'b1;
end
endtask

task initilize;
begin
{pkt_valid,data_in,read_en_0,read_en_1,read_en_2}=0;
end
endtask

task packet_gen_1();
reg [7:0] payload_data,parity,header;
reg[5:0]payload_len;
reg[1:0]address;
begin@(negedge clk);
wait(~busy)
@(negedge clk)
payload_len=6'd14;
address=2'b01;
header={payload_len,address};
parity=0;
data_in=header;
pkt_valid=1;
parity=parity^header;
@(negedge clk);
wait(~busy)
for(i=0;i<payload_len;i=i+1)
begin
@(negedge clk);
wait(~busy)
payload_data={$random}%256;
 data_in=payload_data;
parity=parity^payload_data;
end
@(negedge clk);
wait(~busy)
pkt_valid=0;
data_in=parity;
end
endtask

task packet_gen_2();
reg [7:0] payload_data,parity,header;
reg[5:0]payload_len;
reg[1:0]address;
begin@(negedge clk);
wait(~busy)
@(negedge clk)
payload_len=6'd4;
address=2'b10;
header={payload_len,address};
parity=0;
data_in=header;
pkt_valid=1;
parity=parity^header;
@(negedge clk);
wait(~busy)
for(i=0;i<payload_len;i=i+1)
begin
@(negedge clk);
wait(~busy)
payload_data={$random}%256;
data_in=payload_data;
parity=parity^payload_data;
end
@(negedge clk);
wait(~busy)
pkt_valid=0;
data_in=parity;
end
endtask

task packet_gen_13();
reg [7:0] payload_data,parity,header;
reg[5:0]payload_len;
reg[1:0]address;
begin@(negedge clk);
wait(~busy)
@(negedge clk)
payload_len=6'd12;
address=2'b00;
header={payload_len,address};
parity=0;
data_in=header;
pkt_valid=1;
parity=parity^header;
@(negedge clk);
wait(~busy)
for(i=0;i<payload_len;i=i+1)
begin
@(negedge clk);
wait(~busy)
payload_data={$random}%256;
data_in=payload_data;
parity=parity^payload_data;
end
@(negedge clk);
wait(~busy)
pkt_valid=0;
data_in=parity;
end
endtask

initial
begin
initilize;
reset;
//-------------------
repeat(3) //first clk pulse data wil be there in register
@(negedge clk); //second clk pulse the data will be avilable in the fifo
packet_gen_1; //so wait for two clock pulse
@(negedge clk);
read_en_1=1;
wait(~vld_out_1)
@(negedge clk);
read_en_1=0;
//---------------------
packet_gen_2;
repeat(2)
@(negedge clk)
read_en_2=1;
wait(~vld_out_2)
@(negedge clk);
read_en_2=0;
//----------------------
packet_gen_13;
repeat(2)
@(negedge clk)
read_en_2=1;
wait(~vld_out_2)
@(negedge clk);
read_en_2=0;

#1000; $finish;
end

endmodule