Department of Electrical Engineering

Faculty Member: Sir Mughees Dated: March 11, 2024

Semester:2nd Section: BSCS-13E

Group No.: 7

EE-221: Digital Logic Design

Lab 6: Binary to Gray and Gray to Binary Code Conversion

PLO4/CLO4 PLO4/ PLO5/ PLO8/ PLO9/CLO7

CLO4 CLO5 CLO6
Name Reg. No Viva / Lab Analysis Modern Ethics Individual Total
Performanc of data in Tool and and Team marks
e Lab Usage Safety Work Obtaine
Report d

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25

Marks
Rimsha Nosheen 471832

Mehreen 462557

Ans-Ur-Rehman 473914

Farhan Naveed 466629

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Lab6: Part (a): Binary to Gray and Gray to Binary Code Conversion

Lab6: Part (b): Gate-level Modeling in Verilog

This Lab has been divided into two parts:

In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).

The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.

Objectives:

 Understand steps involved in design of combinational circuits

 Understand binary codes for decimals and their hardware realization
 Write code for combinational circuits using Verilog Gate Level Modeling
 Design a circuit in Verilog by calling different modules

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The students will get
hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
report on LMS for grading.
 The students will start lab task and demonstrate design steps separately for step-wise
evaluation( course instructor/lab engineer will sign each step after ascertaining functional
verification)
 Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back components before
leaving.
 The students will complete lab task and submit complete report to Lab Engineer before leaving
lab.
 The Total duration for the lab is 3 hrs. After lab duration, a deduction of 5 marks per day
will be done for late submission.
 A lab with in-complete lab tasks will not be accepted.
 There are related questions at the end of this activity. Give complete answers.

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Pre-Lab Tasks: (To be done before coming to the lab) (2 marks)

1. What do you mean by binary codes for the decimal digits? Give some examples and codes (tables) for
the decimal digits.

A binary number system is one of the four types of number system. In computer applications, where
binary numbers are represented by only two symbols or digits, i.e. 0 (zero) and 1(one). The binary
numbers here are expressed in the base-2 numeral system. For example, (101)2 is a binary number.
Each digit in this system is said to be a bit.
Examples are excess-3 code, BCD code, 8421 code etc.

Decimal number Binary number

0 0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

10 1010

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 2. What is a self-complementing code? Name any two of them; show their complementing nature with
examples and describe advantages.

If the one's complement of the code is equal to the nine's complement of the code, then it is called a
self complementing code. Such codes have the property that the 9’s complement of a decimal number
is obtained directly by changing 1’s to 0’s and 0’s to 1’s (i.e., by complementing each bit in the pattern).

Examples: The 2421, the excess‐3 and the 8421 codes are examples of self‐complementing codes.

First of all 8421 & 2421 code are "self-complementing code" both (because the necessary condition for
a code to be self-complementing is that the sum of all of its weight must be equal to 9) i.e. 84-2-1(8+4-
2-1=9) and, 2421(2+4+2+1=9).

Decimal 0=0000(in 84-2-1 system) & (9's complement of 0=9) than 9(in 84-2-1) should have 1111.
Hence 0 & its 9's complement i.e. 9 maintain their self-complement relationship.
Decimal 1=0111(in 84-2-1 system) & (9's complement of 1=8 ) that implies (84-2-1) equivalent of 8
should be 1000,hence again the number & its complement preserve their self-complementary relationship.

Advantage:
With self complementing codes, the design of the hardware is easier when it comes to say,
9's complement subtraction. It is a method of subtraction by addition, the negative number is converted
to its 9's complement number. Self complementing codes give an easy way out.

3. In the lab you would be implementing a gray to binary and binary to gray code converter. Make a truth
table for both the codes by filling in the following tables and Simplify the expressions for W,X,Y,Z in terms of
A,B,C,D and vice versa.( Use backside of the page if necessary). Also give some applications in which gray
code could be used.

Applications of Grey Code:

Gray codes are widely used to prevent spurios output from electromechanical switches and to
facilitate error correction in digital communications such as digital terrestrial television and some
cable TV systems. The use of Gray code in these devices helps simplify logic operations and reduce
errors in practice.

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 Dec Binary Gray HINT:
A B C D W X Y Z
Our inputs and outputs are of 4-bit each.
0 0 0 0 0 0 0 0 0 You will have to make 4 K-Maps (Consider
1 0 0 0 1 0 0 0 1 W as independent function of A,B,C,D,
Make K-Map and simplify it). Arrive at the
2 0 0 1 0 0 0 1 1
simplest expression for each output.
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
W=A
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0 X=A X-OR B
8 1 0 0 0 1 1 0 0 Y=B X-OR C
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1 Z=C X-OR D
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

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 K-Maps for Binary to Gray:

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 Dec Gray Binary HINT:
W X Y Z A B C D
Our inputs and outputs are of 4-bit each.
0 0 0 0 0 0 0 0 0 You will have to make 4 K-Maps (Consider
1 0 0 0 1 0 0 0 1 A as independent function of W,X,Y,Z.
Make K-Map and simplify it). Arrive at the
2 0 0 1 1 0 0 1 0
simplest expression for each output.
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
A= W
6 0 1 0 1 0 1 1 0
7 0 1 0 0 0 1 1 1 B= W ^ X
8 1 1 0 0 1 0 0 0 C= (W ^ X) ^ Y
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
D= ((W ^ X)^Y) ^ Z
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1

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K-Maps for Binary to Gray:

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 3. Draw the logic diagram for the Binary-to-Gray and Gray-to-Binary code converters using Exclusive-OR
gates in the space provided below.

Binary Gray Binary

A
W A

B
X B

C
Y C

D
Z D

Only the following gates are available to you for lab tasks.

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Lab Tasks: (To be completed in the lab) (3 marks)
Lab Task 1:

Implement the Binary to Gray Code Converter using logic gates. Make the Schematic Diagram. Show the
results to your Teacher/Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.

We used three XOR gates.

Proteus Simulation:

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Hardware:

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Lab Task 2:

Realize the Gray to Binary Code Converter using exclusive-OR gates. Make the Schematic Diagram. Show the
results to your Teacher/ Lab Engr. What and how many gates did you use? Do not dispatch your hardware.
You will need it in lab task 3.

We used three XOR gates.

Hardware: Apologies Sir, this is cascaded circuit. We forgot to take pictures for grey to binary circuit.

EE-221: Digital Logic Design Page 12

Lab Task 3:

Now cascade the two circuits in series by connecting the outputs of binary-to-gray converter to the inputs of the
gray-to-binary converter. You should be able to get the binary input at output as well. Show the results to your
Teacher/Lab Engr. Use LEDs to show input-output relationship.

Proteus Simulation:

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Hardware:

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Lab Task 4:

Design and simulate the gate-level model of the circuit you patched in task 3. Give the code in the space
provided below.
GATE-LEVEL MODELING:

DATAFLOW MODELING:

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Code:

module LAB6(W,X,Y,Z,A,B,C,D);

input A,B,C,D;

output W,X,Y,Z;

wire w1,w2,w3;

xor X1(w1,A,B);

xor X2(w2,B,C);

xor X3(w3,C,D);

assign W=A;

xor X4(X,A,w1);

xor X5(Y,X,w2);

xor X6(Z,Y,w3);

endmodule

module test_LAB;

reg a,b,c,d;

wire w,x,y,z;

LAB6 l6(w,x,y,z,a,b,c,d);

initial

begin

#100 a = 1'b0; b = 1'b0;c=1'b0;d=1'b0;

#100 a = 1'b0; b = 1'b0;c=1'b0;d=1'b1;

#100 a = 1'b0; b = 1'b0;c=1'b1;d=1'b0;

#100 a = 1'b0; b = 1'b1;c=1'b0;d=1'b0;

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 #100 a = 1'b1; b = 1'b0;c=1'b0;d=1'b0;

#100 a = 1'b1; b = 1'b0;c=1'b0;d=1'b1;

#100 a = 1'b1; b = 1'b0;c=1'b1;d=1'b0;

#100 a = 1'b1; b = 1'b1;c=1'b0;d=1'b0;

#100 a = 1'b1; b = 1'b1;c=1'b0;d=1'b1;

#100 a = 1'b1; b = 1'b1;c=1'b1;d=1'b0;

#100 a = 1'b1; b = 1'b1;c=1'b1;d=1'b1;

#100 a = 1'b0; b = 1'b0;c=1'b1;d=1'b1;

#100 a = 1'b0; b = 1'b1;c=1'b1;d=1'b0;

#100 a = 1'b0; b = 1'b1;c=1'b1;d=1'b1;

#100 a = 1'b0; b = 1'b1;c=1'b0;d=1'b1;

#100 a = 1'b1; b = 1'b0;c=1'b1;d=1'b1;

end

endmodule

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