DIGITAL COMPONENTS

Basic Components
Outline

• Decoders
• Multiplexers
• Registers
• Binary Counters
• Memory
3-to-8 Line Decoder
D0
• A decoder is a combinational circuit
• It activates the output bit that
D1
corresponds to the binary number at
the input
D2
• For n-bit binary input there could be up
to 2n-bit output.
D3
• An n-input m-output decoder is called
an n-to-m line decoder, where m ≤ 2n.
D4

D5

D6

D7
3-to-8 Line Decoder
D0

A B C D0 D1 D2 D3 D4 D5 D6 D7 D1

(0) 0 0 0 1 0 0 0 0 0 0 0 D2
(1) 0 0 1 0 1 0 0 0 0 0 0
(2) 0 1 0 0 0 1 0 0 0 0 0 D3
(3) 0 1 1 0 0 0 1 0 0 0 0
(4) 1 0 0 0 0 0 0 1 0 0 0 D4
(5) 1 0 1 0 0 0 0 0 1 0 0
(6) 1 1 0 0 0 0 0 0 0 1 0 D5
(7) 1 1 1 0 0 0 0 0 0 0 1
D6

D7
Decoder Example
A B C D

Y0

Y1
Y0
• Implement the Y1
A Y2
Y2
following EW
functions using a
Y3 B Y3
decoder and OR Y4 C Y4
gates: Y5 D Y5
Y6
Y6
Y7
EW = Σ (1, 2, 3, 7, 11) Y7
Y8
Y8
Y9
NS = Σ (0, 4, 5, 6, 9, 10, Y9 Y10 NS
12, 13, 14, 15) Y10 Y11
Y11 Y12
Y12
Y13
Y14
Y13
Y15
Y14

Y15
3-to-8 Decoder (74 138)

• The Enable bit, E, enables (when E = 1, i.e. E’=0) or

disables (when E = 0, i.e. E’=1) the functionality of the
decoder.
• When the decoder is disabled (E = 0), all the output
pins of the decoder are reset to 0:

E=G1 • G2AN’ • G2BN’

Encoder

• An encoder is a combinational circuit that performs the

opposite operation of a decoder.
• A 2n-bit input, n-bit output encoder generates the
binary code corresponding to the input value.
Inputs Outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Decoder in Action

Random-access
memory
(RAM)
Decodes CPU device select to enable the output device
Central
Processing Unit
(CPU) Output
Devices
Input Memory stick

Devices Input-output DVD burner

Processor Display
(IOP)
Multiplexer (MUX)

• A multiplexer is a combinational circuit that receives

binary information from one of the 2n input data bits (I0,
I1, …) and directs it to a single output line (Z).
• The selection of a particular input data bit is determined
by a set of n input selection bits (A0, A1, …) .
• It resembles a multi-select contact switch
– Only one connection is active at any time A1 A0 E Z
I0 (x) x x 0 0
I1 (0) 0 0 1 I0
I2 Z
(1) 0 1 1 I1
I3 A1A0
(2) 1 0 1 I2
4-to-1-Line Multiplexer (3) 1 1 1 I3
 4-to-1 line MUX

I0 E A1 A0
D0
I1
D1 I0
Z
I2 D2
I1
I3 Z

D3 I2

0 1 2 3
I3
2-to-4 decoder

A1 A0 E

Design based on 2-to-4 decoder

 MUX in Action
Random-access
memory
(RAM)
MUX let all input devices share one input port Decodes CPU device select to enable the output device

Central
Input Processing Unit
Devices (CPU) Output
Devices
Memory stick

Input-output DVD burner

Processor Display
(IOP)
11
Logic Function Implementation with MUX

• Any n variable function can be implemented with:

1.(2n)-to-1 MUX directly;
2.(2n-1)-to-1 MUX by applying MEV;
3.(2n -k)-to-1 MUX + gates by using func. decomposition
Logic Function Implementation with MUX

1.Using (2n)-to-1 MUX directly

• Example: F(c1,c2,c3,c4) = Σ (1, 2, 3, 7, 11)
0
1
1
1
0
0
0

16x1 MUX
1
0 Σ (1, 2, 3, 7, 11)
0
0
1
0
0
0
0

C1 C2 C3 C4
 Logic Function Implementation with MUX

2. (2n-1)-to-1 MUX by applying MEV

– MEV: Map-Entered Variables
– The idea is: instead of hard coding all outputs (as in
previous example), use a smaller MUX and some logic
to drive the inputs
We have 4 variables C0..3
We have 3 inputs to the MUX C0..2
We use C3 with some logic to drive
all inputs – 4 possibilities:
- Output does not change with C3 8x1 MUX Σ (1, 2, 3, 7, 11)
- Use hard coded value {0,1}
- Output changes with C3
- Use C3 of C3’ as input
(depending on the
input/output relation)
C0 C1 C2
 Logic Function Implementation with MUX

2. (2n-1)-to-1 MUX by applying MEV

– MEV: Map-Entered Variable (C3 in this case)
– The idea is: instead of hard coding all outputs (as in
previous example), use a smaller MUX and some logic
to drive the inputs
We have 4 variables C0..3
We have 3 inputs to the MUX C0..2
We use C3 with some logic to drive
all inputs – 4 possibilities:
- Output does not change with C3
- Use hard coded value 0 or 1
- Output changes with C3 8x1 MUX
- Use C3 or C3’ as input
(depending on the
input/output relation)
Logic Function Implementation with MUX

3. (2n -k)-to-1 MUX + gates by using function

decomposition
– We can use MEV recursively to keep using smaller the
smaller MUX
– The logic will keep getting bigger/more complex each
time
– We can even end up with no MUX and fully gated
function!
– Let’s use 4x1 MUX and include C2 in the gates
Logic Function Implementation with MUX

3. (2n -k)-to-1 MUX + gates by using function

decomposition
– Let’s use 4x1 MUX and include C2 in the gates
– (MEV C2) C2|C2’C3
C2&C3

8x1 MUX
Logic Function Implementation with MUX

4x1 MUX
Logic Function Implementation with MUX

• (2n-1)-to-1 MUX by applying MEV

– What if the function include don’t care bits?
 Use don’t care values to your advantage to match
defined values, i.e. to use hard coded 0 or 1

 Example: F(c1,c2,c3,c4) = Σ (1, 2, 3, 7, 11)

Don’t care = Σ (0, 4, 13)
Logic Function Implementation with MUX

• (2n-1)-to-1 MUX by applying MEV, with don’t care

 Example: F(c1,c2,c3,c4) = Σ (1, 2, 3, 7, 11)
Don’t care = Σ (0, 4, 13) 1

00 0000 X 1
01 0001 1
02 0010 1 0
03 0011 1
04 0100 x C3
05 0101 0
06 0110 0 0
07 0111 1
08 1000 0 C3
09 1001 0
10 1010 0 0
11 1011 1
12 1100 0 0
13 1101 x
14 1110 0
15 1111 0
MEV K-maps Minimization

• Use K-maps to minimize F = Σ (3,7,11,12,13,14,15,16,18)

+ d(24,25,26,27,28,29,30,31).
• To find the simplified function from a MEV K-map,
follow these steps: EPI: Essential Prime Implicants
1. Determine the EPI’s consisting of only 1’s along with
any don't care terms that may exist (i.e., cover the 1’s
in the K-map).
2. Consider the 1’s as don't care terms once step 1 is
completed, because all of the 1’s have been previously
covered.
 MEV m a b c d e F MEV m a b cde F
0 0 0 0000 0 8 16 1 0 000 1
MEV K-maps 1 0 0001 0 17 1 0 001 0
1 2 0 0010 0 9 18 1 0 010 1
3 0 0011 1 19 1 0 011 0
3. Group all identical MEV terms 2 4 0 0 1 0 0 0 10 20 1 0 100 0
with 1’s or don't care terms 5 0 0101 0 21 1 0 101 0
– Write the term AND MEV 3 6 0 0 1 1 0 0 11 22 1 0 110 0
7 0 0111 1 23 1 0 111 0
value 4 8 0 1 0 0 0 0 12 24 1 1 000 x
9 0 1001 0 25 1 1 001 x
– F = bc + a’de + ac’e’
5 10 0 1 0 1 0 0 13 26 1 1 010 x
11 0 1011 1 27 1 1 011 x
cd 6 12 0 1 1 0 0 1 14 28 1 1 100 x
ab 00 01 11 10
0 1 3 2
13 0 1101 1 29 1 1 101 x
00 0 e e 0 7 14 0 1 1 1 0 1 15 30 1 1 110 x
4 5 7 6 15 0 1111 1 31 1 1 111 x
01 0 e 1* 1*
12 13 15 14
11 x x x x
8 9 11 10
10 e’ e’ 0 0
 Registers

• Registers are flip-flop based storage elements that can

be loaded and retrieved in many ways
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Characteristic Equation:
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
Qn+1 = Dn

D C D C D C D C D C D C D C D C
C Dn Qn Qn+1
• • • • • • • 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0 0 1 0
1 0 1
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
1 1 1

C
Characteristic Table
D7 D6 D5 D4 D3 D2 D1 D0
 Register with Parallel Load

Enable Qkn+1 Function Qk Qk

DBk D Q D Q
0 Qkn Store
1 DBk Load CLK Qk CLK Qk
Q Q
R R
=> + <=
Enable = Ld/St CL
Load/Store Enable = Ld/St CL
CK Load/Store Enable = Ld/St
Q0 Q0 Load/Store CL CK
DB0 DB3
Register

Next State Logic CC

State Register

Q1 Q1 0M
Qk
Flip Flops
Sn+1 = δ(Sn,Xn)

DB1 DB2 D Q
U
Q2 Q2 DBk 1
X CLK Qk
DB2 DB1 Q
R
Q3 Q3
DB3 DB0

Load/Store functions combined

 Register with Parallel Load
CL
Enable = Ld/St
Load/Store CK
• 4 bit register with parallel load Q0
0M D Q
U CLK Q0
• When the load input Ld / St = 1, at the positive clock pulse DB0 1
X RQ
transition time, the data in the four input bits DB0 is
transferred into the register; otherwise Q1
• when load input Ld / St = 0, the register output bits maintain 0M D Q
their values. DB1 1
U
CLK Q1
X RQ

The transition function (δ) of the Parallel Register: Q2

Qk(n+1) = Ld DBk + St Qk(n); k={0,1,2,3} 0M
D Q
= Enable DBk + Enable Qk; U
DB2 1 CLK Q2
Step 3 If the Parallel Register is implemented with X RQ
D-FF's, its excitation equation gives: D(n) = Qk(n+1)
Q3
0M D Q
Step 4 => Dk = Enable DBk + Enable Qk; k={0,1,2,3} U
DB3 1 CLK Q3
X R Q
Shift Registers

• A shift register is a register that is capable of shifting

its binary information in one or both directions.
• The logical configuration of a shift register consists of a
chain of cascaded flip-flops.
• The serial input denotes the external input fed into the
shift register.
• The serial output denotes the data that is not fed into
any of the register’s flip-flops.
time Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
n 1 0 1 0 1 0 0 0
Serial
Input = 0 0
n+1 0 1 0 1 0 1 0 0

Right shift register

 Left Shift Register

• The Next State (Sn+1) of a sequential circuit is a function (δ) of its

input (X) and of its present state (Sn): Sn+1 = δ(X, Sn).
• For left shift, the input Xi of each FFi is connected to the FFi-1 output
from its right Xi=Qi-1 => Qin+1= δ(Qi-1n,Qin); i={0,1,2,3}
Left shift register
time Q2 Q1 Q0 Q2 Q1 Q0
n 0 1 0 Serial In
X2 X1 X0
n+1 1 0 0
Serial In
Q2n+1=Q1n Q1n+1=Q0n Q0n+1=SerIn
Right Shift Register
time Q3 Q2 Q1 Q0
• When implementing n 1 0 0 0
with D FF’s: Qn+1 = D Serial In
• So, the output Q of n+1 0 1 0 0
each flip-flop is
connected to the input
D of the next flip-flop
X3 = SerIn X2 = Q 3 X1 = Q 2 X0 = Q 1

D0=Q1
D2=Q3

D1=Q2
serial input = D3
D Q D Q D Q D Q
Q0 =
C C C C
serial
28 output
clock
Multi-function Registers

• Bidirectional Shift Register with Parallel Load is the most

general form of register
– It can be loaded and retrieved serially and in parallel
– It has the following capabilities:
1. clock pulse input to synchronize all operations.
2. shift right operation with a serial input line
3. shift left operation with a serial input line
4. parallel load operation with n input lines
5. n parallel output lines
6. A control state to leave the output lines unchanged
Multi-function Registers

Mode Control Serial In S1 S0

S1 S0 Register operation A3
I3

Register
00 No change (msb)
01 Shift right (msblsb) I2 A2
10 Shift left (lsb  msb)
I1 A1
11 Parallel load
I0 A0
(lsb)
 Multi-function Registers
Serial In S1 S0 CL
CK

f30 0 M D3 Q
f31 1
U A3
f32 2 CLK (msb)
I3 f33 3 X Q
R

f20 0 M D2 Q
f21 1
U A2
S1 S0 Function I2 f23
f22 2
3 X
CLK
Q
R
(f0) 0 0 No Change=Store
(f1) 0 1 Shift Right: direction msb→lsb
(f2) 1 0 Shift Left: direction lsb →msb
f10 M
(f3) 1 1 Parallel Load DB I1
0 D1 Q
f11 1
U A1
f12 2 CLK
f13 3 X Q
R

f00 0 M D0 Q
f01 1
U A0
f02 2 CLK (lsb)
I0 f03 3 X Q
R
Common sense design strategies

• Focus on one bit first. In many cases the rest would

have a similar pattern.
• Try to reason with your own words. Do the
computation with “words" first.
• See if you can define the “rules" governing the
logic circuit, and put them in your own words.
• The above design strategies may save you a significant
amount of time and facilitate your task as a designer.
However, they may not be trivial in all the cases.
 Top-down design
Serial In S1 S0 Serial In
S1 S0
A3 Q3
I3 I3
Register

(msb)

Next State Logic CC

State Register
Q2

Flip Flops
Sn+1 = δ(Sn,Xn)
I2 A2 I2
Q1
I1 A1 I1
A0 (lsb) Q0
I0 I0

Steps 1,2
S1 S0 Akn+1 Function
(f0) 0 0 Akn No Change=Store (k={0,1,2,3})
(f1) 0 1 Ank+1 Shift Right (k={0,1,2}: msb->lsb & D3=Serial In)
(f2) 1 0 Ank-1 Shift Left (k={1,2,3}: lsb => msb & D0=Serial In)
(f3) 1 1 Ik Parallel Load (k={0,1,2,3})

State / Transition
Table (MEV format)
 Top-down design S1 S0 CL
CK

S1 S0 Dk = Akn+1 0 M D3 Q
Serial In 1
U A3
(f0) 0 0 Dk = Ak ; k={0,1,2,3} 2 CLK (msb)
(f1) 0 1 Dk = Ak+1 ; k={0,1,2} I3 3 X Q
R
Steps 3,4 D3=Serial In
D-FF's (f2) 1 0 Dk = Ak-1 ; k={1,2,3}
excitation D0=Serial In 0 M D2 Q
1 A2
equations (f3) 1 1 Dk = Ik ; k={0,1,2,3} 2
U
CLK
I2 3 X Q
R

Step 5: Implementation
0 M D1 Q
1
U A1
2 CLK
I1 3 X Q
R

0 M D0 Q
Serial In
1
U A0
2 CLK (lsb)
3 X Q
I0 R
Four‐bit universal
shift register
FPGA Programmable Logic Element

• A field-programmable gate array (FPGA) is

an integrated circuit designed to be configured after
manufacturing – hence the term "field-programmable“
• he FPGA configuration is generally specified using
a hardware description language (HDL), similar to that
used for an application-specific integrated
circuit (ASIC).
• Circuit diagrams were previously used to specify the
configuration, but this is increasingly rare due to the
advent of electronic design automation tools.
• FPGAs contain an array of programmable logic blocks,
and a hierarchy of reconfigurable interconnects that
allow the blocks to be wired together
 TDI
ABC
D
Ck f(0,0,0)
Q

FPGA Programmable Logic 0

D
Truth Table Ck
Q
f(0,0,1)
1
A B C f(A,B,C)
D
Ck f(0,1,0)
0 0 0 f(0,0,0) Q
2

„Programmable
0 0 1 f(0,0,1)

Inverter”
D
Ck f(0,1,1) M
Q
0 1 0 f(0,1,0) 3

0 1 1 f(0,1,1) D
Ck
Q
f(1,0,0) U f(A,B,C)
1 0 0 f(1,0,0) 4

1 0 1 f(1,0,1) D
Ck f(1,0,1) X
Q
5
1 1 0 f(1,1,0)
D
Ck f(1,1,0)
1 1 1 f(1,1,1) Q
6

Clk · Prog D
Ck f(1,1,1)
Q
TDO 7
FPGA
FPGA

1. FPGA is made up of thousands of Logic Elements

(LE's). Each LE is really a little general purpose Gate,
typically it will have a couple of flip flops, some AND,
OR, NOT gates and maybe a few other tid bits thrown
in depending on which brand.
2. Then there are the IO Blocks. Each IO Block is
completely configurable to be input, output or
bidirectional, as well as a few other things like
programmable pull up resistors and voltage levels.
3. RAM blocks
4. Programmable Interconnect: is a special type of
static RAM, each "bit" connects the input or output of
an LE, IO ro RAM block to a 1 bit bus or rail, or you can
think of it as a wire
 Counters

• Counters are registers that goes through a prescribed

series of states
– Asynchronous Counters: also known as Ripple
counters Flip flop’s output’s serve as clock for
triggering connected flip flops

Q0 Q1 Q2

clk

0 1 0 2 3 2 0 4 5 4 6 7 6 4 0

BAD
Counters

– Synchronous counters: All flip flops are triggered

by a clock signal at the same time
• Example: Modulo 16 synchronous counter
Modulo 16 synchronous counter-D
Q3 Q2 Q1 Q0 0 2 3 4 5
1
CL
4-Bit BINARY 15 6
COUNTER
CK
14 7
CL
3
Q = Σ Qi . 2i 13 12 11 10 9 8
i=0

1
CK
0
1
CL 0

Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6

Using D flip-flops
 Modulo 16 synchronous counter-D
DECIMAL Present STATE OF The next state = D0 D1
Q3 Q2 Q3 Q2
STATE THE COUNTER FLIP FLOP INPUTS
Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10
Q Q3 Q2 Q1 Q0 D3 D2 D1 D0
00 1 1 1 1 00 0 0 0 0
0 0 0 0 0 0 0 0 1 01 0 0 0 0 01 1 1 1 1
1 0 0 0 1 0 0 1 0
11 0 0 0 0 11 0 0 0 0
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 1 0 0 10 1 1 1 1 10 1 1 1 1
4 0 1 0 0 0 1 0 1
5 0 1 0 1 0 1 1 0
6 0 1 1 0 0 1 1 1
7 0 1 1 1 1 0 0 0 Q3 Q2 D2 Q3 Q2 D3
8 1 0 0 0 1 0 0 1 Q1 Q0 00 01 11 10 00 01 11 10
Q1 Q0
9 1 0 0 1 1 0 1 0
10 1 0 1 0 1 0 1 1 00 0 1 1 0 00 0 0 1 1
11 1 0 1 1 1 1 0 0
12 1 1 0 0 1 1 0 1 01 0 1 1 0 01 0 0 1 1
13 1 1 0 1 1 1 1 0 11 1 0 0 1 11 0 1 0 1
14 1 1 1 0 1 1 1 1
15 1 1 1 1 0 0 0 0 10 0 1 1 0 10 0 0 1 1

Using D flip-flops has the distinct advantage of a straightforward definition of the flip-flop
The current state of these inputs is the next state of the counter Q n+1 = Dn
 Modulo 16 synchronous counter-D
Dn = Qn+1
Q3 Q2 D3 Q3 Q2 D2
Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10

00 0 0 1 1 00 0 1 1 0

01 0 0 1 1 01 0 1 1 0
11 0 1 0 1 11 1 0 0 1
10 0 0 1 1 10 0 1 1 0

D3 = Q3. Q2 + Q3. Q1 + Q3.Q0 + Q3.Q2.Q1.Q0 D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0

Q3 Q2 D1 Q3 Q2 D0
00 01 11 10 Q1 Q0 00 01 11 10
Q1 Q0
1 1 1 1 D0 = Q0
00 0 0 0 0 D1 = Q1. Q0 + Q1. Q0 00

1 1 1 1 01 0 0 0 0
01
11 11 0 0 0 0
0 0 0 0
10 1 1 1 1 10 1 1 1 1
 CL CK
Q0
D Q

CLK Q0
Q
R

Q1
D Q

CLK Q1
Q
R

D0 = Q0
Q2
D1 = Q1. Q0 + Q1. Q0 D Q

CLK Q2
D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0 R
Q

D3 = Q3. Q2 + Q3. Q1 + Q3.Q0

+ Q3.Q2.Q1.Q0 D Q
Q3

CLK Q3
Q
R
Modulo 16 synchronous counter-JK
Q3 Q2 Q1 Q0 0 2 3 4 5
1
CL
4-Bit BINARY 15 6
COUNTER
CK
14 7
CL
3
Q = Σ Qi . 2i 13 12 11 10 9 8
i=0

1
CK
0
1
CL 0

Q 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6

Using JK flip-flops
 Modulo 16 synchronous counter-JK

• Common sense design approach:

We can notice from the State Table that:
1. A0 toggles its value at each clock pulse – always increment
=> J0 = 1 ; K0 = 1.
2. A1 toggles its value at time T only if at time (T - 1) A0 is 1.
increment every second pulse

J1 = K1 = A0 (T - 1)
Qn Qn+1 Jn Kn
0 0 0 x
Present State Next State Flip-Flop Inputs
A2 (T − 1) A1 (T − 1) A0 (T − 1) A1 (T ) J1 K1 0 1 1 x
x x 0 A1 (t − 1) 0 0 1 0 x 1
x x 1 1 1
(A1 (t − 1))’ 1 1 x 0
 Modulo 16 synchronous counter-JK

• Common sense design approach:

We can notice from the State Table that:
3. A2 toggles its value at time T only if at time (T - 1)
A1 = 1 and A0 = 1, increment only when the count
modulo 4 = 3

Present State Next State Flip-Flop Inputs Qn Qn+1 Jn Kn

A2 (T − 1) A1 (T − 1) A0 (T − 1) A2 (T ) J2 K2 0 0 0 x
x 0 0 A2 (t − 1) 00
x 0 1 A2 (t − 1) 00 0 1 1 x
x 1 0 A2 (t − 1) 00 1 0 x 1
x 1 1 (A2 (t − 1))' 11
J2 = K2 = A1 (T - 1) A0 (T - 1) 1 1 x 0
 Present state Next state
State transition Sn Sn +1
A A3 A2 A1 A0 A3+ A2+ A1+ A0+

0 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1 0
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 1 0 0
4 0 1 0 0 0 1 0 1
5 0 1 0 1 0 1 1 0
6 0 1 1 0 0 1 1 1
7 0 1 1 1 1 0 0 0
8 1 0 0 0 1 0 0 1
9 1 0 0 1 1 0 1 0
10 1 0 1 0 1 0 1 1
11 1 0 1 1 1 1 0 0
12 1 1 0 0 1 1 0 1
13 1 1 0 1 1 1 1 0
14 1 1 1 0 1 1 1 1
15 1 1 1 1 0 0 0 0
 Use the “Common
Present state Sn Next state Sn +1 A3 input A2 input A1 input A0 input sense” design approach
A3 A2 A1 A0 A3+ A2+ A1+ A0+ J3 K3 J2 K2 J1 K1 J0 K0 -> see previous slide
A
0 0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
1 0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
2 0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
3 0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
4 0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
5 0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
6 0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
A0
7 0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
8 1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x
9 1 0 0 1 1 0 1 0 x 0 0 x 1 x x 1 A1A0
10 1 0 1 0 1 0 1 1 x 0 0 x x 0 1 x
11 1 0 1 1 1 1 0 0 x 0 1 x x 1 x 1
12 1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x A2A1A0
13 1 1 0 1 1 1 1 0 x 0 x 0 1 x x 1
14 1 1 1 0 1 1 1 1 x 0 x 0 x 0 1 x
15 1 1 1 1 0 0 0 0 x 1 x 1 x 1 x 1 50
Present state Sn Next state Sn +1 A3 input A2 input A1 input A0 input
A3 A2 A1 A0 A3+ A2+ A1+ A0+ J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1 J0
A1A0
0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x \A3A
2 00 01 11 10
0 1 0 1 0 1 1 0 0 x x 0 1 x x 1 00 1 1 1 1
01 X X X X
0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x 11 1 1 1 1
10 X X X X
0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
K0
1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x A1A0
\A3A
1 0 0 1 1 0 1 0 x 0 0 x 1 x x 1 2 00 01 11 10
00 X X X X
1 0 1 0 1 0 1 1 x 0 0 x x 0 1 x 01 1 1 1 1
11 X X X X
1 0 1 1 1 1 0 0 x 0 1 x x 1 x 1 10 1 1 1 1

1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x
1 1 0 1 1 1 1 0 x 0 x 0 1 x x 1 J0 = 1
1 1 1 0 1 1 1 1 x 0 x 0 x 0 1 x K0 = 1
1 1 1 1 0 0 0 0 x 1 x 1 x 1 x 1
 Present state Sn Next state Sn +1 A3 input A2 input A1 input A0 input
A3 A2 A1 A0 A3+ A2+ A1+ A0+ J3 K3 J2 K2 J1 K1 J0 K0
A
0 0 0 0 0 0 0 0 1 0 x 0 x 0 x
1 0 0 0 1 0 0 1 0 0 x 0 x 1 x
2 0 0 1 0 0 0 1 1 0 x 0 x x 0 A1A0
\A3A
3 0 0 1 1 0 1 0 0 0 x 1 x x 1 2 00 01 11 10
00 0 0 0 0
4 0 1 0 0 0 1 0 1 0 x x 0 0 x 01 1 1 1 1
11 X X X X
5 0 1 0 1 0 1 1 0 0 x x 0 1 x 10 X X X X

6 0 1 1 0 0 1 1 1 0 x x 0 x 0 K1
A1A0
7 0 1 1 1 1 0 0 0 1 x x 1 x 1 \A3A
2 00 01 11 10
8 1 0 0 0 1 0 0 1 x 0 0 x 0 x 00 X X X X
01 X X X X
9 1 0 0 1 1 0 1 0 x 0 0 x 1 x 11 1 1 1 1
10 0 0 0 0
10 1 0 1 0 1 0 1 1 x 0 0 x x 0

J1 = A0
11 1 0 1 1 1 1 0 0 x 0 1 x x 1
12 1 1 0 0 1 1 0 1 x 0 x 0 0 x
13 1 1 0 1 1 1 1 0 x 0 x 0 1 x
K1 = A0
14 1 1 1 0 1 1 1 1 x 0 x 0 x 0
15 1 1 1 1 0 0 0 0 x 1 x 1 x 1
 Present state Sn Next state Sn +1 A3 input A2 input A1 input A0 input
A3 A2 A1 A0 A3+ A2+ A1+ A0+ J3 K3 J2 K2 J1 K1 J0 K0
A
0 0 0 0 0 0 0 0 1 0 x 0 x
1 0 0 0 1 0 0 1 0 0 x 0 x
2 0 0 1 0 0 0 1 1 0 x 0 x
3 0 0 1 1 0 1 0 0 0 x 1 x
4 0 1 0 0 0 1 0 1 0 x x 0 J2
A1A0
5 0 1 0 1 0 1 1 0 0 x x 0 \A3A
2 00 01 11 10
6 0 1 1 0 0 1 1 1 0 x x 0 00 0 X X 0
01 0 X X 0
7 0 1 1 1 1 0 0 0 1 x x 1 11 1 X X 1
10 0 X X 0
8 1 0 0 0 1 0 0 1 x 0 0 x
K2
9 1 0 0 1 1 0 1 0 x 0 0 x A1A0
\A3A
10 1 0 1 0 1 0 1 1 x 0 0 x 2 00 01 11 10
00 X 0 0 X
11 1 0 1 1 1 1 0 0 x 0 1 x 01 X 0 0 X
11 X 1 1 X
12 1 1 0 0 1 1 0 1 x 0 x 0 10 X 0 0 X

13 1 1 0 1 1 1 1 0 x 0 x 0 J2 = A0A1
14 1 1 1 0 1 1 1 1 x 0 x 0 K2 = A0A1
15 1 1 1 1 0 0 0 0 x 1 x 1
 Present state Sn Next state Sn +1 A3 input A2 input A1 input A0 input
A3 A2 A1 A0 A3+ A2+ A1+ A0+ J3 K3 J2 K2 J1 K1 J0 K0
A
0 0 0 0 0 0 0 0 1 0 x
1 0 0 0 1 0 0 1 0 0 x
2 0 0 1 0 0 0 1 1 0 x
3 0 0 1 1 0 1 0 0 0 x
4 0 1 0 0 0 1 0 1 0 x J3
A1A0
5 0 1 0 1 0 1 1 0 0 x \A3A
2 00 01 11 10
6 0 1 1 0 0 1 1 1 0 x 00 0 0 X X
01 0 0 X X
7 0 1 1 1 1 0 0 0 1 x 11 0 1 X X
10 0 0 X X
8 1 0 0 0 1 0 0 1 x 0
K3
9 1 0 0 1 1 0 1 0 x 0 A1A0
\A3A
10 1 0 1 0 1 0 1 1 x 0 2 00 01 11 10
00 X X 0 0
11 1 0 1 1 1 1 0 0 x 0 01 X X 0 0
12 1 1 0 0 1 1 0 1 x 0 11 X X 1 0
10 X X 0 0
13 1 1 0 1 1 1 1 0 x 0
J3 = A0A1A2
K3 = A0A1A2
14 1 1 1 0 1 1 1 1 x 0
15 1 1 1 1 0 0 0 0 x 1
 Modulo 16 counter-JK

J0 A1A0 J2 J3
A1A \A3A A1A0 A1A0
0\A3 2 00 01 11 10 \A3A \A3A
A2 00 01 11 10 00 0 0 0 0 2 00 01 11 10 2 00 01 11 10
00 1 1 1 1 01 1 1 1 1 00 0 X X 0 00 0 0 X X
01 X X X X 11 X X X X 01 0 X X 0 01 0 0 X X
11 1 1 1 1 10 X X X X 11 1 X X 1 11 0 1 X X
10 X X X X 10 0 X X 0 10 0 0 X AX0
K1
K0 A1A0 K2 K3
A1A \A3A A1A0 A1A0
0\A3 2 00 01 11 10 \A3A \A3A
A2 00 01 11 10 00 X X X X 2 00 01 11 10 2 00 01 11 10
00 X X X X 01 X X X X 00 X 0 0 X 00 X X 0 A01A0
01 1 1 1 1 11 1 1 1 1 01 X 0 0 X 01 X X 0 0
11 X X X X 10 0 0 0 0 11 X 1 1 X 11 X X 1 0
10 1 1 1 1 10 X 0 0 X 10 X X 0 0

J0 = 1 J1 = A0 J2 = A0A1 J3 = A0A1A2A A A 2 1 0

K0 = 1 K1 = A0 K2 = A0A1 K3 = A0A1A2
 Binary Counter with Parallel Load

• Multifunction Register with D-Flip Flops

S1 S0 Qkn+1 Function
(f0) 0 0 Qkn Store
k = {0,1,2,3}
(f1) 0 1 Nk Count up Multifunction Register
(f2) 1 0 DBk Load implemented as a Sequential Circuit
(f3) 1 1 0 Clear S1 S0
S1 S0
Q3 Q3

Multifunction
DB3 DB3
(msb)

Next State Logic CC

State Register
Register
Q2 Q2

Flip Flops
Sn+1 = δ(Sn,Xn)
DB2 DB2
Q1 Q1
DB1 DB1
Q0 Q0
DB0 DB0
(lsb)
Binary Counter with Parallel Load S1 S0 CL
CK

f00 0 M D0 Q Q0
f01 1
U (lsb)
f0 2 2 CLK
f0 3 3 X Q
R

f10 0 M D1 Q1
Q
f11 1
U
f 12 2 CLK
f1 3 3 X Q
R

f20 0 M D2 Q2
Q
f21 1
U
f 22 2 CLK
f2 3 3 X Q
R

f30 0 M D3 Q3
Q
f31 1
U (msb)
f 32 2 CLK
f3 3 3 X Q
R
Binary Counter with Parallel Load

• Use the “Common sense” design approach, (where

obvious) or D- FF’s excitation equation: Dn = Qn+1 (1)

Store (f0): Qn+1 = Qn (2) to be implemented with D-FF

From (1), (2) => Dn = Qn+1= Qn i.e., Dk = Qk, k ={0,1,2,3}

Clear (f3): Qn+1 = 0 (3) with D-FF

From (1), (3) => Dn = 0 i.e., Dk = 0, k ={0,1,2,3}

Load (f2): Qn+1 = DBn (4) with D-FF

From (1), (4) => Dn = DBn, i.e., Dk = DBk, k ={0,1,2,3}
 Count up (f2) – as before! CLR
CK
Q0
D Q

CLK
Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ D3 D2 D1 D0 Q
R
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 0 Q1
D Q
0 0 1 0 0 0 1 1 0 0 1 1
CLK Q1
0 0 1 1 0 1 0 0 0 1 0 0 Q
R
0 1 0 0 0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0 0 1 1 0
Q2
0 1 1 0 0 1 1 1 0 1 1 1 D Q
0 1 1 1 1 0 0 0 1 0 0 0 CLK Q2
Q
1 0 0 0 1 0 0 1 1 0 0 1 R
1 0 0 1 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 1 1 Q3
D Q
1 0 1 1 1 1 0 0 1 1 0 0
CLK Q3
1 1 0 0 1 1 0 1 1 1 0 1 Q
R
1 1 0 1 1 1 1 0 1 1 1 0
1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 0 0 0 0 0 0 0 0
 CL
A1A0 2 CK
Q0
0
Multifunction 1
M D Q
U CLK
2
Register DB0
0 3
X
R
Q

Implementation
Q1
0
M D Q
A1 A0 Dk= Qkn+1 Function 1
U
2
CLK Q1
(f0) 0 0 Qkn Store DB1 X Q
0 3 R
(f1) 0 1 Nk Count up
(f2) 1 0 DBk Load
(f3) 1 1 0 Clear Q2
0 D Q
M
1
U CLK Q2
2
DB2 X Q
0 3 R

Q3
0
M D Q
1
U CLK Q3
2
DB3 X Q
0 3 R
 Binary Counter with Parallel Load

• Multifunction Register with JK-Flip Flops Multifunction Register

implemented as a Sequential Circuit

S1 S0
S1 S0
Q3 Q3

Multifunction
DB3 DB3
(msb)

Next State Logic CC

State Register
Register
Q2 Q2

Flip Flops
Sn+1 = δ(Sn,Xn)
DB2 DB2
Q1 Q1
DB1 DB1
DI0 D0 Q0 Q0
DB0 DB0
D1 (lsb)
DI1 Z
DI2 D2
DI3 k = {0,1,2,3} Qn Qn+1 Jn Kn
D3
0 1 2 3 S1 S0 Qkn+1 Function 0 0 0 x
2-to-4 decoder MUX (f0) 0 0 Qkn Store
(f1) 0 1 Nk Count up
0 1 1 x
S1 S0 E
(f2) 1 0 DBk Load 1 0 x 1
(f3) 1 1 0 Clear
1 1 x 0
Binary Counter with Parallel Load

k = {0,1,2,3}
S1 S0 Qkn+1 Function
(f0) 0 0 Qkn Store
(f1) 0 1 Nk Count up
(f2) 1 0 DBk Load
(f3) 1 1 0 Clear
 D-Latch using JK FF

START HERE
D Qn Qn+1
D J Q Given:
δ 0 0 0 D-Latch
0 1 0 Characteristic
K
1 0 1 Table
1 1 1
1

JK Excitation Table
D Qn Qn+1 J K Qt Qt+Δt Jt Kt
0 0 0 0 x 0 0 0 x
0 1 0 x 1 0 1 1 x
1 0 1 1 x 1 0 x 1
1 1 1 x 0
1 1 x 0
Excitation table for
Sequential Circuit to be Designed

Step 3
 D-Latch using JK FF

Step 4: SR input Step 5

J equations
4
D Qn 0 1

0 0 0 01 D J Q
1 1 2 x3 J=D
5
K=D K
K D
4
D Qn Qn+1 J K D Qn 0 1
0 0 0 0 x
0 x 0 11 D Clock
0 1 0 x 1
1 0 1 1 x 1 x2 0 3
1 1 1 x 0

Excitation table for

Sequential Circuit to be Designed

Step 3
 State Encoding mod 4 counter

1. Two bit counter, followed by decoder

2. 1-hot encoding, ring counter

S3 S2 S1 S0 S3 S2 S1 S0

D S Q D Q D Q D Q
2-to-4 decoder C C C C
R R R
Clock
1 T Q T Q
RST
C C

Clock