DIGITAL LOGIC CIRCUITS

Hardware for Boolean Algebra

Outline

• Boolean Algebra
• Logic Functions Representation
• Logic Gates
• Logic Functions Minimization
• Combinational Circuits
• Sequential Circuits
 Logic Functions
zi = Fi(x0,x1,x2, …) | zi {0,1}, i = 0,1,2, … m-1, xk {0,1}, k = 0,1,2, …n-1
where Fi = logic functions ; xk = input variables; zi = output variables
where Logic 0 = FALSE and Logic 1 = TRUE

Logic function F
Block diagram
x0
x1
Logic z
x2 Circuit
F(x0,x1,x2,x3)
x3
Logic Functions
Logic Inverter
can be represented by
1. truth tables,
Logic function F 2. logic (Boolean) expressions,
3. logic diagrams (schematics) of the logic
x z circuits that implement these functions.
0 1 4. K-maps – later!
1 0 Time diagrams
x (functional simulation)
VHi ≈ +5V =
TRUE = Logic 1
z=x U1A VLo ≈ 0V =
x 1 2
z FALSE = Logic 0
t
0 10 20 30 40 50 [ns]
z (Ideal) time diagram
7404
1

0 0 10 20 30 40 50
t
[ns]
 Realistic Time Diagrams

Approximations of Real Time-Diagrams

x
VHi ≈ +5V =
TRUE = Logic 1

Propagation Delay VLo ≈ 0V =

t
Logic Inverter FALSE = Logic 0
0 10 20 30 40 50 [ns]
z
U1A
x z 1
1 2

7404 0 t
z=x 0 10 20
td propagation delay
30 40 50 [ns]

x z
0 1
1 0
 Realistic Time Diagrams

Approximations of Real Time-Diagrams

x
1

Rise / Fall Time

50%

t
0
Logic Inverter z
0 10 20 30 40 50 [ns]
U1A 1
x z 90%
1 2
50%

10%
0
7404 t
z=x 0 10
td
20
tr
30
tf 6
40 50 [ns]
delay rise time fall time

x z
0 1
1 0
Boolean Algebra over {0, 1}

• ,=,+,., , 0,1
• The algebra is defined over a field B that contain only
two elements {0, 1}
• There are three operations in the field:
1. .: AND binary operation
2. +: OR binary operation
3. : NOT unary operation
• Boolean Algebra is closed on the field B, i.e. the result
of any operation lies in B, i.e. is either 0 or 1
Boolean Algebra over {0, 1}

• Equivalence relationship ‘=‘ with the following

properties:
 reflexivity: ( x  B)  (x = x)
 symmetry: ( x, y  B)  (x = y  y = x)
 transitivity: ( x, y, z  B)  (x = y, y = z  x = z)
• Parentheses are allowed
Boolean Algebra over Boolean Vectors

• = ⋯, {0,1} is a Boolean vector

• Boolean operations are performed on element by
element
• ,=,+,., , 00 … 0 , {11 … 1}
• AND: A.B = {a1.b1, a2.b2 , …, an.bn }
• OR: A+B = {a1+b1, a2+b2 , …, an+bn }
• NOT: = ⋯
Boolean Axioms

Property OR AND
Closeness a + b = c → c ε {0,1} a . b = c → c ε {0,1}
Identity a+0=a a.1=a
0 is identity for OR 1 is identity for AND
Commutative a+b=b+a a.B=b.a
Distributive a+(bc) = (a+b)  (a+c) a  (b + c) = ab + ac
Complement a+a=1 aa=0
Associative (a + b) + c = a + (b + c) (a  b) c = a (b  c)
Boolean Theorems

Theorem OR AND
Idempotency + = . =
Null + 1= 1 .0 = 0
Absorption + . = . + =
+ . = + . + = .
Uniting . + . = + . + =
Consensus . + . + . + . + . .c
= . + ( . ) = a + b .( . )
Factoring + . + . + .
= . + ( . ) = + .( + )
De Morgan’s Theorems

• Very important theorem!

OR AND
+ = . . = +
+ + + ⋯= . . … . . …= + + + ⋯
Proving Theorems using Axioms

• Rewrite expression and utilize axioms

• Prove the theorem: X • Y + X • Y' = X
– Using distributive axiom LHS = X.(Y+Y’)
– Using complementarity LHS = X.1
– Using identity LHS = X = RHS
• Prove the theorem: X + X • Y = X
– Using identity X + X • Y = X • (1) + X • Y
– Using distributive axiom X • (1) + X • Y = X • (1+Y)
– Using null axiom X • (1+Y) = X • 1
– Using identity axiom X • 1 = X
Proving Theorems using Axioms

• Rewrite expression and utilize axioms

• Prove Consensus theorem:
– . + . + . = . + ( . )
– LHS = . + . + .
– Using identity LHS = . + ( + ) . + .
– Using distributive LHS = . + . . + . . + .
– Regrouping LHS = . + ( . . ) + ( . . ) + .
– Using distributive LHS = . . 1 + + . . (1 + )
– Using identity LHS = . + . = RHS
Proving Theorem using Truth Table

• Truth table is a unique signature of a Boolean

function
a Logic
• A function with n input binary variable will f
b Circuit
require 2 of inputs to exhaustively cover all
n
f(a,b,c)
c
input combinations
• For each input combination evaluate the a b c f
corresponding output f 22 21 20
(0)
– Example 3 inputs a,b,c require 8 0 0 0 0
combinations range [0,7]
(1)
0 0 1 0
(2)
0 1 0 0
(3)
0 1 1 1
(4)
1 0 0 0
(5)
1 0 1 0
(6)
1 1 0 0
(7)
1 1 1 1
 Proving Theorems (Perfect Induction)
“ Proof ”: X. (Y+Z) = X.Y+X.Z
AND rules (identities)
X. X.Y+X.
X Y Z Y+Z XY XZ
. .
(Y+Z) Z
(2) 0.X=0 000 0 0 0 0 0
(4) 1 .X = X
001 1 0 0 0 0
(6) X .X = X
X .X = 0 010 1 0 0 0 0
(8)
011 1 0 0 0 0
(10) X .Y = Y .X 100 0 0 0 0 0
(12) X . (Y . Z) = (X . Y) . Z 101 1 1 0 1 1
(13) X . (Y + Z) = X . Y + X . Z
110 1 1 1 0 1
(16) X .Y = X + Y
111 1 1 1 1 1
 Proving Theorems (Perfect Induction)
“ Proof ”: X+Y.Z = (X+Y).(X+Z)

OR rules (identities)

(1) X Y Z X + Y.Z (X+Y) . (X+Z)

0+X=X _____________________________________________________________________

(3) 1+X=1 0 0 0 0 0
(5) X+X=X 0 0 1 0 0
(7) X+X=1 0 1 0 0 0
(17) (X) = X 0 1 1 1 1
1 0 0 1 1
(9) X+Y=Y+X 1 0 1 1 1
(11) X + (Y + Z) = (X + Y) + Z 1 1 0 1 1
(14) 1 1 1 1 1
X + Y . Z = (X+Y) . (X+Z)
(15) X+Y=X.Y
 Proving DeMorgan’s Theorem
ab  ab
ab  ab
a b a.b a+b a+b a.b
a + b = a.b
_______________________________

0 0 1 1 1 1
0 1 0 0 1 1
a.b=a+b 1 1
1 0 0 0
1 1 0 0 0 0

 can be generalized:
x1  x 2  x n  x1  x 2  x n

x1  x 2  x n  x1  x 2  x n

 All Logic Functions of Two Variables

• 16 possible functions of 2 input variables:

n
– 2^(2^n) = functions of n inputs 2
2
x F Map 1st
y row to 23

x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15

0X 0Y 0 0 0 0 0 016 possible
0 0 functions
1 1 (F0–F15)
1 1 1 1 1 1
00 10 00 00 00 00 10 10 10 10 01 01 01 01 11 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
11 00 00 00 11 11 00 00 11 11 00 00 11 11 00 0 0 1 1 1 1
11 11 00 11 00 11 00 11 00 11 00 11 00 11 00 1 1 0 0 1 1
0 1 Map last
X Y not Y not X
X and Y X xor Y X=Y X nand Y
Row to 20

X or Y X nor Y not (X and Y)

not (X or Y)
Digital Logic Gates
Sum of Product (SoP) Representation

• We can uniquely define a logic function A Logic F

using its truth table B Circuit
F(A,B,C)
• Focusing on the terms where the function C
evaluates to TRUE min-
– We can represent the function by Oring term A B C F
all input combinations that evaluate to (m0) 0 0 0 0
TRUE (m1) 0 0 1 0
(m2) 0 1 0 1
(m3) 0 1 1 1
(SoP): F = ABC + ABC + ABC + ABC (m4) 1 0 0 0
Sum of minterms: F = m2 + m3 + m5 + m7 (m5) 1 0 1 1
F = Σ (2, 3, 5, 7) (m6) 1 1 0 0
(m7) 1 1 1 1

Map to 22 Map to 20
Sum of Product (SoP) Representation
A B C
A Logic F
B Circuit
C F(A,B,C)
A.B .C
min-
term A B C F
A.B .C
(m0) 0 0 0 0
F (m1) 0 0 1 0
A.B .C (m2) 0 1 0 1
(m3) 0 1 1 1
A.B .C (m4) 1 0 0 0
(m5) 1 0 1 1
(m6) 1 1 0 0
A B C (m7) 1 1 1 1
A B C

(SoP): F = ABC + ABC + ABC + ABC

Sum of minterms: F = m2 + m3 + m5 + m7
F = Σ (2, 3, 5, 7)
 Product of Sum (PoS) Representation

• By applying De Morgan’s Theorem on the SoP

representation we get the PoS representation!
A B C (SoP): F = ABC + ABC + ABC + ABC min-
(PoS): F = (A+B+C) (A+B+C) (A+B+C) (A+B+C) term A B C F
(m0) 0 0 0 0
(m1) 0 0 1 0
(m2) 0 1 0 1
(m3) 0 1 1 1
F (m4) 1 0 0 0
(m5) 1 0 1 1
(m6) 1 1 0 0
(m7) 1 1 1 1
Karnaugh Maps

• Karnaugh map is a graphical representation of a truth

table of a logic function.
• Each line in the truth table (minterm) corresponds to a
square in the Karnaugh map.
• The Karnaugh map squares are labeled so that
horizontally or vertically adjacent squares differ only in
one variable. (Each square in the top row is considered
to be adjacent to a corresponding square in the bottom
row. Each square in the left most column is considered
to be adjacent to a corresponding square in the right
most column.)
B 011 111
A BC 00 01 11 10 010 110
0 0 1 3 2
B C 001
4 5 7 6
101
A 1
000 A
C 100
 Karnaugh Maps – 4 Variables
Map to 23 22 21 20
Map to 23 22 21 20
Numerical equivalent of logic combinations ABCD

C
A B C D F
read as binary values with A = msb and D = lsb

AB CD 00 01 11 10
(0) 0 0 0 0 ... 0 1 3 2
(1) 0 0 0 1 ... 00
4 5 7 6
(2) 0 0 1 0 ... 01
(3) 0 0 1 1 ... 12 13 15 14 B
11
(4) 0 1 0 0 ... A 8 9 11 10
(5) 0 1 0 1 ... 10
(6) 0 1 1 0 ... D
(7) 0 1 1 1 …
(8) 1 0 0 0 …
(9) 1 0 0 1 … The minterms are listed by an
(10) 1 0 1 0 … equivalent decimal number for
(11) 1 0 1 1 … easy reference
(12) 1 1 0 0 …
(13) 1 1 0 1 …
(14) 1 1 1 0 …
(15) 1 1 1 1 ...
 Karnaugh Maps – 5 Variables (0)
a
0
b
0
c
0
d
0
e Y
0
(1)
0 0 0 0 1
The 2 K-maps are obtained from the (2)(3)2 0 0 0 1 0
0 0 0 1 1
3D parallel adjacent squares by (4)
0 0 1 0 0
(5)
0 0 1 0 1
1. translation of the blue square or (6)
0 0 1 1 0
cd e
2. rotation of the green square. (7)
(8)
0 0 1 1 1
ab 000 001 011 010 100 101 111 110 0 1 0 0 0
(9)
00 0 1 3 2 4 5 7 6 0 1 0 0 1
(10)
0 1 0 1 0
8 9 11 10 12 13 15 14 (11)
01 0 1 0 1 1
(12)
24 25 27 26 28 29 31 30 0 1 1 0 0
11 (13)
0 1 1 0 1
(14)
10 16 17 19 18 20 21 23 22 0 1 1 1 0
(15)
0 1 1 1 1
de 00 01 11 10 (16)
1 0 0 0 0
(17)
cd e 0 1 3 2 1 0 0 0 1
(18)
ab 000 001 011 010 100 101 111 110 1 0 0 1 0
(19)
6 7 5 4 8 9 11 10 1 0 0 1 1
00 0 1 3 2 c=0 (20)
1 0 1 0 0
01 8 9 11 10 14 15 13 12 24 25 27 26 (21)
1 0 1 0 1
(22)
1 0 1 1 0
11 24 25 27 26 30 31 29 28 16 17 19 18 (23)
1 0 1 1 1
(24)
10 16 17 19 18 22 23 21 20 1 1 0 0 0
(25)
1 1 0 0 1
(26)
de 00 01 11 10 1 1 0 1 0
(27)
ab 1 1 0 1 1
(28)
00 4 5 7 6 1 1 1 0 0
(29)
1 1 1 0 1
(30)
c=1 01 12 13 15 14 1 1 1 1 0
(31)
11 28 29 31 30 1 1 1 1 1

10 20 21 23 22 (logic) adjacent cells

 Karnaugh Maps – 6 Variables def
abc 100 101 111 110
100 36 37 39 38
def 101 44 45 47 46
abc 000 001
100 32 33 35 34 63 62
def 101 40 41 43 42 55 54
abc 100 001
000 4 5 7 6 59 58
def 001 12 13 15 14 51 50
abc 000 001
000 0 1 3 2 31 30

8 9 11 10 23 22
001 {0,4,32,36} = adjacent cells
011 24 25 27 26

010 16 17 19 18
def
abc 000 001 011 010 100 101 111 110
def
abc 000 001 011 010 100 101 111 110 000 0 1 3 2 4 5 7 6
100 32 33 35 34 36 37 39 38
8 9 11 10 12 13 15 14
001
def 40 41 43 42 44 45 47 46
abc 101 24 25 27 26 28 29 31 30
011
000 0 1 3 2 4 5 7 6 63 62
010 16 17 19 18 20 21 23 22
001 8 9 11 10 12 13 15 14 55 54
100 32 33 35 34 36 37 39 38
011 24 25 27 26 28 29 31 30
101 40 41 43 42 44 45 47 46
010 16 17 19 18 20 21 23 22
111 56 57 59 58 60 61 63 62

110 48 49 51 50 52 53 55 54

27
Logic Minimization

• Logic minimization aims to:

– reduce the number of gates (resulting from
reduction of the number of terms)
– reduce the number of inputs per gate (resulting
from fewer variables per term)
• Cost function: (proportional with) the number of gates
inputs
• Simplifying logic function => Logic circuit minimization
• The minimization will reduce cost, efficiency and power
consumption.
Logic Minimization

• Manual procedures:
1. Boolean Algebraic manipulation
2. Karnaugh maps (K-maps)
• Automatic procedures for:
a) Finding all Prime Implicants (PI)
b) Finding the minimum cover from the PI’s list
Logic Minimization - Algebraic manipulation
F = ABC + ABC + ABC + ABC
F = (ABC + ABC) + (ABC + ABC)
A B C
F = A(BC + BC) + A ( BC + BC)

F = AB( C + C) + AC ( B + B)
1 1
A.B
F
F = AB + AC
A.C

A A A Logic F
B Circuit
C F(A,B,C)
The Uniting Theorem

• Key tool for simplification: A (B' + B) = A

where A can be a product term of any other input
variables
• Essence of simplification:
– Find two element subsets of the ON-set where only
one variable changes its value – this single varying
variable can be eliminated and a single product term
used to represent both elements

A B F F = A'B'+AB' = (A'+A)B' = B'

0 0 1 B has the same value (0) in both on-set rows
=> B remains in the expression of the product term
0 1 0
1 0 1 A has different values in the two rows
=> A is eliminated
1 1 0
Implicants & Graphic Representation

• Given a logic function z = f(x0, x1, x2, …)

• Implicant = product term that, if equal to 1, implies f = 1
– whenever the implicant is 1=> f = 1
– f can be 1 other times, as well: it may be implied by other
implicants
– from the K-map point of view, an implicant is a rectangle
of 1, 2, 4, 8, … (any power of 2) 1’s of adjacent squares
• Prime Implicant (PI): the largest possible k-cube for
which f = 1
– cannot be totally covered by another implicant
 Implicants & Graphic Representation
F   2,3,5,7 
011 111
• Prime Implicants (PI): BC, AC, A’B
110
010 • Essential PI (EPI): PI that in the only
B 001
101
one to cover some true combination
C

100
– AC, A’B
000 A
• A minimum cover of a logic function
ABC AB has to contain all its essential prime
ABC
B implicants
• Theorem: The minimal SoP of a
0 1 3 2
0 0 1 1 BC
4 5 7 6 function is a sum of prime implicants
A 0 1 1 0 ABC B
C
AC 0 1 3 2 AB
ABC AC 0 0 1 1*
4 5 7 6
A 0 1* 1 0 BC
C

33
Logic Minimization using K-Maps

• To obtain the SoP of Fmin (the minimized F), one has to

find the minimum set of PI’s which covers F as follows:
1. Represent the given function F on a K-map
2. Find the PI set of the function F
3. Mark with * all K-map cells that contain a 1 which
is covered by only a single PI; each PI that contains
a * is an EPI. Include all EPI’s in the minimal set
which covers the function.
Logic Minimization using K-Maps

• To obtain the SoP of Fmin (the minimized F), one has to

find the minimum set of PI’s which covers F as follows:
4. Remove from the K-map the EPI’s and the 1’s they
cover, then apply step 3 onto the remaining 1’s and
PI’s, to find the secondary EPI’s.
5. Repeat step 4 until no higher order EPI’s are found.
Then find a minimum set from the rest of the non-
EPI prime implicants that cover the remaining 1's
on the map, then add them to the minimal set
which covers the function.
 Logic Minimization using K-Maps

• Looping a pair of adjacent 1s eliminates the variable

that appears in both direct and complemented form.

A B C F F   2,3,5,7   AC  AB
ABC 0 1
(0) 0 0 0 0 0 1
(1) 0 0 1 0 00 0 0
B 2 3
(2) 0 1 0 1 01 1 1
A BC 00 01 11 10
(3) 0 1 1 1 11
6 7
0 1
(4) 1 0 0 0 0 0 0 0 1 1 3 1*2 AB 4 5
(5) 1 0 1 1 10 0 1
0 4 1*5 17 06
1 BC
(6) 1 1 0 0
(7) 1 1 1 1 AC PI: AC, BC, A’B
C EPI: AC, A’B
 Logic Minimization using K-Maps
F   0,2,5,6,7,8,10,13,14,15 
 ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
A B C D F Looping a quad of adjacent 1s eliminates the two variables
(0) 0 0 0 0 1 that appears in both direct and complemented form.
(1) 0 0 0 1 0
CD 00 PI EPI* Non-
(2) 0 0 1 0 1 01 11 10
essential PI
(3) 0 0 1 1 0 AB BD
(4) 0 1 0 0 0 0 1 3 2
BD
00 1* 0 0 1
(5) 0 1 0 1 1 CD
(6) 0 1 1 0 1
4 5 7 6 BC
01 0 1* 1 1
(7) 0 1 1 1 1 12 13 15 14
11 0 1* 1 1
(8) 1 0 0 0 1 BD
(9) 1 0 0 1 0 10 8 9 11 10 BD CD
1* 0 0 1
(10) 1 0 1 0 1
(11) 1 0 1 1 0 BC
(12) 1 1 0 0 0
CD
(13) 1 1 0 1 1
F = BD + BD + or
(14) 1 1 1 0 1
BC
(15) 1 1 1 1 1
 SoP/NAND & PoS/NOR implementation
Remember
DeMorgan’s Theorem Equivalent Gate Symbols

A A.B A A+B
A.B =A+ B =
B B

A A+B A A. B
A+ B =A. B =
B B

SoP/NAND PoS/ NOR

 NAND gate implementation of SoP
F = A·B + A·C = A·B + A·C = (A·B) · (A·C)

A B C NAND gates are faster than ANDs

and ORs in most technologies
X=(X)
A B C

A F
A A
Incompletely Specified Logic Functions

• Don’t care Input combinations due to:

– Undefined situations
– Can't happen conditions
• Example: Binary coded decimal (BCD) input
combination
– Range 0..9
– Requires 4 bits: range 0..15
– 10..15 is don’t care!
 Incompletely Specified Logic Functions
• Example: Binary coded decimal (BCD) input
combination, output = input + 1
A B C D W X Y Z
(0)
0 0 0 0 0 0 0 1
(1)
0 0 0 1 0 0 1 0
(2)
0 0 1 0 0 0 1 1
(3)
0 0 1 1 0 1 0 0
(4)
(5)
0 1 0 0 0 1 0 1 off-set of W
0 1 0 1 0 1 1 0
(6)
(7)
0 1 1 0 0 1 1 1 on-set of W
0 1 1 1 1 0 0 0
(8)
1 0 0 0 1 0 0 1
(9)
1 0 0 1 0 0 0 0 don't care (DC) set of W
(10)
1 0 1 0 x x x x
(11)
1 0 1 1 x x x x
(12)
1 1 0 0 x x x x
(13)
1 1 0 1 x x x x
(14)
1 1 1 0 x x x x
(15)
1 1 1 1 x x x x
Incompletely Specified Logic Functions

• Don't care terms can be treated as 1’s or 0’s, depending on

which one is more advantageous.
• don't care should be included in the group if including a don't
care in the group makes
1. the group bigger, or
2. makes it possible to reduce the number of groups,
 Incompletely Specified Logic Functions
F   0,1,3,7,8,12  dc(5,10,13,14) dc -> x = don’t care terms
Don't care terms can be treated as 1’s or 0’s,
A B C D F depending on which one is more advantageous.
(0) 0 0 0 0 1 So, if including a don't care in a group makes
(1) 0 0 0 1 1 1. the group bigger, or
(2) 0 0 1 0 0 2. makes it possible to reduce the number of groups,
(3) 0 0 1 1 1 the don't care should be included in the group, but not otherwise!
(4) 0 1 0 0 0 CD 00 Secondary
(5) 0 1 0 1 x 01 11 10 PI EPI* EPI
AB
(6) 0 1 1 0 0 0 1 3 2

(7) 0 1 1 1 1 00 1 1 1* 0 AD
(8) 1 0 0 0 1 4 5 7 6 AD
01 0 x 1* 0 ABC
(9) 1 0 0 1 0 12 13 15 14
AD
(10) 1 0 1 0 x 11 1* x 0 x
(11) 1 0 1 1 0 8 9 11 10 ABC
10 1 0 0 x
(12) 1 1 0 0 1
AD BC D
(13) 1 1 0 1 x ABC BC D
(14) 1 1 1 0 x Fmin = AD + AD + or
(15) 1 1 1 1 0 BCD
 Incompletely Specified Logic Functions
A B C D F F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 CD 00
(0)
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
01 11 10
(1)
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AB
(2)
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 2
(3)
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 1 1 1* 0
(4)
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 7 6
(5)
0 1 0 1 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01 0 x 1* 0
(6)
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 13 15 14
(7)
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 1* x 0 x
(8)
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 9 11 10
(9)
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 1 0 0 x
(10)
1 0 1 0 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
(11)
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(12)
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ABC
(13)
1 1 0 1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 F13min = AD + AD + or
(14)
1 1 1 0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
(15)
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BCD
ABC
F13 = A ⊕ D + or
BCD
A’ D’
B’ B’
C’ C’
A A
D D
 Combinational Circuits

• A combinational circuit is a setup of a number of

connected logic gates implementing the logic function
between n input variables and m output variables.
• In a combinational circuit, the output is time-
independent and does only depend on the circuit's input
• In a combinational circuit, the output is “re-computed"
as soon as a change in the input occurs, and it is
presented to the output with a delay

x0 z = F(x0, x1, x2, …) | z {0, 1}, xk {0, 1}, k = 0,1,2,…

x1 Logic z
x2 Circuit F can be represented by: logic expression, truth
x3 table, K-map
Combinational Circuits Design

1. Define the problem

2. Assign different letter symbols to the input and
output variables
3. Derive the truth table defining the relationship
between the inputs and the outputs
4. Obtain the simplified Boolean expression for each
output variable
5. Draw the circuit's logic diagram
Combinational Circuits Design

• Half Adder: Adds two 1-bit numbers A & B, output sum

S and Carry Cout

Cout
A B Cout S A HA
0 0 0 0 B S
0 1 0 1
1 0 0 1 Cout
1 1 1 0 HA
A S
S=A⊕B B
Cout = (A · B)
Shannon identified the bit as a fundamental unit of information and,
coincidentally, the basic unit of computation.
 Combinational Circuits Design

• Full Adder: Adds two 1-bit numbers A & B, takes 1 bit

carry from previous stage Cin; output sum S and Carry
Cout
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
Equations are modified as follows: 0 1 1 1 0
Cout = ((A ⊕ B) · CIN) + (A · B) 1 0 0 0 1
S = A ⊕ B ⊕ CIN 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 Combinational Circuits Design

• Full Adder: Adds two 1-bit numbers A & B, takes 1 bit

carry from previous stage Cin; output sum S and Carry
Cout

Equations are modified as follows:

Cout = ((A ⊕ B) · CIN) + (A · B)
S = A ⊕ B ⊕ CIN
Sequential Circuits

• The output of sequential circuits is logic function of the

present state of external inputs, but also on the state of
these inputs in past. Therefore, they are also referred to
as circuits with memory.
• The sequential circuits are formed by additional
feedback signals, looped backward from the output to
the input of the circuit (referred to as signals of internal
state of the circuit).
– By this backward loop, the dependence on previous
values of inputs is implemented as dependence on
the current internal state of the machine.
 Sequential Circuits

• The sequential switching circuits are classified in:

• Synchronous sequential circuits =

• Asynchronous sequential circuits = any outputs may change at time events
(asynchronously) change of an input may defined by a periodical control signal
trigger an output change (pulse) called clock.
Inputs Combinational Inputs Combinational
Outputs Outputs
Circuits Feedback
Circuits

Delay Memory
line
Clock