SEQUENTIAL CIRCUITS

Sub-topic
Outline

• Classical Automata
• Flip-flops
• Latches
• Sequential Circuit Design
Sequential Circuits

• The output of sequential circuits is logic function of the

present state of external inputs, but also on the state of
these inputs in past. Therefore, they are also referred to
as circuits with memory.
• The sequential circuits are formed by additional
feedback signals, looped backward from the output to
the input of the circuit (referred to as signals of internal
state of the circuit).
– By this backward loop, the dependence on previous
values of inputs is implemented as dependence on
the current internal state of the machine.
 Sequential Circuits

• The sequential switching circuits are classified in:

• Synchronous sequential circuits =

• Asynchronous sequential circuits = any outputs may change at time events
(asynchronously) change of an input may defined by a periodical control signal
trigger an output change (pulse) called clock.
Inputs Combinational Inputs Combinational
Outputs Outputs
Circuits Feedback
Circuits

Delay Memory
line
Clock
 Classical Automata
Finite State Machines (FSMs)

input X
(clock) Internal state S output Z

Next state S+ computed by function 

Output Z computed by function 
Transition Function
• Moore-automata:
Z =  (S); S+ =  (X, S)
• Mealy-automata
Z =  (X, S); S+ =  (X, S)

Output Function
Classical Automata

• A state diagram is a directed graph connecting all the

possible states of the sequential circuits, where each
transition has the following form:

Example
- X = {e} S0 e=1 S1
- Z = {0,1,2,3} 0 1
- S = {S0,S1,S2,S3} e=1
-Initial state = S0 e=1
State Diagram:
S3 S2
3 e=1 2
Sequential Circuits as FSM

• Input set: X={Xi |i=0,m-1} X= {X0,X1,X2,…, Xm-1}

• Output set: Z={zj | j=0,p-1} Z = {Z0,Z1,Z2,…, Zp-1}
• States: S = {Sk | k=0,q-1} S={S0,S1,S2,…, Sq-1}

Present State S(t)

S(t)
S(t+Δt)
S(t+Δt)=δ(S(t),X(t)) Next Memory
State S(t)
Combinational
X(t)
Circuits Z(t)
Z(t) = λ(S(t),X(t))
Latches & Flip-Flops

• A flip-flop or a latch holds (stores) 1 "bit".

• "Bit" ::= "binary digit.“

S
Q
Q
S Q
Q
R
R

t SR S R Qt+Δt Qt+Δt
311 0 0 0 0
210 0 1 1 0 Set
101 Reset
1 0 0 1
000 1 1 Q Qt
t Hold
 S-R Latch

• Elementary memory elements

(Set-Reset) Truth table of Q(t+Δ)
S
Q
reset set
S
S
0 1 0 2 0 t SR
00 01 11 10
Q (t )
R 0 0 0 X 1
R Q Q t  t  S t  Q t  R t
1 1 0 X 1 condition : S t  R t  0

t SR S R Qt+Δt Qt+Δt R

311 0 0 1 1 Weird!!
210 0 1 1 0 Set
Reset
101
000
1
1
0
1
0
Q Qt
t
1
Hold Preserve Q
a.k.a. Hold Q
 S-R Latch

• Elementary memory elements

(Set-Reset)
Q S= 0
Q =1
S S =0 Q =1
S
0 1 0 2 0 t
3 SET
1
R
R Q Q =1
R= 0
Q =0
t SR R= 1
S R Qt+Δt Qt+Δt
311 S =1 Q= 0
0 0 1 1 Weird!!
210 0 1 1 0 Set Q =1
101 1 0 0 1 Reset S =1
Hold RESET
000 1 1 Q Qt
t
2
HOLD
0
Q =1
R= 0
Q =0
R= 1
 S-R Latch
S Q
BLOCK
DIAGRAM
STATE TABLE R
Present Next State Qt+Δt
CHARACTERISTIC or EXCITATION
State SR
FUNCTIONAL TABLE TABLE
Qt 00 01 10 11
0 0 0 1 - St Rt Qt Qt+Δt Qt+Δt St Rt Qt+Δt Function Qt Qt+Δt St Rt
1 1 0 1 - 0 0 0 0 1 0 0 Qt Hold 0 0 0 x
0 0 1 1 0 0 1 0 Reset 0 1 1 0
0 1 0 0 1 1 0 1 Set 1 0 0 1
S Q 0 1 1 0 1 Indeterminate
/ Forbidden
1 1 0? (non-sense) 1 1 x 0
1 0 0 1 0
Q
R 1 0 1 1 0 Characteristic Q t  t  S t  Q t  R t
LOGIC 1 1 0 0? 0? Equation: condition : S t  R t  0
DIAGRAM 1 1 1 0? 0?

SR=00v01 SR=10 00v10

STATE DIAGRAM 0 1
01
JK Flip-Flop

• The basic S-R NAND flip-flop circuit has many

advantages and uses in sequential logic circuits but it
suffers from two basic switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0)
must always be avoided
2. if Set or Reset change state while the enable (EN)
input is high the correct latching action may not
occur (i.e. not gated with a clock)
• To overcome these two fundamental design problems
with the SR flip-flop design, the JK flip Flop was
developed
– Invented by: Jack Kilby
 JK Flip-Flop

JK=00v01 10v11 00v10

0 1 CHARACTERISTIC or
FUNCTIONAL TABLE EXCITATION TABLE
01v11
Jn Kn Qn+1 Function Qn Qn+1 Jn Kn
0 0 Qn Hold 0 0 0 x
0 1 0 Reset 0 1 1 x
1 0 1 Set 1 0 x 1
1 1 Qn Toggle 1 1 x 0
CHARACTERISTIC EQUATION:
n 1 MEV representation
Q  Q J Q K
n n n n
(Map-Entered Variable)
 Clock Pulse
IEEE Std 181™-2011 - “IEEE Standard for Transitions, Pulses, and Related
Waveforms,” IEEE Instrumentation and Measurement Society
• negative-going transition: terminating state is more negative than its originating state.
• positive-going transition: terminating state is more positive than its originating state.
• transition duration: the difference between the two reference level instants of the same
transition. Unless otherwise specified, they are the 10% and 90% of the reference levels.
 Clock Pulse

90%

10%
 D-Latch
Enable D S R Q Q
0 0 1 1 Q Q
0 1 1 1 Q Q
1 0 1 0 0 1
1 1 0 1 1 0

S
D
Q

Q
δ R
Enable
 D-Latch
Enable D S R Q Q
0 0 1 1 Q Q
0 1 1 1 Q Q
1 0 1 0 0 1
1 1 0 1 1 0

1
Enable
0
1
D 0
1
S 0
1
R 0
Hold 1
Q 0

“Hold”state “Transparent” state “Hold”state

Master-Slave D Flop-Flop

Latch 1 Latch 2

D1
D D Q D Q Q
Master Slave
Enab. Enab. Q

CLK
EN1 EN2
 Master-Slave D Flop-Flop Latch 1

D1
Latch 2

D D
Master
Q D
Slave
Q Q
Enab. Enab. Q
CLK EN1 EN2
1
D Din* Input data D may change
0
1
CLK 0
1
EN1 Latch 1 is Latch 1 is Holding Latch 1 is Transparent
Transparent 0
1
D1 D1 = Din* Changed input data D enter Latch 1
0
1
EN2 Latch 2 is Holding Latch 2 is Transparent Latch 2 is Holding
0
1
Q Q = D1 = Din* 0
The state of the flip-flop’s output Q copies input Positive-Edge-Triggered
D when the positive edge of the clock CLK occurs D Flip-Flop
 Master-Slave D Flop-Flop

D=1
Dn Qn Qn+1 Qn Qn+1 Dn
D Q
0 0 1 1 0 0 0 0 0 0
CLK
0 Q 0 1 0 0 1 1
STATE DIAGRAM
1 0 1 1 0 0
BLOCK
DIAGRAM 1 1 1 1 1 1
TIME Qn+1 = Dn Dn = Qn+1
DIAGRAM Setup Hold There
the
is a timing "window" around the clocking moment during which
input must remain stable and unchanged in order to be recognized.
time time
D Din* Input data D may change

1
CLK 0
Propagation
time 1
Q Q = Din*
0
 T Flip-Flop

Positive-Edge -Triggered
T Flip-Flop (rising edge)

T Q

CLK
Q

0 T=1 0
0 1
T=1
 T Flip-Flop

T Q
Tn Qn Qn+1 Qn Qn+1 Tn
CLK
0 0 0 0 0 0
Q
0 1 1 0 1 1
1 0 1 1 0 1
0 T=1 0 1 1 0 1 1 0
0 1
T=1 Q n1  Q n  T  Q n  T
Sequential Circuits

• Sequential circuits is based on combinational circuits

connected to a vector of flip-flops – (memory elements)
• Combinational circuits is used for:
1. Generating the circuit’s desired output – based on
the current state of flip-flops and current input
2. Generating the next state based on the current
state and current input
Zn = λ(Sn,Xn)

Sn+1 = δ(Sn,Xn)
Sequential Circuits

• For a sequential circuit with m flip-flops, p input

variables, and q output variables, the state table
consists of:
• m columns for the FF present states (Sn) S ={Si, i = 0,…, m-1}
• p columns for the circuit’s inputs X = {Xj, j = 0, 1, …, p-1}
• m columns representing the flip-flops’ next states
Sin 1   ( S n , X n ), i  0...m  1
• q columns representing the circuit’s outputs (Z)
Z kn   ( S n , X n ), k  0...q  1

Present Next Outputs

State Inputs State δ λ
Sm-1

Sm-1
xp-1

… … … …

zq-1
S0

S0
x0

z0
Synchronous Sequential Circuits as FSM

• The behavior of sequential circuits can be described

using the Finite State Machine (FSM) model
 Synchronous Sequential Circuits as FSM

• The behavior of sequential circuits can be described

using the Finite State Machine (FSM) model

Mealy FSM Output based on present state and present input:

Zn = λ(Sn,Xn)
m

Register
Next state s(n)

State
x(n) δ m
z(n)
p present
s(n+1) λ
state q
Present input
clk
 Synchronous Sequential Circuits as FSM

• The behavior of sequential circuits can be described

using the Finite State Machine (FSM) model

Moore FSM Output based on present state only:

m Zn = λ(Sn)

Register
Next state s(n) z(n)

State
x(n) δ λ
p m present q
s(n+1)
Present input state
clk
 Sequential Circuits Analysis

• Q: Find the Transition Function of a D-Latch

SR characteristics
2
0. Being given the logic diagram
of sequential circuit: Enable D S R Qt+Δt Qt+Δt S R Qt+Δt Qt+Δt
0 0 1 1 Qt Qt 0 0 1 1
D S S Q
0 1 1 1 Qt Qt 0 1 1 0
R Q 1 0 0 1
R 1 0 1 0 0 1
1 1 1 0 1 1 0 1 1 Qt Qt
Enable CC outputs:
S=D.Enable
R=D.Enable 3
Enable D Qt+Δt Qt+Δt
ANALYSIS = 0 x Qt Qt
from circuit to transition table
= find Q(t+Δt) = δ(D(t),Q(t)) 1 0 0 1
1 1 1 0
Sequential Circuits Analysis

1. From circuit to state diagram

– A(n+1) = δA(x(n),A(n),B(n))
– B(n+1) = δB(x(n),A(n),B(n)) State Register
– y(n) = λ(x(n),A(n),B(n))
2. Find the output of comb
Circuits
– DA = xA + xB
δ
– DB = xA’
– y = x’A + x’B

Logic Diagram
Sequential Circuits Analysis

2. Find the output of comb

Circuits
– DA = xA + xB State Register
– DB = xA’
– y = x’A + x’B = x’(A+B)
Present State In Next State Out
A B x A+ B+ y δ
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0 λ
1 1 0 0 0 1
1 1 1 1 0 0
Logic Diagram
Sequential Circuits Analysis

3. Use characteristic equation of D-Flop-Flop

– DA = A+ = xA + xB
State Register
– DB = B+ = xA’
Present State In Next State Out
A B x A+ B+ y
0 0 0 0 0 0
0 0 1 0 1 0
δ
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
λ

Logic Diagram
Sequential Circuits Analysis

3. Derive state diagram

– Nodes are states AB
– Transitions tagged by
Input/output Present State In Next State Out
A B x A+ B+ y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Sequential Circuits Design

1. From the problem specification, create the state

diagram which shows all of the states that the FSM
can be in, and how to switch from one state to another
2. State Table - transition (δ) and output (λ) functions
Make a state table based on the problem specification or
state diagram. It may show the next states Sn+1 and
outputs Zn as functions of present states Sn and inputs Xn
Transition function: Sn+1 = δ(Sn,Xn), output function Zn = λ(Sn,Xn).
State minimization = reduce the number of states in
the table (not in CEG2136)
Sequential Circuits Design

3. State Assignment (Encoding). Assign binary codes to

the states in the state table, if they were not assigned
already. If you have N states, your binary codes will
have at least log2 N digits, and your circuit will have
at least log2 N flip-flops  Transition table (i.e.,
binary-coded state table) = a state table with encoded
states.
4. Excitation Table and Equations. Choose the type of
flip-flops to be used. For each flip-flop and each row of
your transition table, find the flip-flop input values that
are needed to generate the next state from the present
state. You may use flip-flop excitation tables.
Sequential Circuits Design

5. Find simplified equations for the flip-flops inputs &

the circuit outputs Z.
6. Build the circuit!
Sequential Circuits Design Example

• Design a D-Latch using SR-latch

1. Problem Specs

D S Q Given: D-Latch
En D Qt+Δt
δ State Diagram
Enable
R 0 x Qt or Characteristic
1 0 0 Table
1 1 1

2. State Diagram, 3. State Assignment

En=0 D.En=01 En=0
0 1
D.En=01
 Sequential Circuits Design Example
4. Excitation Table

D-Latch Specs
En D Qt+Δt
SR Excitation Table

Qt Qt+Δt St Rt 0 x Qt
respects SR=0

0 0 0 x 1 0 0
1 1 1
0 1 1 0
State table of Sequential
1 0 0 1 Circuit to be Designed

1 1 x 0
En D Qt Qt+Δt S R
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 1 x 0
1 0 0 0 0 x
1 0 1 0 0 1
1 1 0 1 1 0
1 1 1 1 x 0
Excitation table for
Sequential Circuit to be Designed
Sequential Circuits Design Example
5. Find simplified equations

S En D Qt Qt+Δt S R
En DQt 00 01 11 10 0 0 0 0 0 x
0 0 1 1 x 0
0 0 0 x1 x3 0 2
0 1 0 0 0 x
1 0 4 0 5 x7 1 6 0 1 1 1 x 0

En.D 1 0 0 0 0 x
R
1 0 1 0 0 1
En DQt 00 01 11 10
1 1 0 1 1 0
0 x 0 0 1 0 3 x2 1 1 1 1 x 0

1 x4 1 5 0 7 06
En.D
Sequential Circuits Design Example
6. Build the circuit
D S Q
S = En.D
R = En.D
Enable R

S = En.D
R = En.D

D Q
S

En Q
R
39
Sequential Circuits Design Example2

• Design a JK-FF using SR-latch

1. Problem Specs Qn Qn+1 Jn Kn
J
0 0 0 x
S Q
Comb. 0 1 1 x
Circuits
K 1 0 x 1
R
1 1 x 0

2. State Diagram, 3. State Assignment

JK=00v01 10v11 00v10
0 1
01v11
 Sequential Circuits Design Example2
4. Excitation Table
Qn Qn+1 Jn Kn

JK-FF Specs
SR Excitation Table

Qt Qt+Δt St Rt 0 0 0 x
respects SR=0

0 0 0 x
0 1 1 x
0 1 1 0
1 0 0 1
1 0 x 1
1 1 x 0 1 1 x 0
J K Qt Qt+Δt S R
0 0 0 0 0 x
0 0 1 1 x 0
0 1 0 0 0 x
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 x 0
1 1 0 1 1 0
1 1 1 0 0 1
Excitation table for
Sequential Circuit to be Designed
Sequential Circuits Design Example2
5. Find simplified equations

J KQt 00 01 11 10 J K Qt Qt+Δt S R
0 0 0 0 0 x
S= JQ’ 0 0 0 x 1 0 3 0*2
0 0 1 1 x 0
1 14 x 5 07 1 6
0 1 0 0 0 x
J KQt 00 01 11 10 0 1 1 0 0 1
R= KQ
1 0 0 1 1 0
0 x 0 0 1 13 x 2
1 0 1 1 x 0
1 0 4 0*5 17 0 6 1 1 0 1 1 0
1 1 1 0 0 1
Sequential Circuits Design Example2
6. Build the circuit

S= JQ’

R= KQ
Sequential Circuits Design Example3

• Apply the Sequential Circuit Design Procedure to

derive the logic diagram of a logic circuit which
implements the following FSM
1.
2. State Diagram, 3. State Assignment
x=0

00
NOTE:
x=0 The states are
01 11
already encoded,
so the Transition Table
will be derived directly from
10 the state diagram. Hence, after Step 1
will go directly to Step 3.
x=0
Sequential Circuits Design Example3
4. Excitation Table
Present Next State
State Sn In Sn+1
x=0
A B x A+ B+
00 0 0 0 0 0
0 0 1
x=0
01 11 0 1 0
0 1 1
1 0 0
10
1 0 1
x=0 1 1 0
1 1 1
Sequential Circuits Design Example3
4. Excitation Table
Present Next State
State Sn In Sn+1
x=0
A B x A+ B+
00
00 0 0 0 0 0
0 0 1
x=0
01 11 0 1 0
0 1 1
1 0 0
10
1 0 1
x=0 1 1 0
1 1 1
Sequential Circuits Design Example3
4. Excitation Table
Present Next State
State Sn In Sn+1
x=0
A B x A+ B+
00
00 0 0 0 0 0
0 0 1 0 1
x=0
01 11 0 1 0
0 1 1
1 0 0
10
1 0 1
x=0 1 1 0
1 1 1
Sequential Circuits Design Example3
4. Excitation Table
Present Next State
State Sn In Sn+1
x=0
A B x A+ B+
00
00 0 0 0 0 0
0 0 1 0 1
x=0
01 11 0 1 0 0 0
0 1 1 1 0
1 0 0 1 0
10
1 0 1 1 1
x=0 1 1 0 1 1
1 1 1 0 0
 Sequential Circuits Design Example3
4. Excitation Table – using 2 JK-FF

Present Next State Next State control gates’ out

State Sn In Sn+1 = Flip-flops’ Inputs
Next State State Register A B x A+ B+ JA KA JB KB
JA
J Q A
Excitation
Equations 0 0 0 0 0 0 X
Sn KB
clk
K 0 0 1 0 1 0 X
JB B 0 1 0 0 0 0 X
J Q
Combinational Clk 0 1 1 1 0 1 X
Circuits KB
K
1 0 0 1 0 X 0
1 0 1 1 1 X 0
x Clk 1 1 0 1 1 X 0
1 1 1 0 0 X 1
 Sequential Circuits Design Example3
4. Excitation Table – using 2 JK-FF

Present Next State Next State control gates’ out

State Sn In Sn+1 = Flip-flops’ Inputs
Next State State Register A B x A+ B+ JA KA JB KB
JA
J Q A
Excitation
Equations 0 0 0 0 0 0 X 0 X
Sn KB
clk
K 0 0 1 0 1 0 X 1 X
JB B 0 1 0 0 0 0 X X 1
J Q
Combinational Clk 0 1 1 1 0 1 X X 1
Circuits KB
K
1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
x Clk 1 1 0 1 1 X 0 X 0
1 1 1 0 0 X 1 X 1
 Sequential Circuits Design Example3
5. Find simplified equations
JA Bx
B KA Bx
B
00 01 11 10 00 01 11 10
A A
0 0 0 01 1 3 0 2 0 x 0 x1 x3 x2
4 5 7 6 4 5 7 6
1 x x x x 1 0 0 1 0
x x
JA = Bx KA = Bx
Bx
A
00 01 11 10 KB Bx
B
00 01 11 10
0 00 11 x3 x2 A
4 5 7 6
1 0 1 x x 0 x 0 x1 1 3 1 2
4 5 7 6

JB = x x 1 x x 1 0
x

KB = x+A’
Sequential Circuits Design Example3
6. Build the circuit

JA = Bx
KA = Bx x
A
JB = x JA =KA

KB = x+A’

JB B

KB
A’
Sequential Circuits Design Example4

• Design a 4 bit counter Qn Qn+1 Jn Kn

1. Use 4 JK-FF for 4 bit output 0 0 0 x
0 1 1 x
Next State
1 0 x 1
J Q
Excitation 1 1 x 0
clk
Equations
Sn Combinational K
Circuits State
Register

Clk
 Present state Sn Next state Sn +1
Example4 Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
• Design a 4 bit counter 0 0 1 0 0 0 1 1
2. State Diagram, 0 0 1 1 0 0 0 1
3. State Assignment 0 1 0 0 x x x x
0 1 0 1 x x x x
0 1 1 0 0 0 1 0
State Diagram
0 1 1 1 x x x x
1 0 0 0 1 1 0 0
Reset 0000 1000 1100 1101 1 0 0 1 x x x x
1 0 1 0 x x x x
0001 1111
1 0 1 1 x x x x

0011 0010 0110 1110 1 1 0 0 1 1 0 1

1 1 0 1 1 1 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 1 1 0
 Present state Sn Next state Sn +1 Q3 input Q2 input Q1 input Q0 input
Q3 Q2 Q1 Q0 Q3+ Q2+ Q1+ Q0+ J3 K3 J2 K2 J1 K1 J0 K0
C
0 0 0 0 1 0 0 0 1 x 0 x 0 x 0 x
o 0 0 0 1 0 0 0 0 0 x 0 x 0 x x 1
u 0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
n 0 0 1 1 0 0 0 1 0 x 0 x x 1 x 0
t 0 1 0 0 x x x x x x x x x x x x
e 0 1 0 1 x x x x x x x x x x x x
r 0 1 1 0 0 0 1 0 0 x x 1 x 0 0 x
0 1 1 1 x x x x x x x x x x x x

D 1 0 0 0 1 1 0 0 x 0 1 x 0 x 0 x
1 0 0 1 x x x x x x x x x x x x
e
1 0 1 0 x x x x x x x x x x x x
s
1 0 1 1 x x x x x x x x x x x x
i
1 1 0 0 1 1 0 1 x 0 x 0 0 x 1 x
g 1 1 0 1 1 1 1 1 x 0 x 0 1 x x 0
n 1 1 1 0 0 1 1 0 x 1 x 0 x 0 0 x
55 1 1 1 1 1 1 1 0 x 0 x 0 x 0 x 1
 Sequential Circuits Design Example4

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10

Q3Q2 Q3Q2 Q3Q2 Q3Q2
00 1 0 0 0 00 x x x x 00 0 0 0 0 00 x x x x
01 x x x 01 x x x x 01 x x x x 01 x x x 1
11 x x x x 11 0 0 0 1 11 x x x x 11 0 0 0 0
10 x x x x 10 0 x x x 10 1 x x x 10 x x x x
J 3  Q1  Q0 K 3  Q1  Q0 J 2  Q3 K 2  Q3

Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10 Q1Q0 00 01 11 10

Q3Q2 Q3Q2 Q3Q2 Q3Q2
00 0 0 x x 00 x x 1 0 00 0 x x 1 00 x 1 0 x
01 x x x x 01 x x x 0 01 x x x 0 01 x x x x
11 0 1 x x 11 x x 0 0 11 1 x x 0 11 x 0 1 x
10 0 x x x 10 x x x x 10 0 x x x 10 x x x x

J 1  Q3  Q0 K1  Q3  Q0 J 0  Q2  Q1 K 0  Q3  Q1
Sequential Circuits Desi Example4

J 3  Q1  Q0
K 3  Q1  Q0

J 2  Q3
K 2  Q3

J 1  Q3  Q0
K1  Q3  Q0

J 0  Q2  Q1
K 0  Q3  Q1