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Vlsi Design Flow: RTL To GDS: Prof. Sneh Saurabh

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954 views2 pages

Vlsi Design Flow: RTL To GDS: Prof. Sneh Saurabh

Uploaded by

Sunil Kumar
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VLSI DESIGN FLOW: RTL TO GDS

PROF. SNEH SAURABH


Department of Electronics and Communications Engineering
IIIT Delhi

PRE-REQUISITES : Basic Course on Digital Circuits (typically taught in the first/second year of UG Program)
INDUSTRY SUPPORT : The course develops skills to use design automation tools for chip designing. The course will be
valued by companies working on semiconductors, such as Qualcomm, Intel, Texas Instruments,
NXP, ST Microelectronics, Micron, IBM, Cadence, Synopsys, Siemens, ARM, AMD, NVidia, Apple, and
Google.

COURSE OUTLINE :

This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design,
and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the
help of activities and demonstrations on freely available CAD tools. This course will enhance the employability of the students and will
make them ready to undertake careers in the semiconductor industry.

ABOUT INSTRUCTOR :

Prof.Sneh Saurabh obtained his Ph.D. from IIT Delhi in 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000. He has rich
experience in the semiconductor industry, having spent 16 years working for industry leaders such as Cadence Design Systems,
Synopsys India, and Magma Design Automation before joining IIIT Delhi in June 2016. He has been involved in developing some of the
well-established industry-standard EDA tools for clock synchronization, constraints management, STA, formal verification, and physical
design. He has taught VLSI-specific courses for over six years at IIIT Delhi, the most popular being VLSI Design Flow. His teaching has
been rated excellent by students consistently, and he has received the Teaching Excellence award for seven consecutive semesters,
three times for the course VLSI Design Flow. He holds three US patents and is the co-author of the book "Fundamentals of Tunnel Field-
Effect Transistors." He is an Editor (IETE Technical Review), an Associate Editor (IEEE Access), a Review Editor (Frontiers in Electronics
Integrated Circuits and VLSI), and a Senior Member of IEEE.

COURSE PLAN :
Week 1: Basic Concepts of Integrated Circuit: Structure, Fabrication, Types, Design Styles, Designing vs. Fabrication, Economics,
Figures of Merit Overview of VLSI Design Flow: Design Flows and Abstraction; Pre-RTL Methodologies: Hardware-software Partitioning,
SoC Design, Intellectual Property (IP) Assembly, Behavioral Synthesis

Week 2: Overview of VLSI Design Flow: RTL to GDS Implementation: Logic Synthesis, Physical Design; Verification and Testing; Post-
GDS Processes

Week 3: Hardware Modeling: Introduction to Verilog Functional verification using simulation: testbench, coverage, mechanism of
simulation in Verilog

Week 4: RTL Synthesis: Verilog Constructs to Hardware Logic Optimization: Definitions, Two-level logic optimization

Week 5: Logic Optimization: Multi-level logic optimization, FSM Optimization Formal Verification: Introduction, Formal Engines: BDD,
SAT Solver

Week 6: Formal Verification: Model Checking, Combinational Equivalence Checking Technology Library: Delay models of
Combinational and Sequential Cells

Week 7: Static Timing Analysis: Synchronous Behavior, Timing Requirements, Timing Graph, Mechanism, Delay Calculation, Graph-
based Analysis, Path-based Analysis, Accounting for Variations
Week 8: Constraints: Clock, I/O, Timing Exceptions Technology Mapping Timing-driven Optimizations

Week 9: Power Analysis, Power-driven Optimizations Design for Test: Basics and Fault Models, Scan Design
Methodology

Week 10: Design for Test: ATPG, BIST Basic Concepts for Physical Design: IC Fabrication, FEOL, BEOL, Interconnects
and Parasitics, Signal Integrity, Antenna Effect, LEF files

Week 11: Chip Planning: Partitioning, Floorplanning, Power Planning Placement: Global Placement, Wirelength
Estimates, Legalization, Detailed Placement, Timing-driven Placement, Scan Cell Reordering, Spare Cell Placement

Week 12: Clock Tree Synthesis: Terminologies, Clock Distribution Networks, Clock Network Architectures, Useful
Skews Routing: Global and Detailed, Optimizations Physical Verification: Extraction, LVS, ERC, DRC, ECO and Sign-off

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