VERILOG

Fundamentals of Verilog

Comments:
Comments can be inserted in the code for readability and documentation.Comments
are text added to the model for purposes of documentation. They are ignored by the
simulator that implements the model.
There are two ways to write comments:
- A single-line comment starts with `//`. Verilog skips from that point to the end of the
line.
- A multiple-line comment starts with `/*` and ends with `*/`. Multiple-line comments
cannot be nested.
Examples:
a = b && c; // This is a single-line comment
/* This is a multiple-line comment */
/* This is /* an illegal */ comment */

Number Specification
Numbers can also be represented in binary, octal and hexadecimal. By default,
Verilog simulators treat numbers as decimals.

There are two types of number specification in Verilog: sized and unsized.
Sized numbers
Sized numbers are represented as [size]'[base_format][number]
Examples:
3'b010; // size is 3, base format is binary ('b), and the number is 010 (indicates
value 2 in binary)
3'd2; // size is 3, base format is decimal ('d) and the number is 2 (specified in
decimals)
9'h1FA; // size is 9, base format is hexadecimal ('h) and the number is 0x1FA (in
hex) to represent decimal 506
32'hFACE_47B2; // Underscore (_) can be used to separate 16 bit numbers for
readability

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Uppercase letters are legal for number specification when the base format is
hexadecimal.
16'hcafe; // lowercase letters Valid
16'hCAFE; // uppercase letters Valid
32'h1D40_CAFE; // underscore can be used as separator between 4 letters Valid

Unsized number
Numbers specified without a `<base format>` specification are decimal by default.
Numbers written without a `<size>` specification have a default number of bits that is
simulator- and machine-specific (must be at least 32).
Examples:
23456; // This is a 32-bit decimal number by default
'hc3; // This is a 32-bit hexadecimal number
'o21; // This is a 32-bit octal number

X or Z values
Verilog has two symbols for unknown and high impedance values. An unknown value
is denoted by an `X`. A high impedance value is denoted by `z`.
Examples:
12'h13x; // This is a 12-bit hex number; 4 least significant bits unknown
6'hx; // This is a 6-bit hex number
32'bz; // This is a 32-bit high impedance number

Negative numbers
Negative numbers can be specified by putting a minus sign before the size for a
constant number. Size constants are always positive. It is illegal to have a minus sign
between `<base format>` and `<number>`.
Examples:
-6'd3; // 8-bit negative number stored as 2's complement of 3
4'd-2; // Illegal specification

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Whitespace
White space is a term used to represent the characters for spaces, tabs, newlines and
formfeeds, and is usually ignored by Verilog except when it separates tokens. In fact,
this helps in the indentation of code to make it easier to read.
Blank spaces (`\b`), tabs (`\t`), and newlines (`\n`) comprise the whitespace.
Whitespace is not ignored in strings.

Operators
There are three types of operators: unary, binary, and ternary or conditional.
• Unary operators shall appear to the left of their operand
• Binary operators shall appear between their operands
• Conditional operators have two separate operators that separate three operands
Examples:
a = -b; // - is a unary operator, b is the operand
a = b && c; // && is a binary operator, b and c are operands
a = b ? c : d; // ?: is a ternary operator, b, c, and d are operands

Strings
A string is a sequence of characters that are enclosed by double quotes. The
restriction on a string is that it must be contained on a single line.
Examples:
"Hello Verilog World"; // is a string

Identifiers and Keywords

Keywords are special identifiers reserved to define the language constructs.
Keywords are in lowercase. Identifiers are names given to objects so that they can be
referenced in the design. Identifiers are made up of alphanumeric characters, the
underscore (`_`) and the dollar sign (`$`) and are case-sensitive.
Examples:
reg value; // reg is a keyword; value is an identifier
input clk; // input is a keyword, clk is an identifier

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DATA TYPES
Value Set
Verilog supports four values and eight strengths to model the functionality of real
hardware.

Value Level - Condition in Hardware Circuits

0 - Logic zero, false condition
1 - Logic one, true condition
X - Unknown value
z - High impedance, floating state

Strength levels are particularly useful for accurate modeling of signal contention,
MOS devices, dynamic MOS, and other low-level devices. Only `trireg` nets can
have storage strengths `large`, `medium`, and `small`.

Nets
Nets are used to connect between hardware entities like logic gates and hence do not
store any value on its own.Just as in real circuits, nets have values continuously
driven on them by the outputs of devices that they are connected to.
Examples:
wire a; // Declare net a
wire b, c; // Declare two wires b, c
wire d = 1'b0; // Net d is fixed to logic value 0 at declaration

Registers
Verilog data-type reg can be used to model hardware registers since it can hold values
between assignments.Registers retain value until another value is placed onto them.
Examples:
reg reset; // Declare a variable reset
initial begin
reset = 1'b1; // Initialize reset to 1
#100 reset = 1'b0; // After 100 time units reset is deasserted
end

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Vectors
Verilog needs to represent individual bits as well as groups of bits(multiple bit
widths).Verilog has scalar and vector nets and variables.
Nets or `reg` data types can be declared as vectors(multiple bit widths).
Examples:
wire o_nor; // single bit scalar net
wire [7:0] o_flop; // 8-bit vector net
wire [7:0] bus; // 8-bit bus
reg parity; // single bit scalar variable
reg [31:0] addr;

Integer, Real, and Time Register Data Types

Integer
An integer is a general-purpose register data type used for manipulating quantities.
Integers store values as signed quantities.
Examples:
integer counter; // General purpose variable used as a counter
initial counter = -1; // A negative one is stored in the counter

Real
Real number constants and real register data types are declared with the keyword
`real`.
Examples:
real delta; // Define a real variable called delta
initial begin
delta = 4e10; // Delta is assigned in scientific notation
delta = 2.13; // Delta is assigned a value 2.13
end

Time
A special `time` register data type is used in Verilog to store simulation time.
Examples:
time save_sim_time; // Define a time variable save_sim_time
initial save_sim_time = $time; // Save the current simulation time
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Arrays
Arrays are allowed in Verilog for `reg`, `integer`, `time`, and vector register data
types. Arrays are accessed by `<array-name>[<subscript>]`. Multidimensional arrays
are not permitted in Verilog.
Examples:
integer count[0:7]; // An array of 8 count variables
reg bool[31:0]; // Array of 32 one-bit boolean register variables

Memories
Memories are declared with the keyword `reg` only. Memories must be one-
dimensional.
Examples:
reg mem1bit[0:1023]; // Memory of 1K 1-bit words
reg [7:0] mem8bit[0:1023]; // Memory of 1K 8-bit words

Parameters
Parameters are constants that can be declared in a module by the keyword
`parameter`.
Examples:
parameter port_id = 5; // Port id is set to 5
parameter cache_line_width = 32; // Cache line is 32-bit wide

Strings
Verilog does not have a string data type. However, a string can be stored in a `reg`.
Examples:
reg [8*18:1] string_value; // Declare a variable that can store an 18 character string
initial string_value = "Hello Verilog World"; // Store string in variable

SYSTEM TASKS
Verilog provides standard system tasks for displaying and monitoring information,
and for stopping and finishing the simulation.

Displaying Information
$display
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Displays information to the screen whenever it is executed. Arguments can be
variables or quoted strings, separated by commas.
Examples:
initial begin
$display("Hello Verilog World");
$display("%b", 9); // Displays the binary number 1001
end

$monitor
Displays information to the screen whenever any one of the monitored variables
changes value.
Examples:
initial begin
$monitor("At time %t, value = %d", $time, value);
end

COMPILER DIRECTIVES
Compiler directives are provided to define macros and include files in Verilog.
Compiler directives affect the way the simulator handles the Verilog code.

`define
Defines a macro. Can be used as a shorthand for longer constructs.
Examples:
`define WIDTH 32
reg [`WIDTH-1:0] data; // Data is a 32-bit register

`include
Includes the contents of a specified file.
Examples:
`include "my_verilog_code.v"

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