Exercise 10.

1
Exercise 10.2
Exercise 10.3
Exercise 10.4

(a) The timing diagram below shows only the missing cells:

(b) The Mealy machine below has 5 states, there is one state for A > B, one state for
A < B, and two states for A = B. Two states are necessary for A = B because 2’s
compliment is inverted for negative numbers, therefore the conditions for being
greater than or less than are different for negative numbers than positive numbers.
Exercise 10.5

In the state diagram, the output signal has bits Sh, Cl, Ld.
Exercise 10.6
Exercise 10.7

Input(4:0)
Reset
Enter

U1

Clk Clk Unlock Unlock

U2
U3 Enter

Input(4:0) Equal Equal

Enter Value(4:0) Value(4:0) Reset

Reset LastValue LastValue

Comparator
Counter Controller

In this case, the counter can be any 4-bit counter, where the sequence in the counter is the
sequence in the combination lock. When the counter reaches the end of the counter, it
asserts the LastValue signal, this tells the controller that it is ready to unlock the door if
the controller has not already gone to the error state.
Exercise 10.8

Starting with how many chips are needed, a 4096 x 1 RAM chip consists of 512 bytes.
Therefore to achieve the goal of 16 KB, 32 chips are needed.

Assuming that the 4096 x 1 RAM is a DRAM, then six address bits are needed for each
chip. Organizing the chips for addressing is very similar to the organization of the
individual chips in 10.21. Basically the 8-bit memory bus must carry all of the address
bits for each DRAM as well as the WE’, CAS’, and RAS’ signals. Each 4096 bit DRAM
requires 6 address bits; therefore, there appears to be a problem in passing each of the
signals as well as the address bits to fully use each 4096 DRAM. Another problem is
actually determining which chip you wish to address. This is where the organization in
10.21 can really help. Dedicating one bit in the bus to be the chip selection bit (CS), this
chip selection bit can be used in conjunction with the CAS’ and RAS’ bits to select which
actual chip to use. When CS is enabled, the WE’ bit can be used as an address bit into
the matrix of chips. When CS’ is enabled, WE’ acts as the write enable bit as usual.

What this yields is that there are 25 * 25 entries in the chip matrix and 24 * 24 entries in
each chip, which yields a 32 KB address space; however, there is still one more problem
to address, since address to each chip are now restricted to 4 bits, it will not completely
use a 4096 bit chip, which means that 32 chips may not be enough. However, this can be
resolved by assigning every 4 rows and 4 columns that are adjacent in the chip selection
matrix to the same physical chip.
Exercise 10.9

Since each row needs to be refreshed once in the 4 ms span of time, then dividing the
4ms by the 512 rows gives the minimum frequency at which row updates need to be
scheduled. This is approximately 7.81 µs. With an 80 ns access time, 50,000 memory
accesses can happen in 4 ms, since 512 of these are dedicated to row refresh operations,
then just over 1% of memory accesses are row refresh operations.
Exercise 10.10

Not yet available.

Exercise 10.11

The minimized cycle time is equivalent to the greater min cycle time of either the Read
Cycle or the Write Cycle. From the diagrams, a Write Cycle has minimum cycle time of
200 ns, the Read Cycle also has a cycle time of 200 ns. It is also important to note the
time at which the output from the Read Cycle is valid outside of the read cycle time, this
does not interfere with the write cycle, because the Write Cycle follows the same
convention in asserting Data Out as the Read Cycle. Therefore since both the Read Cycle
and Write Cycle use 200 ns clock cycles, this is the minimized cycle time.
Exercise 10.12
Exercise 10.13

The Control module uses the two-bit Digit signal to determine which value to pass as
Load3. Load3 is then used as a multiplexer to get the proper values out of the adders.
The adder on the left handles the signal “10”, the middle adder handles “11” and the right
adder handles “01”. There does not need to be any adders for “00” since the Control
module will just opt to pass “00” to Load3 which means that Load3 will stay the same..

This implementation does cut the number of clock cycles in half; however, it also causes
the length of a clock cycle to increase, since the critical path now has to go through two
adders instead of one on each cycle. In this particular case it is indeterminate whether
more logic is better in terms of speed of multiplying; however, looking at broader
circuits, it is often the case where multipliers are bundled in with adders and other circuits
that depend on the same clock. It may be the case that with 2 adders the multiplier
becomes the bottleneck on the clock which in turn slows down all of the other circuits
dependent on that clock.
Exercise 10.14
The implementation below uses the sequential multiplier in figure 10.31. It assumes that
the multiplicand is loaded into the Sequential Multiplier first, (which happens when both
Load1 and Load2 are asserted), and then the multiplier is loaded with only Load1
asserted. Assume that Convert2sComp always just takes the complement of its input.
The multiplixer that feeds the Input bus on the sequential multiplier determines whether
or not to use the converted number or the existing number by looking at the sign bit.
Since both the multiplier and multiplicand go through this logic, this takes care of the
inputs. The output is a little bit more complicated. The two D_FlipFlops keep track of
the sign bits for the multiplier and multiplicand, this is useful because the XOR of just the
sign bits determines whether or not the product should be positive or negative.

U1
U5
In_16(16:0) Out_16(16:0)

Input(8:0) In_8(8:0) Out_8(8:0)

Clk Clock

Convert2sComp Input(8:0)
Load1
Load1
Load2
Load2
Input(8:8)
Product(16:0)
U6
Product(16:0)
Start In_16(16:0) Out_16(16:0)
U3
Start In_8(8:0) Out_8(8:0)

Load1 Clk Q SequentialMultiplier

Convert2sComp
D

D_FlipFlop

U4
Load2 Clk Q

D_FlipFlop
Exercise 10.15

In this implementation it is assumed that the character encoding uses the high order 2-bits
to determine how many times the button has been pressed, thus the difference between a
number and its first letter is always 128. The timing problem of pressing “2” twice and
getting “D” versus hitting “2” twice and getting “22” is solved by adding a Timer (with a
length of roughly a few milliseconds or so). This way there is a certain grazing period at
which it cycles through the “2”, “d”, “e”, “f” rather than adding another “2”.

module KeyboardDecode ( AckS ,R1 ,C1 ,R2 ,C2 ,R3 ,C3 ,R4 ,ResetS ,Send
,CharToSend ,ClkS );

input AckS, R1, C1, R2, C2, R3, C3, R4, ResetS, ClkS;
output [7:0] CharToSend ;
output Send;
reg [7:0] CharToSend;
reg [5:0] TempChar;
reg [5:0] BaseChar;
reg [1:0] KeysHit;
reg ResetTimer;
reg Send;
wire KeyPress, AllowNewPress;

assign KeyPress = (R1 || R2 || R3 || R4) && (C1 || C2 || C3);

// Call a Timer module

.Timer( ResetTimer, AllowNewPress);

always @(posedge ClkS) begin

ResetTimer <= 0'b0;
if (ResetS) begin Send <= 0; end
else begin
if (KeyPress && !AckS) begin
if (R1 && C1) BaseChar <= 6'b110001; // 1abc
if (R1 && C2) BaseChar <= 6'b110010; // 2def
if (R1 && C3) BaseChar <= 6'b110011; // 3ghi
if (R2 && C1) BaseChar <= 6'b110100; // 4jkl
if (R2 && C2) BaseChar <= 6'b110101; // 5mno
if (R2 && C3) BaseChar <= 6'b110110; // 6pqr
if (R3 && C1) BaseChar <= 6'b110111; // 7stu
if (R3 && C2) BaseChar <= 6'b111000; // 8vwx
if (R3 && C3) BaseChar <= 6'b111001; // 9yz
if (R4 && C1) BaseChar <= 6'b101010; // *
if (R4 && C2) BaseChar <= 6'b110000; // 0
if (R4 && C3) BaseChar <= 6'b100011; // #
if (TempChar == BaseChar && !AllowNewPress)
begin
KeysHit <= KeysHit + 1;
CharToSend <= {KeysHit, BaseChar};
ResetTimer <= 1'b1;
end
else begin
KeysHit <= 2'b00;
ResetTimer <= 1'b1;
end
 TempChar <= BaseChar;
end
end
if (AckS) Send <= 0;
end

endmodule
Exercise 10.16

module prob10_16_Sender ( Txd ,AckS ,Send ,Clk ,CharToSend ,ResetS );

input Send, Clk, CharToSend, ResetS ;

output Txd, AckS ;

reg Txd;
reg secondPart;
reg [7:0] charToSend;
reg [3:0] bitCounter;
reg go;

always @(posedge Clk) begin

if (ResetS) begin Txd <= 1; go <= 0; end
else begin
if (Send) begin
charToSend <= CharToSend;
bitCounter <= 0; go <= 1;
secondPart <= 0;
end
else begin
if (bitCounter == 0) Txd <= 0;
else if (bitCounter > 0 && secondPart == 0
&& bitCounter <= 8) begin
Txd <= !charToSend[8 - bitCounter];
secondPart <= 1;
end
else if (bitCounter > 0 && secondPart == 1
&& bitCounter <= 8) begin
Txd <= charToSend[8 - bitCounter];
bitCounter <= bitCounter + 1;
secondPart <= 0;
end
else if (bitCounter > 8) begin Txd <= 1;
go <= 0;
end
end
end

end

assign AckS = go;

endmodule
module prob10_16_Receiver ( AckR ,ClkR ,CharRcvd ,ResetR ,Rxd ,Rcvd );

input AckR, ClkR, ResetR, Rxd

output [7:0] CharRcvd ;

output Rcvd ;

reg [7:0] CharRcvd ;

reg Rcvd ;
reg [8:0] characterReceived;
reg [4:0] bitCounter;
reg [1:0] cycleCounter;
reg secondPart;
reg go;

always @(posedge ClkR) begin

if (ResetR) begin go <= 0; Rcvd <= 0; end
else begin
if (!go && !Rcvd && !AckR && Rxd);
if (!go && !Rcvd && !AckR && !Rxd) begin
go <= 1;
bitCounter <= 0;
cycleCounter <= 0;
secondPart <= 0;
end
if (go) begin
// every four cycles . . .
if (cycleCounter == 0) begin
if (secondPart == 0) begin secondPart <= 1; end
else begin
secondPart <= 0;
characterReceived[8-bitCounter] <= Rxd;
if (bitCounter < 8) bitCounter <=
bitCounter + 1;
else begin
go <= 0;
Rcvd <= 1;
end
end
end
if (AckR) Rcvd <= 0;
end
end
endmodule