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INSTRUCTION SET
Data transfer instructions
The general structure is as follows
MOV opr1, opr2
This instruction transfers the data from OPR2 to OPR1.
(OPR1) ⇽ (OPR2)
The following are the examples of data transfer instructions.

Example MOV AX,BX; This instruction moves the contents of the register BX to the
register AX.

Note: Opr1, and opr2 can be represented by any one of the addressing modes with the
following restrictions:
• Both the operands can not be memory.
• Only source operand can be specified by the immediate mode.
• When the source is immediate data, the destination can be either a register or a
memory location.
• When the source is immediate data the destination can’t be segment register.

Example: MOV AX, [BX]

This instruction transfers 2 bytes of data from data segment memory to AX register.
The register BX contains the offset address.

(AX) DS:[(BX)]
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BEFORE EXECUTION AFTER EXECUTION

AX 7799H 2000H
5678H X10 H DS
AX DS 2000H
BX 7344H
BX 7344H
Data segment memory Data segment memory
+

27344H 99H 27344H 99H

Memory pointer
27345H 27345H 77H
77H
27346H 88H 27346H 88H

Example: MOV AX, 36

This instruction transfers the given data in the instruction to the specified
register. The data itself appears as the second operand of the instruction.

In this example the data 36H is moved to AX register. Since the given data is
only 8-bit and the register specified is 16-bit 00H is attached to the data by the
assembler.

(AX) 00 36H

AFTER EXECUTION
BEFORE EXECUTION

AX 5678H AX 0036H

Example: MOV DS, 34H [BX+SI]

• This instruction transfers data from memory to AX register.

• The EA of the memory is the sum of BX and SI contents.
• The displacement 34H is also added for calculating physical address
• Data segment register DS is used for calculating the physical address.

AX DS: [(BX) + (SI) + 34H]

The operation of the instruction is illustrated as follows

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BEFORE EXECUTION AFTER EXECUTION

SI 3366H SI 3366H

AX 7799H
AX 5678H
BX 7344H
BX 7344H

DS 2000H DS 2000H

Data segment memory

Data segment memory
2A6A9H 33H
33H
2A6A9H
2A6AAH 99H
2A6AAH 99H
2A6ABH 77H
2A6ABH 77H
2A6ACH
88H
2A6ACH 88H

LEA dest, opr

• The “opr” can be represented any of the addressing modes of memory.
• The “dest” can be represented by any 16- bit register of microprocessor.

Working:

• This instruction transfers the effective address of the source operand and
the same is transferred to the specified register in “dest”.

Note: This instruction doesn’t calculate the physical address since the data is
not accessed from memory

Example: LEA BX, [BP+DI]

In the above example, the contents of BX and DI registers are added the result
is the effective address which transferred to the BX register.

(BX) (BP) + (DI)

The operation of this instruction is illustrated as follows:

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BEFORE EXECUTION AFTER EXECUTION

BX 85E1H
BX 1234H
BP 5678H
BP 5678H
DI 3569H
DI 3569H +

LDS dest, opr

• The “opr” can be represented any of the addressing modes of memory.
• The “dest” can be represented by any 16 bit register of microprocessor.
Working:
• This instruction transfers the 16-bit data from memory to the specified
register “dest”.
• Another 16-bit data from the next memory location is transferred to DS
register.

Example: LDS BX, [DI]

• This instruction transfers the 16-bit data from memory to BX register.

• Another 16-bit data from the next memory location is transferred to DS
register.

(BX) DS: [ (DI)]

(DS) DS: [ (DI) + 2]

This operation is illustrated as follows:

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LES dest, opr

• The “opr” can be represented any of the addressing modes of memory.
• The “dest” can be represented by any 16 bit register of microprocessor.
Working:
• This instruction transfers the 16-bit data from memory to the specified register “dest”.
• Another 16-bit data from the next memory location is transferred to ES register.

Example: LES BX, [DI]

Working:
• This instruction transfers the 16-bit data from memory to BX registere.
• Another 16-bit data from the next memory location is transferred to ES register.

(BX) DS: [ (DI)]

(ES) DS: [ (DI) + 2]

This operation is illustrated as follows:

XCHG opr1, opr2

• “opr1” and “opr2” can be represented by any one of the addressing mode except
immediate mode.
• Both the operands can’t be memory.
• Both operands must be of same size.
Working
This instruction will exchange the data present in the two operands.
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Example: XCHG BX, CX

This instruction exchanges the data present the registers BX and CX

The operation of the instruction can be illustrated as fllows:

XLAT
In this instruction the operands are not specified explicitly. But are understood by the
microprocessor as AL, BX registers.

Working:

This instruction transfers one byte of data from the data segment memory to AL register. The
offset address is calculated as sum of the contents of the AL register to BX registers.

(AL) DS:[ (BX) + (AL)]

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STACK RELATED INSTRUCTIONS

• A part of RAM can be used as stack.

• Stack is part of the memory used for temporary storage of data

• The process of transferring data to the stack is called PUSH operation.

• When the data is transferred from the stack memory it is called POP operation.
• Stack pointer ‘SP’ is a register that contains the address of the top of the stack
(TOS)

• With every PUSH operation the SP contents gets decremented and with every
POP operation the SP contents gets incremented.

The PUSH operation is described as follows:

The POP operation is described as follows:

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PUSH opr
• “opr” can be represented by any addressing mode except immediate mode of
addressing.
• “opr” has to be 16-bit operand.
• This instruction is used for transferring the data from “opr” the stack memory.

Working:

• The contents of SP are decremented by 2

(SP) (SP) – 2

• The data from the “opr” is then transferred to the stack memory pointed by SP.
SS: [ (SP)] (opr)

Example: PUSH BX

Working:

• The contents of SP are decremented by 2

(SP) (SP) – 2

• The data from the “BX” is then transferred to the stack memory pointed by SP.
SS: [ (SP)] (BX)

The operation is illustrated as follows:

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example: PUSHF
• In the instruction the operand is not specified.
• The operand is the flag register
• This instruction is used for transferring the data from “flag” to the stack memory.
Working
• The contents of SP are decremented by 2
(SP) (SP) – 2
• The data from the “flag” is then transferred to the stack memory pointed by SP
SS: [ (SP)] (F)

The above operation can be illustrated as follows:

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POP opr
• “opr” can be represented by any addressing mode except immediate mode of
addressing.
• “opr” has to be 16-bit operand.
• This instruction is used for transferring the data from the stack memory to the “opr”

Working:
• The data from the stack memory pointed by SP is transferred to “opr”
(opr) SS: [ (SP)]

• The contents of SP is incremented by 2

(SP) (SP) + 2

Example POP BX
Working:
• The data from the stack memory pointed by SP is transferred to BX register.
(opr) SS: [ (SP)]

• The contents of SP are incremented by 2

(SP) (SP) + 2

The operation of this instruction can be illustrated as follows:

Example: POPF
• The operand is the flag register
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• This instruction is used for transferring the data from the stack memory to the
“flag register”

Working:

• The data from the stack memory pointed by SP is transferred to “flag

register”

(F) SS: [ (SP)]

• The contents of SP is incremented by 2

(SP) (SP) + 2

This operation is illustrated as follows:

Arithmetic instructions
• All arithmetic instructions affect the flags.
• The flag register is a 16-bit register. Each bit of the register is called a FLAG.
• The format of the flag register is as follows.

X X X X OF DF IF TF SF ZF X AF X PF X CF

MACHINE CONTROL
FLAGS CONDITION FLAGS

Explanation of flags:

Condition flags:
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• CF: this flag represents carry from the MS bit

• AF: this flag represents the carry from third bit
• PF: this represents the parity of the result
• SF: this bit becomes ‘1’ when the result is –ve
• ZF: This bit becomes ‘1’ when the result becomes zero
• OF: This flag becomes ‘1’ when overflow occurs. overflow is said to have
occurred when the sign of the result doesn’t match with the sign
of the data.

Machine control flags:

• TF: this is called TRAP flag. When this flag is set then microprocessor
executes the program instruction by instruction and it is called single step
operation
• IF: this is called INTERRUPT flag. When this flag is set the interrupts of the
microprocessor are enabled.
• DF: this is called direction flag. When this flag is set index registers are
automatically decremented while executing string instructions.

ADD opr1, opr2

Rules:

• “opr1” and “opr2” can represented by any mode of addressing

• “opr1” can’t be immediate mode of addressing
• Both “opr1” and “opr2” can’t be represented by memory

Operation:

• The contents of the both operands are added and the result is stored in the
“opr1”

Example: ADD BL, CL

Add the contents of BL and CL and store the result in BL

(BL) (BL) + (CL)

All condition flags are affected based on the result.

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Addition with carry

ADC opr1, opr2

Rules:

• “opr1” and “opr2” can represented by any mode of addressing

• “opr1” can’t be immediate mode of addressing
• Both “opr1” and “opr2” can’t be represented by memory

Operation:

• The contents of the both operands are added along with carry flag and the result
is stored in the “opr1”

(opr1) (opr1) + (opr2) + (CF)

Example: ADC BL, CL

Working:
The contents of BL and CL are added along with CF. The result is stored in BL
registers. All conditional flags are affected based on the result.

(opr1) (opr1) + (opr2) + (CF)

This operation ca be illustrated as follows:

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BCD ADDITION

DAA (Decimal Adjust after Addition)

• After addition of decimal numbers, the result may not be correct in decimal
number system.
• To get the correct decimal result after addition of decimal numbers, DAA
instruction is used.
• The DAA instruction corrects the result in AL register after addition of BCD
numbers to decimal value
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BCD SUBTRACTION
DAS
(Decimal Adjust after Subtraction)

• After subtraction of decimal numbers the result may not be correct in decimal
number system.
• To get the correct decimal result after subtraction of decimal numbers, DAS
instruction is used.
• The DAS instruction corrects the result in AL register after subtraction of BCD
numbers to decimal value
Consider the addition of decimal numbers 98 from 75

The expected decimal answer is 75-98 = -23

The result after the subtraction done by microprocessor = 75H - 98H = DDH
CF AL
The result after usage of DAS instruction is as shown: 1 77

AL register and the carry flag together contain the correct decimal answer

NOTE: Since the result is negative, the CF is set and AL contains the 10s complement

ASCII addition
AAA (ASCII Adjust after Addition)

• After addition of ASCII numbers (of unpacked BCD), the result may not be
correct in ASCII number system.
• To get the correct ASCII result after addition of valid ASCII numbers, AAA
instruction is used.
• The AAA instruction corrects the result in AL register after addition of valid ASCII
numbers to unpacked BCD value
• To the result after above correction, 3030H must be added to AX to get the
answer in ASCII
NOTE: Valid ASCII numbers are: 30H to 39H
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AAS (ASCII Adjust after Subtraction)

• After subtraction of ASCII numbers, the result may not be correct in ASCII
number system.
• To get the correct unpacked BCD result after subtraction of valid ASCII
numbers, AAS instruction is used.
• The AAS instruction corrects the result in AL register after subtraction of valid
ASCII numbers to unpacked BCD value
• To the result after above correction, 3030H must be added to AX to get the
answer in ASCII
NOTEE: Valid ASCII numbers are: 30H to 39H

Multiplication

MUL opr
• The instruction contains only one operand, the other operand is accumulator.
• This instruction performs unsigned multiplication. That is the data is considered
to be unsigned.
• “opr” can be represented by any addressing mode except immediate mode of
addressing
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Working:

8- bit Operation: The contents of the “opr” are multiplied with that of the AL and the
result is stored in AX.
(AX) (AL) x (OPR)

16-bit operation: The contents of the “opr” are multiplied with that of the Ax and the
result is stored in AX and DX registers. AX register contains the lower 16 bits of
the result and DX register contains the higher 16 bits of the result.

(DX) : (AX) (AX) x (OPR)

IMUL opr
• The instruction contains only one operand, the other operand is accumulator.
• This instruction performs signed multiplication. That is the data is considered to
be signed, i.e.., the data can be either positive or negative numbers
• “opr” can be represented by any addressing mode except immediate mode of
addressing

Working:
8- bit Operation: The contents of the “opr” are multiplied with that of the AL and the
result is stored in AX
(AX) (AL) x (OPR)

16-bit operation: The contents of the “opr” are multiplied with that of the Ax and the
result is stored in AX and DX registers
(DX) : (AX) (AX) x (OPR)

AAM (ASCII adjust after multiplication)

• When unpacked BCD numbers are multiplied, the result after the multiplication
may not be correct BCD value since the microprocessor does the multiplication
in HEX.
• To get the correct result after multiplication, AAM instruction is used.
• The result after the execution of this instruction will be correct BCD value in AL
and AH registers.
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DIV opr
• The instruction contains only one operand.
• This instruction performs unsigned division. That is the data is considered to be
unsigned.
• “opr” can be represented by any addressing mode except immediate mode of
addressing

WORKING:

8- bit Operation:
• The contents of the “AX” register are divided with that of the “opr” and the
quotient is stored in AL register and remainder is stored in AH register
(AX) (AL) Q

(OPR) (AH) R

16-bit operation:
• The contents of the “DX” and “AX” registers are divided with that of the “opr”
and the quotient is stored in AX register and remainder is stored in DX register
(DX) : (AX) (AX) Q

(OPR) (DX) R
IDIV opr

• The instruction contains only one operand.

• This instruction performs signed division. That is the data is considered to be
signed.
• “opr” can be represented by any addressing mode except immediate mode of
addressing
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WORKING:

8- bit Operation:
• The contents of the “AX” register are divided with that of the “opr” and the
quotient is stored in AL register and remainder is stored in AH register
(AX) (AL) Q

(OPR) (AH) R

16-bit operation:
• The contents of the “DX” and “AX” registers are divided with that of the “opr”
and the quotient is stored in AX register and remainder is stored in DX register
(DX) : (AX) (AX) Q

(OPR) (DX) R

AAD (ASCII adjust before division)

• When BCD numbers are multiplied, the result after the multiplication may not be
correct BCD value since the microprocessor does the multiplication in HEX.
• To get the correct result after multiplication, AAM instruction is used. This
instruction must be used before performing division.
• Then the result after the division will be correct BCD value. The BCD quotient
will be in AL register and BCD remainder will be in AH register.

Jump and call instructions

JUMP instructions:
These instructions are used for changing the control of sequence of program execution.
Let us understand the process of program execution

Role of IP
• IP always contains the address of next instruction to be fetched.
• After completion of execution of current instruction, µC fetches the next instruction
pointed by IP.
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• While fetching an instruction the contents of IP is incremented whether IP must be

incremented by ’1’ or ‘2’ is decided by the instruction under execution
• For JUMP operation to take place the contents of IP must be altered.

Types of JUMP instructions

CONDITIONAL JUMP SHORT JUMP

SHORT JUMP

DIRECT JUMP

CONDITIONAL JUMP NEAR JUMP

INDIRECT JUMP

DIRECT JUMP

FAR JUMP

INDIRECT JUMP
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NOTE:
If the microprocessor jumps within the same code segment memory (CS register
contents not altered), it is called intra-segment jump operation.
If the microprocessor jumps from one code segment to another (CS register
contents altered), it is called inter-segment jump operation.

UNCONDITIONAL SHORT JUMP

JMP SHORT rel_addr
• “rel_addr” is an 8-bit number. It is called relative address.
• SHORT is an assembler directive
• This instruction alters only the contents of IP and CS register contents is not
altered.
• Hence, microprocessor jumps within the same code segment memory.
• Therefore, it is called INTRASEGMENT jump operation.
• The given “rel_addr” is added to IP
(IP) (IP) + rel_addr

UNCONDITIONAL NEAR DIRECT JUMP

JMP NEAR rel_addr

• “rel_addr” is an 16-bit number. It is called relative address.
• NEAR is an assembler directive.
• This instruction alters only the contents of IP and CS register contents is not
altered.
• Hence, microprocessor jumps within the same code segment memory.
• Therefore, it is called INTRASEGMENT jump operation.
• The given “rel_addr” is added to IP
(IP) (IP) + rel_addr

UNCONDITIONAL NEAR INDIRECT JUMP

JMP NEAR opr
• “opr” is a 16-bit register of the microprocessor or memory operand.
• This instruction alters only the contents of IP and CS register contents is not
altered.
• Hence, microprocessor jumps within the same code segment memory.
• Therefore, it is called INTRASEGMENT jump operation.
• The given “rel_addr” is transferred to IP
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(IP) (opr)

UNCONDITIONAL FAR DIRECT JUMP

• JMP FAR L_addr
• “L_addr” is an 32-bit number.
• NEAR is an assembler directive.
• This instruction alters both the contents of IP and CS register.
• Hence, microprocessor can jump from one code segment memory to another.
• Therefore, it is called INTERSEGMENT jump operation.
• The lower 16 bits of L_addr is transferred to IP and higher 16 bits are transferred
to CS
(IP) Lower 16 bits of L_addr ;
(CS) higher 16 bits of L_addr

UNCONDITIONAL FAR INDIRECT JUMP

• JMP FAR opr
• “opr” is a memory operand .
• FAR is an assembler directive.
• This instruction alters both the contents of IP and CS register.
• Hence, microprocessor can jump from one code segment memory to another.
• Therefore, it is called INTERSEGMENT jump operation.
• The lower 16 bits of “opr” is transferred to IP and higher 16 bits are transferred to
CS
(IP) lower 16 bits of (opr);
(CS) higher 16 bits of (opr)
CONDITIONAL JUMP

J<condition> rel_addr
• “rel_addr” is an 8-bit number. It is called relative address.
• The <condition> is user specified.
• This instruction alters only the contents of IP and CS register contents is not
altered.
• Hence, microprocessor jumps within the same code segment memory.
• Therefore, it is called INTRASEGMENT jump operation.
Operation:
• Microprocessor checks the specified condition
• If the condition is TRUE, microprocessor performs JUMP operation by adding
the given “rel_addr” is added to IP
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(IP) (IP) + rel_addr

• If the condition is FALSE, the microprocessor doesn’t perform the JUMP
operation. That is the contents of IP are not altered.

List of condition jump instructions for unsigned operation

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List of condition jump instructions for signed operation

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JCXZ rel_addr

• This is a conditional jump instruction

• Operation:
• Microprocessor checks contents of CX register.
• If CX contents are equal to zero microprocessor performs jump operation by
adding the “rel_addr” to IP.
• (IP) (IP) + rel_addr
• If CX contents are not equal to zero, microprocessor doesn’t perform jump
operation.

Iteration control instructions

This is similar to FOR-LOOP statement of c programming language

Various loop instructions are:
• LOOP rel_addr
• LOOPE rel_addr / LOOPZ rel_addr
• LOOPNE rel_addr /LOOPNZ rel_addr

LOOP rel_addr
This is conditional jump instruction

OPERATION:
• The contents of CX register is decremented.
(CX) (CX) -1
• Then microprocessor checks the contents of CX.
• If CX contents are not equal to zero, then microprocessor performs JUMP
operation by adding the “rel_addr” to IP.
• If cx contents is equal to zero, microprocessor doesn’t perform JUMP
operation

LOOPE rel_addr
This is conditional jump instruction

OPERATION:

• The contents of CX register is decremented.

(CX) (CX) -1
• Then microprocessor checks the contents of CX.
o If CX contents are not equal to zero and ZF =1 then microprocessor
performs JUMP operation by adding the “rel_addr” to IP.
o If cx contents is equal to zero or ZF =0, microprocessor doesn’t perform
JUMP operation

LOOPNE rel_addr
This is conditional jump instruction
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OPERATION:

• The contents of CX register is decremented.

(CX) (CX) -1
• Then microprocessor checks the contents of CX.
o If CX contents are not equal to zero and ZF =0 then microprocessor
performs JUMP operation by adding the “rel_addr” to IP.
o If cx contents is equal to zero or ZF =1, microprocessor doesn’t perform
JUMP operation

COMPARE OPERATION

CMP opr1, opr2

Rules:

• “opr1” and “opr2” can represented by any mode of addressing

• “opr1” can’t be immediate mode of addressing
• Both “opr1” and “opr2” can’t be represented by memory

Operation:

• The contents of the both operands are COMPARED. There is no result of

comparison. Therefore, the both the operands contents will remain unaltered.
• Only the flags are affected.

Relation between the operands Flag status

Opr1 equals to opr2 ZF = 1
Opr1 not equals to opr2 ZF =0
Opr1 > opr2 CF =0 & ZF= 0
Opr1 < opr2 CF = 1
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ROTATE OPERATIONS
The various rotate instructions are:
• Rotate right without carry
• Rotate right with carry
• Rotate left without carry
• Rotate left with carry

Rotate right without carry

ROR opr, 1

• “opr” can be represented by any addressing mode except immediate mode.

• This instruction performs single rotate operation
• The least significant bit of the operand is shifted to carry flag. The same bit is
shifted to most significant bit position of the operand.
• All the other bits of the operand are shifted right by one-bit position

D7 D6 D5 D4 D3 D2 D1 D0 C

After execution:
D0 D7 D6 D5 D4 D3 D2 D1 D0

ROR opr, CL
• “opr” can be represented by any addressing mode except immediate mode.
• The least significant bit of the operand is shifted to carry flag. The same bit is
also shifted to most significant bit position of the operand.
• All the other bits of the operand are shifted right by one-bit position
• This instruction performs multiple rotate operation. The number of rotate
operation is specified in CL register.

Rotate right with carry

RCR opr, 1

• “opr” can be represented by any addressing mode except immediate mode.

• This instruction performs single rotate operation
• The least significant bit of the operand is shifted to carry flag. The carry flag is
shifted to most significant bit position of the operand.
• All the other bits of the operand are shifted right by one-bit position

Before execution

D7 D6 D5 D4 D3 D2 D1 D0 C
After execution
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C D7 D6 D5 D4 D3 D2 D1 D0

Rotate left without carry

ROL opr, 1

• “opr” can be represented by any addressing mode except immediate mode.

• This instruction performs single rotate operation
• The most significant bit of the operand is shifted to carry flag. The same bit is
shifted to least significant bit position of the operand.
• All the other bits of the operand are shifted left by one-bit position

D7 D6 D5 D4 D3 D2 D1 D0 C

After execution:
D6 D5 D4 D3 D2 D1 D0 D7 D7

ROL opr, CL
• “opr” can be represented by any addressing mode except immediate mode.
• The most significant bit of the operand is shifted to carry flag. The same bit is
also shifted to least significant bit position of the operand.
• All the other bits of the operand are shifted left by one-bit position
• This instruction performs multiple rotate operation. The number of rotate
operation is specified in CL register.

Rotate left with carry

RCL opr, 1

• “opr” can be represented by any addressing mode except immediate mode.

• This instruction performs single rotate operation
• The most significant bit of the operand is shifted to carry flag. The carry flag is
shifted to least significant bit position of the operand.
• All the other bits of the operand are shifted left by one-bit position

Before execution

D7 D6 D5 D4 D3 D2 D1 D0 C
After execution

D6 D5 D4 D3 D2 D1 D0 C D7

RCL opr, CL
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• “opr” can be represented by any addressing mode except immediate mode.

• The most significant bit of the operand is shifted to carry flag. The carry flag is
shifted to least significant bit position of the operand.
• All the other bits of the operand are shifted left by one-bit position
• This instruction performs multiple rotate operation. The number of rotations is
decided by the contents of CL register.

SHIFT OPERATIONS
The various shift operations are:
Logical left shift/ arithmetic left shift
Logical right shift
Arithmetic right shift.

The shift operation can be done as much number of times as the contents of CL
register or a single shift operation.
Left shift operation
SAL opr, 1 (or) SHL opr, 1
“opr” can be represented by any mode of addressing except immediate mode.
• The most significant bit of the operand is shifted to the carry flag.
• All other bits of “opr” are shifted left by one bit position.
• A “0” is shifted in to the LS bit position of “opr”
• This instruction performs single shift operation.
• The instruction SAL opr, CL or SHL opr, CL is similar but performs multiple shift
operations. The number of shift operations is decided by the contents of CL
register.
Before execution after execution
C D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0

Logical right shift operation

SHR opr, 1
• “opr” can be represented by any mode of addressing except immediate mode.
• The least significant bit of the operand is shifted to the carry flag.
• All other bits of “opr” are shifted right by one bit position.
• The MS bit position of “opr” is retained
• This instruction performs single shift operation.

Before execution
CF

D7 D6 D5 D4 D3 D2 D1 D0 C

After execution
CF

0 D7 D6 D5 D4 D3 D2 D1 D0
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Arithmetic right shift operation

SAR opr,1
• “opr” can be represented by any mode of addressing except immediate mode.
• The least significant bit of the operand is shifted to the carry flag.
• All other bits of “opr” are shifted right by one bit position.
• The MS bit position of “opr” is retained
• This instruction performs single shift operation.

Before execution
CF

D7 D6 D5 D4 D3 D2 D1 D0 C

Before execution
CF

D7 D7 D6 D5 D4 D3 D2 D1 D0

STRING INSTRUCTION

• A string is an array of data

• In 8086, there are two strings:
• Source string ;The source is stored in data segment memory and is
pointed by SI register
• Destination string; The destination string is stored in the extra
segment memory and is pointed by DI register.

VARIOUS STRING INSTRUCTIONS ARE

• MOVS
• REP
• LODS
• STOS
• CMPS
• REPE
• SCAS
• REPNE
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MOVS

• This instruction can be written as

MOVSB
MOVSW
• MOVSB instruction performs 8-bit operation while MOVSW performs 16-bit operation
• This instruction transfers the data from source string to destination string
• ES:[(DI)] DS:[(SI)]
• After executing the instruction, the index registers are incremented or decremented
depending status of DF.

REP

• This is a prefix instruction.

• This prefix instruction is used along with a string instruction

Example: REP MOVSB

Operation:

The sequence of steps of operation is as follows:

1. µp checks the contents of CX register. If it is equal to zero, µp executes the next
instruction
2. If CX is not equal to zero, then the µp executes the string instruction.
3. µp goes back to step number 1
Thus, µp executes the string instruction as many times as the contents of string
instruction.

LODS

• This instruction can be written as

LODSB
LODSW
• LODSB instruction performs 8-bit operation while LODSW performs 16-bit
operation
• This instruction transfers the data from accumulator to destination string
ES:[(DI)] (accumulator)
• After executing the instruction, the index register are incremented or decremented
depending status of DF.

STOS

• This instruction can be written as

o STOSB
o STOSW
• STOSB instruction performs 8-bit operation while STOSW performs 16-bit
operation
• This instruction transfers the data from source string to accumulator
 33

(accumulator) DS:[(SI)]
• After executing the instruction, the index register is incremented or decremented
depending status of DF.

CMPS

• This instruction can be written as

CMPSB
CMPSW
• CMPSB instruction performs 8-bit operation while CMPSW performs 16-bit
operation
• This instruction compares the data in source string with data in destination string.
The comparison is performed by subtraction.
DS:[(SI)] ES:[ (DI) ]
• After executing the instruction, the index register is incremented or decremented
depending status of DF.

REPE
• This is a prefix instruction.
• This prefix instruction is used along with a string instruction

Example: REPE CMPSB

OPERATION:

The sequence of steps of operation is as follows:

1. µp checks the contents of CX register. If it is equal to zero, µp executes the next
instruction
2. If CX is not equal to zero, then the µp executes the string instruction.
3. µp goes back to step number 1 if ZF = 1, otherwise (ZF =0), µp executes the next
instruction.
This is useful to be used for comparing two strings

SCAS

• This instruction can be written as

SCASB
SCASW
• SCASB instruction performs 8-bit operation while SCASW performs 16-bit
operation
• This instruction compares the data in source string with data in Accumulator. The
comparison is performed by subtraction.
o (accumulator) ES:[(DI)]
• After executing the instruction, the index register is incremented or decremented
depending status of DF.
 34

REPNE
• This is a prefix instruction.
• This prefix instruction is used along with a string instruction

Example: REPNE SCASB

Operation:

The sequence of steps of operation is as follows:

4. µp checks the contents of CX register. If it is equal to zero, µp executes the next
instruction
5. If CX is not equal to zero, then the µp executes the string instruction.
6. µp goes back to step number 1 if ZF = 0, otherwise (ZF =0), µp executes the next
instruction.
This is useful to be used for searching for a key element in a string (linear search)

PROCEDURES

• Any program can be divided into smaller part and each smaller part can be
individually developed and tested.
• This approach simplifies the process the software development.
• This technique is called modular programming.
• Each smaller part of a modular program is called a procedure.
• µp executes the instructions of main program sequentially.
• When CALL instruction is executed the control of program execution is
transferred to subroutine after storing the RETURN address on the stack.
• Then the procedure is executed.
• When RET instruction is executed, the control of program execution is transferred
back to the main program.

Various call instructions: DIRECT

NEAR

INDIRECT

DIRECT

FAR

INDIRECT
35
 36

DIRECT NEAR CALL

CALL addr

• “addr” is a 16-bit signed number.

• This instruction is used for transferring the control of program execution to a
procedure present in the same code segment memory.
• Hence it is called “intra segment CALL” instruction.
• This instruction alters the contents only IP register without affecting the contents
of CS register.

EX: CALL 1234H

Working:
• The RETURN address in IP register is saved on the stack by performing PUSH
operation.
(SP) (SP)-2
SS:[SP] (IP)
• The contents of IP is modified to branch to procedure by adding the “addr” to IP
(IP) (IP) + 1234H

INDIRECT NEAR CALL

CALL opr

• “opr” is any 16-bit register or memory location.

• This instruction is used for transferring the control of program execution to a
procedure present in the same code segment memory.
• Hence it is called “intra segment CALL” instruction.
• This instruction alters the contents only IP register without affecting the contents
of CS register.
EX: CALL BX
Working:
• The RETURN address in IP register is saved on the stack by performing PUSH
operation.
(SP) (SP)-2
SS:[SP] (IP)
• The contents of IP is modified to branch to procedure by transferring the contents
of BX to IP
(IP) (BX)
DIRECT FAR CALL

CALL FAR addr

• FAR is an assembler directive
• “addr” is a 32-bit signed number.
• This instruction is used for transferring the control of program execution to a
procedure present in another code segment memory.
• Hence it is called “inter segment CALL” instruction.
 37

• This instruction alters the contents both IP register and CS register.

EX: CALL FAR 12345678H

Working:
The RETURN address in CS and IP registers is saved on the stack by performing PUSH
operation.
(SP) (SP)-2
SS:[SP] (CS)
(SP) (SP)-2
SS:[SP] (IP)

The contents of IP and CS are modified to branch to procedure by transferring the “addr”
to IP and CS
(IP) 1234H
(CS) 5678H

DIRECT FAR CALL

CALL FAR opr

• FAR is an assembler directive
• “opr” is a memory operand.
• This instruction is used for transferring the control of program execution to
a procedure present in another code segment memory.
• Hence it is called “inter segment CALL” instruction.
• This instruction alters the contents both IP register and CS register.

EX: CALL FAR [BX]

Working:
The RETURN address in CS and IP registers is saved on the stack by performing
PUSH operation.

(SP) (SP)-2
SS:[SP] (CS)

(SP) (SP)-2
SS:[SP] (IP)

The contents of IP and CS are modified to branch to procedure by transferring the

address to IP and CS from the data segment memory

(IP) DS:[BX]
(CS) DS:[BX+2]
 38

RET

• This instruction is used for transferring the control of program execution from
procedure to main program.
• The return address present in stack is POPed to only IP register in case of NEAR
operation.
• In case of FAR operation, the return address is POPed to IP and CS also.
• The assembler directive will identify whether the instruction should perform NEAR
or FAR return operation

MACHINE CONTROL INSTRUCTIONS

STI
• This instruction will SET the interrupt flag.
• The other flags are not affected.
• The status of the flag register after the execution is as follows.

CLI
• This instruction will CLEAR the interrupt flag.
• The other flags are not affected.
• The status of the flag register after the execution is as follows.

CLD
• This instruction will CLEAR the direction flag.
• The other flags are not affected.
• The status of the flag register after the execution is as follows.

STD
• This instruction will SET the direction flag.
• The other flags are not affected.
• The status of the flag register after the execution is as follows.

DATA TRANSFER WITH I/O PORTS

The input/output ports may be connected in memory mapped IO or IO mapped IO. For
IO mapped IO (also called isolated IO), IN and OUT instructions are used.

The instructions of IO mapped IO have two addressing modes:

• Fixed port IO addressing
• Variable port IO addressing.
All data transfer with IO ports are with accumulator only.

Ex1: IN AL, 56H

 39

In the above instruction 56H is the 8-bit address of the input port.

This instruction transfers 1-byte of data from the port to the AL register. The port
address is as specified in the instruction.
Before execution
After execution

AL 56H AL 89H

56H 89H 56H 89H

PORT PORT

Ex2: IN AL, DX

This instruction has variable port addressing. The register DX contains the address of
the port.
Before execution After execution

DX 5678H DX 5678H

AL 34H AL 89H

5678H 89H 5678H 89H

PORT
PORT
This instruction transfers 16-bit of data from the specified port to AX register.

Ex3: OUT 56H, AL

This instruction transfers 8 bits of data from AL register to the specified port whose
address is 56H. Before execution After execution

AL 56H AL 56H
Before execution
After execution

AL 56H 56H89H
AL 56H56H56H
PORT
PORT
56H 89H 56H 56H
PORT
PORT

Ex4: OUT DX, AL

This instruction has variable port addressing. The register DX contains the address of
the output port. The instruction transfers the contents of the AL register to the specified
port. The instruction transfers 8 bits of data.
 40

Before execution
After execution
DX 5678H DX 5678H

AL 34H AL 34H

5678H 89H 5678H 34H

PORT
PORT

NEG instruction
Syntax: NEG operand
The operand can be represented by any one of the addressing mode. But immediate
mode can’t be used.
Working: this isntruction replaces the contents of the operand with the 2's complement
and that number.This is achieved by taking 1’s complement and adding ‘1’.

NOT instruction
This instruction replaces the contents of the specified operad by its 1’s complement.
Syntax: NOT opr
The ‘opr’ may be specified by any one of the addresssing modes except immediate
mode of addressing.

RET n

This instruction performs either NEAR or FAR return depending on the declaration of
the ‘procedure’ as explained earlier.

Then stack pointer (SP) contents are modified by adding the number ‘n’ specified in the
instruction to SP.

(SP) <— (SP) + n

Thus this instruction can be used for returning the control to the calling program and to
alter the stack pointer contents. Hence, the calling program will be now using different
portion of stack. Therefore, the above instruction is useful for redefining the stack.

ESC instruction
• This instruction is used to pass instructions to a coprocessor such as 8087.
• The coprocessor and the main processor share the same system bus. The
coprocessor instructions are written along with the instructions of the main
processor instructions. The main processor brings all instructions from the
memory and stores the same in the Queue. The same instructions are also
fetched by the coprocessor which stores these opcodes in its Queue.
• All coprocessor instructions have a 6 bit ESC code to distinguish the co-
processor instructions from these main processor instruction.
 41

• The main processor treats all opcode with ESC bits as NOP and these
instructions are executed by only the co-processor.
HLT
• This instruction will stop the 8086 to stop the fetching and executing of
instructions.
• The 8086 will enter halt state. The only way to get the p out of the halt state is
by the interrupt signal on INTR, NMI or RESET pin.
NOP
• This instruction simply uses up three clock cycles
• increments IP to point to next instruction.
• This instruction affect no flags.
• This instruction can be used to increase the delay of a loop.
• This instruction can also be used to hold a place in a program for an instruction
that will be added later.
CMC
This instruction complements the status of the carry flag. No other flags are affected.
LOCK
• Many microcomputer systems many ps. Each p has its own bus and memory.
The individual microprocessors are connected together by a system bus so that
each can access the common system resource such as disk drives or memory.
• Each p takes control of the system bus only when it needs to access the
system resource.
• The LOCK prefix makes it sure that another processor does not take control of
the system bus when it is in the middle of critical instruction which uses the
system bus. The LOCK prefix is put in front of the critical instruction.
• When an instruction with LOCK prefix instruction executes, the 8086 will assert
its bus lock signal output. This signal is connected to an external bus controller
device which then prevents another processor from taking over the system bus.
• This instruction affect no flags.
WAIT
• When this instruction executes, the 8086 will enter into an idle state where it
does no processing.
• In the idle state the 8086 will test TEST signal and remains in the idle state until
the TEST signal is high.
• When the TEST signal becomes high, the 8086 will exit the idle state and
executes the next instruction.
• The 8086 will exit the idle state if a valid interrupt occurs. After servicing the
ISSR of the interrupt the 8086 will return to idle state.
• This instruction does not affect any flags.
• This instruction is used to synchronize the coprocessor.