Ordering number : ENA1955

LC87FBL08A
CMOS IC
8K-byte FROM and 256-byte RAM integrated
http://onsemi.com
8-bit 1-chip Microcontroller

Overview
The LC87FBL08A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-board-
programmable), 256-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, an asynchronous/synchronous SIO interface, two 12-bit PWM
channels, a 12-bit/8-bit 11-channel AD converter, a system clock frequency divider, an internal reset and a 17-source
9-vector interrupt feature.

Features
Flash ROM
• Capable of On-board programming with wide range (2.7 to 5.5V) of voltage source.
• Block-erasable in 128 byte units
• Writable in 2-byte units
• 8192 × 8 bits

RAM
• 256 × 9 bits

Minimum Bus Cycle

• 83.3ns (12MHz at VDD=2.7V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.

* This product is licensed from Silicon Storage Technology, Inc. (USA).

Semiconductor Components Industries, LLC, 2013

May, 2013 Ver.1.00 52511HKIM 20110419-S00003 No.A1955-1/28
 LC87FBL08A
Minimum Instruction Cycle Time
• 250ns (12MHz at VDD=2.7V to 5.5V)

Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units 17 (P1n, P20, P21,P30, P31, P70 to P73, CF2/XT2)
Ports I/O direction can be designated in 4-bit units 8 (P0n)
• Dedicated oscillator ports/input ports 1 (CF1/XT1)
• Reset pin 1 (RES)
• Power pins 3 (VSS1, VSS2, VDD1)

Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes

SIO
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)

AD Converter: 12 bits/8 bits × 11 channels

• 12 bits/8 bits AD converter resolution selectable

PWM: Multifrequency 12-bit PWM × 2 channels

Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)

Clock Output Function

• Capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected
as the system clock.
• Capable generating the source clock for the subclock

Watchdog Timer
• Capable generating an internal reset on an overflow of a timer running on the low-speed RC oscillator clock or
subclock.
• Operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a
count value held).

No.A1955-2/28
 LC87FBL08A
Interrupts
• 17 sources, 9 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.

No. Vector Address Level Interrupt Source

1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L/INT4
4 0001BH H or L INT3/INT5/base timer

5 00023H H or L T0H

6 0002BH H or L T1L/T1H

7 00033H H or L None

8 0003BH H or L SIO1

9 00043H H or L ADC/T6/T7/PWM4, PWM5

10 0004BH H or L Port 0
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 128levels (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

• 16 bits × 8 bits (5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits (8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)

Oscillation Circuits
• Internal oscillation circuits
Low-speed RC oscillation circuit : For system clock (100kHz)
Medium-speed RC oscillation circuit : For system clock (1MHz)
Frequency variable RC oscillation circuit : For system clock (8MHz)
• External oscillation circuits
Hi-speed CF oscillation circuit: For system clock, with internal Rf
Low speed crystal oscillation circuit: For low-speed system clock, with internal Rf
1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control.
2) Both the CF and crystal oscillator circuits stop operation on a system reset. After reset is released, oscillation
is stopped so start the oscillation operation by program.

System Clock Divider Function

• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (at a main clock rate of 10MHz).

Internal Reset Function

• Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 4 levels (2.57V, 2.87V, 3.86V, and 4.35V) through option
configuration.
• Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V, 4.28V) can be
selected by optional configuration.

No.A1955-3/28
 LC87FBL08A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer or low-voltage detection.
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Note: Available only when X’tal oscillation is selected.

Onchip Debugger
• Supports software debugging with the IC mounted on the target board.
• Software break point setting for debugger.
• Stepwise execution on debugger.
• Real time RAM data monitoring function on debugger.
All the RAM data map can be monitored on screen when the program is running.
(The RAM & SFR data can be changed by screen patch when the program is running)
• Two channels of on-chip debugger pins are available to be compatible with small pin count devices.
DBGP0 (P0), DBGP1 (P1)

Data Security Function (flash versions only)

• Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.

Package Form
• QFP36(7×7) : Lead-/Halogen-free type
• VQLP32(4×4) : Lead-/Halogen-free type (build-to-order )

Development Tools
• On-chip-debugger : (1) TCB87 TypeB + LC87FBL08A
(2) TCB87 TypeC (3 wire version) + LC87FBL08A

No.A1955-4/28
 LC87FBL08A
Flash ROM Programming Boards
Package Programming boards
QFP36 W87F24Q
VQLP32 (build-to-order )

Flash ROM Programmer

Maker Model Supported version Device
Single AF9709/AF9709B/AF9709C
Rev 03.28 or later 87F008SU
Programmer (Including Ando Electric Co., Ltd. models)
Flash Support Group, Inc. AF9723/AF9723B(Main body)
- -
(FSG) Gang (Including Ando Electric Co., Ltd. models)
Programmer AF9833(Unit)
- -
(Including Ando Electric Co., Ltd. models)
Flash Support Group, Inc. AF9101/AF9103(Main body)
(FSG) (FSG models)
In-circuit
+ (Note 2) -
Programmer SIB87(Inter Face Driver)
Our company
(Our company model)
(Note 1)
Single/Gang SKK / SKK Type B / SKK Type C Application Version
Programmer (SanyoFWS) 1.06 or later
Our company LC87FBL08
In-circuit/Gang SKK-DBG Type B / SKK-DBG Type C Chip Data Version
Programmer (SanyoFWS) 2.34 or later
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: [email protected]

Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together
can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or Our company for the information.

No.A1955-5/28
 LC87FBL08A
Package Dimensions
unit : mm (typ)
3162C

9.0
7.0

0.5
27 19

28 18

7.0
9.0
36 10
1 9
0.65 0.3 0.15
(0.9)
1.7max
(1.5)
0.1

SANYO : QFP36(7X7)

Package Dimensions
unit : mm (typ)
3331

TOP VIEW BOTTOM VIEW

4.0 0.35
17 24

16 25
0.35
4.0

0.4

32
9
8 1
(0.6)

0.2 (0.6)
0.85MAX

SIDE VIEW
0.0NOM
0.05

SANYO : VQLP32(4.0X4.0)

No.A1955-6/28
 LC87FBL08A
Pin Assignment

P31/PWM5/INT5/T1IN
P30/PWM4/INT5/T1IN
P21/INT4/T1IN
P03/AN3
P02/AN2
P01/AN1
P00/AN0
VSS2
N.C.
27
26
25
24
23
22
21
20
19
P04/AN4 28 18 P20/INT4/T1IN
P05/AN5/CKO/DBGP00 29 17 P17/T1PWMH/BUZ
P06/AN6/T6O/DBGP01 30 16 P16/T1PWML
P07/T7O/DBGP02 31 15 N.C.
N.C. 32 LC87FBL08A 14 N.C.
N.C. 33 13 P15/SCK1/DGBP10
P70/INT0/T0LCP/AN8 34 12 P14/SI1/SB1/DBGP11
P71/INT1/T0HCP/AN9 35 11 P13/SO1/DBGP12
P72/INT2/T0IN/AN10 36 10 P12
1
2
3
4
5
6
7
8
9
RES

VSS1

P10
P11
P73/INT3/T0IN/AN11

N.C.

CF1/XT1
CF2/XT2
VDD1
Top view

QFP36(7×7) “Lead-/Halogen-free Type”

QFP36 NAME QFP36 NAME

1 P73/INT3/T0IN/AN11 19 P21/INT4/T1IN

2 RES 20 P30/PWM4/INT5/T1IN

3 N.C. 21 P31/PWM5/INT5/T1IN

4 VSS1 22 N.C.

5 CF1/XT1 23 VSS2

6 CF2/XT2 24 P00/AN0

7 VDD1 25 P01/AN1

8 P10 26 P02/AN2

9 P11 27 P03/AN3

10 P12 28 P04/AN4

11 P13/SO1/DBGP12 29 P05/AN5/CKO/DBGP00

12 P14/SI1/SB1/DBGP11 30 P06/AN6/T6O/DBGP01

13 P15/SCK1/DBGP10 31 P07/T7O/DBGP02

14 N.C. 32 N.C.

15 N.C. 33 N.C.

16 P16/T1PWML 34 P70/INT0/T0LCP/AN8

17 P17/T1PWMH/BUZ 35 P71/INT1/T0HCP/AN9

18 P20/INT4/T1IN 36 P72/INT2/T0IN/AN10
Note: N.C. pins must be held open (disconnected).

No.A1955-7/28
 LC87FBL08A

19 P31/PWM5/INT5/T1IN
18 P30/PWM4/INT5/T1IN
17 P21/INT4/T1IN
24 P03/AN3
23 P02/AN2
22 P01/AN1
21 P00/AN0
20 VSS2
P04/AN4 25 16 P20/INT4/T1IN
P05/AN5/CKO/DBGP00 26 15 N.C.
P06/AN6/T6O/DBGP01 27 14 P17/T1PWMH/BUZ
P07/T7O/DBGP02 28 13 P16/T1PWML
LC87FBL08A
P70/INT0/T0LCP/AN8 29 12 P15/SCK1/DBGP10
P71/INT1/T0HCP/AN9 30 11 P14/SI1/SB1/DBGP11
P72/INT2/T0IN/AN10 31 10 P13/SO1/DBGP12
P73/INT3/T0IN/AN11 32 RES 1 9 P12
N.C. 2
VSS1 3
CF1/XT1 4
CF2/XT2 5
VDD1 6
P10 7
P11 8
Top view

VQLP32(4×4) “Lead-/Halogen-free Type” (build-to-order )

VQLP32 NAME VQLP32 NAME

1 RES 17 P21/INT4/T1IN

2 N.C. 18 P30/PWM4/INT5/T1IN

3 VSS1 19 P31/PWM5/INT5/T1IN

4 CF1/XT1 20 VSS2

5 CF2/XT2 21 P00/AN0

6 VDD1 22 P01/AN1

7 P10 23 P02/AN2

8 P11 24 P03/AN3

9 P12 25 P04/AN4

10 P13/SO1/DBGP12 26 P05/AN5/CKO/DBGP00

11 P14/SI1/SB1/DBGP11 27 P06/AN6/T6O/DBGP01

12 P15/SCK1/DBGP10 28 P07/T7O/DBGP02

13 P16/T1PWML 29 P70/INT0/T0LCP/AN8

14 P17/T1PWMH/BUZ 30 P71/INT1/T0HCP/AN9

15 N.C. 31 P72/INT2/T0IN/AN10

16 P20/INT4/T1IN 32 P73/INT3/T0IN/AN11
Note: N.C. pins must be held open (disconnected).

No.A1955-8/28
 LC87FBL08A
System Block Diagram

Interrupt control IR PLA

Standby control Flash ROM

CF/
X'tal

generator
Clock
SRC PC
RC

MRC

RES ACC
Reset control

WDT B register

Reset circuit
(LVD/POR) C register

Bus interface ALU

SIO1 Port 0

Timer 0 PSW
Port 1

RAR
Timer 1 Port 2

RAM
Timer 6 Port 3

Stack pointer
Timer 7 Port 7

Base timer ADC On-chip-debugger

INT0-2
PWM4
INT3 (Noise filter)

PWM5 Port 2 INT4

Port 3 INT5

No.A1955-9/28
 LC87FBL08A
Pin Description
Pin Name I/O Description Option
VSS1, VSS2 - - Power supply pin No
VDD1 - + Power supply pin No
Port 0 I/O • 8-bit I/O port
P00 to P07 • I/O specifiable in 4-bit units
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions Yes
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P06(AN6): AD converter input
P05(DBGP00) to P07(DBGP02): On-chip debugger 0 port
Port 1 I/O • 8-bit I/O port
P10 to P17 • I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P13: SIO1 data output
Yes
P14: SIO1 data input / bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output / beeper output
P15(DBGP10) to P13(DBGP12): On-chip-debugger 1 port
Port 2 I/O • 2-bit I/O port
P20 to P21 • I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input /
timer 0H capture input
Yes
Interrupt acknowledge types
Rising &
Rising Falling H level L level
Falling
INT4 enable enable enable disable disable

Port 3 I/O • 2-bit I/O port

P30 to P31 • I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P30: PWM4 output
P31: PWM5 output
P30 to P31: INT5 input/HOLD reset input / timer 1 event input / timer 0L capture input / Yes
timer 0H capture input
Interrupt acknowledge types
Rising &
Rising Falling H level L level
Falling
INT5 enable enable enable disable disable

Continued on next page.

No.A1955-10/28
 LC87FBL08A
Continued from preceding page.
Pin Name I/O Description Option
Port 7 I/O • 4-bit I/O port
P70 to P73 • I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P70: INT0 input / HOLD reset input / timer 0L capture input
P71: INT1 input / HOLD reset input / timer 0H capture input
P72: INT2 input / HOLD reset input / timer 0 event input / timer 0L capture input
P73: INT3 input (with noise filter) / timer 0 event input / timer 0H capture input
P70(AN8) to P73(AN11): AD converter input No
Interrupt acknowledge types
Rising &
Rising Falling H level L level
Falling
INT0 enable enable disable enable enable
INT1 enable enable disable enable enable
INT2 enable enable enable disable disable
INT3 enable enable enable disable disable

RES I/O External reset input / internal reset output No

CF1/XT1 I • Ceramic resonator or 32.768kHz crystal oscillator input pin
• Pin function No
General-purpose input port
CF2/XT2 I/O • Ceramic resonator or 32.768kHz crystal oscillator output pin
• Pin function No
General-purpose I/O port

Port Output Types

The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option selected in
Port Name Option type Output type Pull-up resistor
units of
P00 to P07 1 bit 1 CMOS Programmable (Note 1)
2 Nch-open drain No
P10 to P17 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
P20 to P21 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
P30 to P31 1 bit 1 CMOS Programmable
2 Nch-open drain Programmable
P70 - No Nch-open drain Programmable
P71 to P73 - No CMOS Programmable
CF2/XT2 - No Ceramic resonator/32.768kHz crystal resonator No
output Nch-open drain
(N-channel open drain when set to general-purpose
output port)
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or
P04 to 07).

No.A1955-11/28
 LC87FBL08A
User Option Table
Mask version Flash-ROM Option Selected in
Option Name Option to be Applied on Option Selection
*1 Version Units of
Port output type P00 to P07   1 bit CMOS
Nch-open drain
P10 to P17   1 bit CMOS
Nch-open drain
P20 to P21   1 bit CMOS
Nch-open drain
P30 to P31   1 bit CMOS
Nch-open drain
Program start - ×  - 00000h
address *2 01E00h
Low-voltage Detect function   - Enable:Use
detection reset Disable:Not Used
function
Detect level   - 3-level
Power-on reset Power-On reset level   - 4-level
function
*1: Mask option selection - No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.

Recommended Unused Pin Connections

Recommended Unused Pin Connections
Port Name
Board Software
P00 to P07 Open Output low
P10 to P17 Open Output low
P20 to P21 Open Output low
P30 to P31 Open Output low
P70 to P73 Open Output low
CF1/XT1 Pulled low with a 100kΩ resistor or less General-purpose input port
CF2/XT2 Pulled low with a 100kΩ resistor or less General-purpose input port

On-chip Debugger Pin Connection Requirements

For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 on-chip
debugger installation manual".

Power Pin Treatment Recommendations (VDD1, VSS1)

Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins:
• Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead
wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (L1=L1’ ,
L2=L2’).
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should approximately 0.1μF.

L2

L1

VSS1

C1 C2

VDD1
L1’

L2’

Note : Be sure to electrically short-circuit between the VSS1 and VSS2 pins.

No.A1955-12/28
 LC87FBL08A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Maximum supply VDD max VDD1
-0.3 +6.5
voltage
Input voltage VI CF1 -0.3 VDD+0.3 V
Input/output VIO Ports 0, 1, 2, 3, 7,
-0.3 VDD+0.3
voltage CF2, RES
Peak output IOPH(1) Ports 0, 1, 2, 3 CMOS output select
-10
High level output current

current Per 1 applicable pin

IOPH(2) P71 to P73 Per 1 applicable pin -5
Mean output IOMH(1) Ports 0, 1, 2, 3 CMOS output select
current P71 to P73 Per 1 applicable pin -7.5
(Note 1-1)
Total output ΣIOAH(1) Ports 0, 1, 2, 3, Total of all applicable pins
current P71 to P73 -25

Peak output IOPL(1) P02 to P07, Per 1 applicable pin

20
current Ports 1, 2, 3 mA
IOPL(2) P00, P01 Per 1 applicable pin 30
Low level output current

IOPL(3) Ports 7, CF2 Per 1 applicable pin 10

Mean output IOML(1) P02 to P07, Per 1 applicable pin
15
current Ports 1, 2, 3
(Note 1-1) IOML(2) P00, P01 Per 1 applicable pin 20
IOML(3) Ports 7, CF2 Per 1 applicable pin 7.5
Total output ΣIOAL(1) Ports 0, 1, Total of all applicable pins
70
current Ports 2, 3, CF2
ΣIOAL(2) Ports 7 Total of all applicable pins 15
Power Pd max(1) QFP36 (7×7) Ta=-40 to +85°C
120
dissipation Package only
Pd max(2) Ta=-40 to +85°C
mW
Package with thermal
275
resistance board
(Note 1-2)
Operating ambient Topr
-40 +85
temperature
°C
Storage ambient Tstg
-55 +125
temperature
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

No.A1955-13/28
 LC87FBL08A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Operating VDD VDD1 0.245μs ≤ tCYC ≤ 200μs
2.7 5.5
supply voltage
Memory VHD VDD1 RAM and register contents sustained
sustaining in HOLD mode. 1.6
supply voltage
High level VIH(1) Ports 1, 2, 3, 7 2.7 to 5.5 0.3VDD+0.7 VDD
input voltage VIH(2) Ports 0 2.7 to 5.5 0.3VDD+0.7 VDD
V
VIH(3) CF1, CF2, RES 2.7 to 5.5 0.75VDD VDD
Low level VIL(1) Ports 1, 2, 3, 7 4.0 to 5.5 VSS 0.1VDD+0.4
input voltage 2.7 to 4.0 VSS 0.2VDD
VIL(2) Ports 0 4.0 to 5.5 VSS 0.15VDD+0.4
2.7 to 4.0 VSS 0.2VDD
VIL(3) CF1, CF2, RES 2.7 to 5.5 VSS 0.25VDD
High level IOH(1) Ports 0, 1, 2, Per 1 applicable pin 4.5 to 5.5 -1.0
output current IOH(2) P71 to P73 2.7 to 4.5 -0.35
IOH(3) Ports 3, Per 1 applicable pin
4.5 to 5.5 -6.0
P05 (System clock
IOH(4) output function
2.7 to 4.5 -1.4
used)
IOH(1) Ports 0, 1, 2, 3, 7 Total of all applicable pins 4.5 to 5.5 -25
IOH(2) 2.7 to 4.5 -11.2
Low level IOL(1) Ports 0, 1, 2, 3 Per 1 applicable pin 4.5 to 5.5 10 mA
output current IOL(2) 2.7 to 4.5 1.4
IOL(3) Ports 7, CF2 Per 1 applicable pin 2.7 to 5.5 1.4
IOL(4) P00, P01 Per 1 applicable pin 4.5 to 5.5 25
IOL(5) 2.7 to 4.5 4
IOL(1) Ports 0, 1, 2, 3, Total of all applicable pins 4.5 to 5.5 70
IOL(2) CF2 2.7 to 4.5 34.6
IOL(3) Ports 7 Total of all applicable pins 2.7 to 5.5 5.6
Instruction tCYC
cycle time 2.7 to 5.5 0.245 200 μs
(Note 2-1)
External FEXCF CF1 • CF2 pin open
system clock • System clock frequency division
2.7 to 5.5 0.1 12
frequency ratio=1/1
• External system clock duty=50±5%
MHz
• CF2 pin open
• System clock frequency division
3.0 to 5.5 0.2 24.4
ratio=1/2
• External system clock duty=50±5%
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.

No.A1955-14/28
 LC87FBL08A
Continued from preceding page.
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Oscillation FmCF(1) CF1, CF2 12MHz ceramic oscillation.
2.7 to 5.5 12
frequency See Fig. 1.
range FmCF(2) CF1, CF2 10MHz ceramic oscillation.
2.7 to 5.5 10
(Note 2-2) See Fig. 1.
FmCF(3) CF1, CF2 4MHz ceramic oscillation.
CF oscillation normal amplifier size selected. 2.7 to 5.5 4
(CFLAMP=0) See Fig. 1.
4MHz ceramic oscillation.
CF oscillation low amplifier size MHz
2.7 to 5.5 4
selected. (CFLAMP=1)
See Fig. 1.
FmMRC(1) Frequency variable RC oscillation.
2.7 to 5.5 7.76 8.0 8.24
(Note 2-3)
FmMRC(2) Frequency variable RC oscillation.
• Ta=-10 to +85°C 2.7 to 5.5 7.80 8.0 8.20
(Note 2-3)
FmRC Internal medium-speed RC oscillation 2.7 to 5.5 0.5 1.0 2.0
FmSRC Internal low-speed RC oscillation 2.7 to 5.5 50 100 200
FsX’tal XT1, XT2 32.768kHz crystal oscillation kHz
2.7 to 5.5 32.768
See Fig. 1.
Oscillation tmsMRC When Frequency variable RC
stabilization oscillation state is switched from
2.7 to 5.5 100 μs
time stopped to enabled.
See Fig. 3.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
frequency variable RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.

No.A1955-15/28
 LC87FBL08A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
High level input IIH(1) Ports 0, 1, 2, 3, Output disabled
current Ports 7, RES Pull-up resistor off
VIN=VDD 2.7 to 5.5 1
(Including output Tr's off leakage
current)
IIH(2) CF1, CF2 Input port selected
2.7 to 5.5 1
VIN=VDD
IIH(3) CF1 Reset state
2.7 to 5.5 15 μA
VIN=VDD
Low level input IIL(1) Ports 0, 1, 2, 3, Output disabled
current Ports 7, RES Pull-up resistor off
VIN=VSS 2.7 to 5.5 -1
(Including output Tr's off leakage
current)
IIL(2) CF1, CF2 Input port selected
2.7 to 5.5 -1
VIN=VSS
High level output VOH(1) Ports 0, 1, 2, IOH=-1mA 4.5 to 5.5 VDD-1
voltage VOH(2) P71 to P73 IOH=-0.35mA 2.7 to 5.5 VDD-0.4
VOH(3) Ports 3, IOH=-6mA
4.5 to 5.5 VDD-1
P05 (System
VOH(4) clock output IOH=-1.4mA
2.7 to 5.5 VDD-0.4
function used) V
Low level output VOL(1) Ports 0, 1, 2, 3 IOL=10mA 4.5 to 5.5 1.5
voltage VOL(2) IOL=1.4mA 2.7 to 5.5 0.4
VOL(3) Ports7, CF2 IOL=1.4mA 2.7 to 5.5 0.4
VOL(4) P00, P01 IOL=25mA 4.5 to 5.5 1.5
VOL(5) IOL=4mA 2.7 to 5.5 0.4
Pull-up resistance Rpu(1) Ports 0, 1, 2, 3, VOH=0.9VDD 4.5 to 5.5 15 35 80
Ports 7 When Port 0 selected
Rpu(2) 2.7 to 4.5 18 50 150
low-impedance pull-up.
kΩ
Rpu(3) Port 0 VOH=0.9VDD
When Port 0 selected 2.7 to 5.5 100 200 300
high-impedance pull-up.
Hysteresis voltage VHYS Ports 1, 2, 3, 7,
2.7 to 5.5 0.1VDD V
RES
Pin capacitance CP All pins For pins other than that under test:
VIN=VSS
2.7 to 5.5 10 pF
f=1MHz
Ta=25°C

No.A1955-16/28
 LC87FBL08A
SIO1 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V (Note 4)
Pin/ Specification
Parameter Symbol Conditions
Remarks VDD[V] min typ max unit
Frequency tSCK(3) SCK1(P15) • See Fig. 5. 2
Input clock

Low level tSCKL(3)

1
pulse width 2.7 to 5.5
tCYC
High level tSCKH(3)
Serial clock

1
pulse width
Frequency tSCK(4) SCK1(P15) • CMOS output selected 2
Output clock

Low level tSCKL(4) • See Fig. 5.

1/2
pulse width 2.7 to 5.5
tSCK
High level tSCKH(4)
1/2
pulse width
Data setup time tsDI(2) SB1(P14), • Must be specified with (1/3)tCYC
Serial input

SI1(P14) respect to rising edge of +0.01

2.7 to 5.5
Data hold time thDI(2) SIOCLK.
0.01
• See Fig. 5.
Output delay time tdD0(4) SO1(P13), • Must be specified with respect to
SB1(P14) falling edge of SIOCLK. μs
Serial output

• Must be specified as the time to

(1/2)tCYC
the beginning of output state 2.7 to 5.5
+0.05
change in open drain output
mode.
• See Fig. 5.
Note 4: These specifications are theoretical values. Add margin depending on its use.

Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V

Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set.
pulse width tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are
INT2(P72), enabled. 2.7 to 5.5 1
INT4(P20 to P21),
INT5(P30 to P31)
tPIH(2) INT3(P73) when noise • Interrupt source flag can be set.
tPIL(2) filter time constant is • Event inputs for timer 0 are 2.7 to 5.5 2
tCYC
1/1 enabled.
tPIH(3) INT3(P73) when noise • Interrupt source flag can be set.
tPIL(3) filter time constant is • Event inputs for timer 0 are 2.7 to 5.5 64
1/32 nabled.
tPIH(4) INT3(P73) when noise • Interrupt source flag can be set.
tPIL(4) filter time constant is • Event inputs for timer 0 are 2.7 to 5.5 256
1/128 enabled.
tPIL(5) RES • Resetting is enabled. 2.7 to 5.5 200 μs

No.A1955-17/28
 LC87FBL08A
AD Converter Characteristics at VSS1 = VSS2 = 0V
<12bits AD Converter Mode/Ta = -40°C to +85°C >
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Resolution N AN0(P00) to 2.7 to 5.5 12 bit
Absolute ET AN6(P06), (Note 6-1) 3.0 to 5.5 ±16
accuracy AN8(P70) to LSB
2.7 to 5.5 ±20
AN11(P73)
Conversion time TCAD • See Conversion time calculation 4.0 to 5.5 32 115
formulas. (Note 6-2) 3.0 to 5.5 64 115 μs
2.7 to 5.5 134 215
Analog input VAIN
2.7 to 5.5 VSS VDD V
voltage range
Analog port IAINH VAIN=VDD 2.7 to 5.5 1
input current μA
IAINL VAIN=VSS 2.7 to 5.5 -1

<8bits AD Converter Mode/Ta = -40°C to +85°C >

Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Resolution N AN0(P00) to 2.7 to 5.5 8 bit
Absolute ET AN6(P06), (Note 6-1)
AN8(P70) to 2.7 to 5.5 ±1.5 LSB
accuracy
Conversion time TCAD AN11(P73) • See Conversion time calculation 4.0 to 5.5 20 90
formulas. (Note 6-2) 3.0 to 5.5 40 90 μs
2.7 to 5.5 80 135
Analog input VAIN
2.7 to 5.5 VSS VDD V
voltage range
Analog port IAINH VAIN=VDD 2.7 to 5.5 1
μA
input current IAINL VAIN=VSS 2.7 to 5.5 -1
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC

External Operating supply AD division AD conversion time

System division ratio Cycle time
oscillation voltage range ratio (TCAD)
(SYSDIV) (tCYC)
(FmCF) (VDD) (ADDIV) 12bit AD 8bit AD
4.0V to 5.5V 1/1 250ns 1/8 34.8μs 21.5μs

CF-12MHz 3.0V to 5.5V 1/1 250ns 1/16 69.5μs 42.8μs

2.7V to 5.5V 1/1 250ns 1/32 138.8μs 85.5μs
4.0V to 5.5V 1/1 375ns 1/8 52.25μs 32.25μs

CF-8MHz 3.0V to 5.5V 1/1 375ns 1/16 104.25μs 64.25μs

2.7V to 5.5V 1/1 375ns 1/32 208.25μs 128.25μs
3.0V to 5.5V 1/1 750ns 1/8 104.5μs 64.5μs
CF-4MHz
2.7V to 5.5V 1/1 750ns 1/16 208.5μs 128.5μs

Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.

No.A1955-18/28
 LC87FBL08A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions Option selected
min typ max unit
voltage
POR release PORRL • Select from option. 2.57V 2.45 2.57 2.69
voltage (Note 7-1) 2.87V 2.75 2.87 2.99
3.86V 3.73 3.86 3.99
4.35V 4.21 4.35 4.49 V

Detection POUKS • See Fig. 7.

voltage (Note 7-2) 0.7 0.95
unknown state
Power supply PORIS • Power supply rise
100 ms
rise time time from 0V to 1.6V.
Note7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled.
Note7-2: POR is in an unknown state before transistors start operation.

Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions Option selected
min typ max unit
voltage
LVD reset voltage LVDET • Select from option. 2.81V 2.71 2.81 2.91
(Note 8-2) (Note 8-1) 3.79V 3.67 3.79 3.91 V
(Note 8-3)
4.28V 4.15 4.28 4.41
• See Fig. 8.
LVD hysteresys LVHYS 2.81V 60
width 3.79V 65 mV
4.28V 65
Detection voltage LVUKS • See Fig. 8.
unknown state (Note 8-4) 0.7 0.95 V

Low voltage TLVDW • LVDET-0.5V

detection • See Fig. 9.
0.2 ms
minimum width
(Reply sensitivity)
Note8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled.
Note8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4: LVD is in an unknown state before transistors start operation.

No.A1955-19/28
 LC87FBL08A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = 0V
Pin/ Specification
Parameter Symbol Conditions
Remarks VDD[V] min typ max unit
Normal mode IDDOP(1) VDD1 • FmCF=12MHz ceramic oscillation mode
consumption • System clock set to 12MHz side 2.7 to 5.5 4.8 8.7
current • Internal low speed and medium speed RC
(Note 9-1) oscillation stopped.
(Note 9-2) • Frequency variable RC oscillation stopped. 2.7 to 3.6 3.0 5.0
• 1/1 frequency division ratio
IDDOP(2) • CF1=24MHz external clock
• System clock set to CF1 side 3.0 to 5.5 5.0 9.6
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 3.0 to 3.6 3.2 6.0
• 1/2 frequency division ratio
IDDOP(3) • FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side 2.7 to 5.5 4.1 7.8
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 2.6 4.9
• 1/1 frequency division ratio
IDDOP(4) • FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side 2.7 to 5.5 2.2 5.1
• Internal low speed and medium speed RC
oscillation stopped.
mA
• Frequency variable RC oscillation stopped. 2.7 to 3.6 1.5 2.7
• 1/1 frequency division ratio
IDDOP(5) • CF oscillation low amplifier size selected.
(CFLAMP=1)
2.7 to 5.5 0.95 2.4
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
2.7 to 3.6 0.50 1.1
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(6) • FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed RC oscillation stopped. 2.7 to 5.5 0.42 1.4
• System clock set to internal medium speed
RC oscillation.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 0.25 0.76
• 1/2 frequency division ratio
IDDOP(7) • FsX’tal=32.768kHz crystal oscillation mode
• Internal low speed and medium speed RC 2.7 to 5.5 3.2 5.4
oscillation stopped.
• System clock set to 8MHz with
frequency variable RC oscillation 2.7 to 3.6 2.3 4.2
• 1/1 frequency division ratio
IDDOP(8) • External FsX’tal and FmCF oscillation stopped.
• System clock set to internal low speed RC 2.7 to 5.5 55 169
oscillation.
• Internal medium speed RC oscillation sopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 39 109
• 1/1 frequency division ratio
IDDOP(9) • External FsX’tal and FmCF oscillation stopped. μA
• System clock set to internal low speed RC
5.0 55 136
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 3.3 39 103
• Ta=-10 to +50°C
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.

No.A1955-20/28
 LC87FBL08A
Continued from preceding page.
Pin/ Specification
Parameter Symbol Conditions
Remarks VDD[V] min typ max unit
Normal mode IDDOP(10) VDD1 • FsX’tal=32.768kHz crystal oscillation mode
consumption • System clock set to 32.768kHz side 2.7 to 5.5 28 89
current • Internal low speed and medium speed RC
(Note 9-1) oscillation stopped.
(Note 9-2) • Frequency variable RC oscillation stopped. 2.7 to 3.6 11 38
• 1/2 frequency division ratio
IDDOP(11) • FsX’tal=32.768kHz crystal oscillation mode μA
• System clock set to 32.768kHz side 5.0 28 78
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 3.3 11 29
• Ta=-10 to +50°C
HALT mode IDDHALT(1) • HALT mode
consumption • FmCF=12MHz ceramic oscillation mode 2.7 to 5.5 2.4 4.5
current • System clock set to 12MHz side
(Note 9-1) • Internal low speed and medium speed RC
(Note 9-2) oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 1.3 2.2
• 1/1 frequency division ratio
IDDHALT(2) • HALT mode
• CF1=24MHz external clock 3.0 to 5.5 2.7 5.3
• System clock set to CF1 side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 3.0 to 3.6 1.6 2.9
• 1/2 frequency division ratio
IDDHALT(3) • HALT mode
• FmCF=10MHz ceramic oscillation mode 2.7 to 5.5 2.0 4.1
• System clock set to 10MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 1.1 2.1
• 1/1 frequency division ratio
IDDHALT(4) • HALT mode
mA
• FmCF=4MHz ceramic oscillation mode
2.7 to 5.5 1.2 3.3
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 0.50 1.2
• 1/1 frequency division ratio
IDDHALT(5) • HALT mode
• CF oscillation low amplifier size selected.
(CFLAMP=1) 2.7 to 5.5 0.70 1.8
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal low speed and medium speed RC
oscillation stopped.
2.7 to 3.6 0.30 0.68
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDHALT(6) • HALT mode
• FsX’tal=32.768kHz crystal oscillation mode 2.7 to 5.5 0.30 0.90
• Internal low speed RC oscillation stopped.
• System clock set to internal medium speed
RC oscillation
• Frequency variable RC oscillation stopped. 2.7 to 3.6 0.20 0.44
• 1/2 frequency division ratio
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.

No.A1955-21/28
 LC87FBL08A
Continued from preceding page.
Pin/ Specification
Parameter Symbol Conditions
remarks VDD[V] min typ max unit
HALT mode IDDHALT(7) VDD1 • HALT mode
consumption • FsX’tal=32.768kHz crystal oscillation mode
2.7 to 5.5 1.3 2.3
current • Internal low speed and medium speed RC
(Note 9-1) oscillation stopped. mA
(Note 9-2) • System clock set to 8MHz with
frequency variable RC oscillation 2.7 to 3.6 0.90 1.5
• 1/1 frequency division ratio
IDDHALT(8) • HALT mode
• External FsX’tal and FmCF oscillation stopped. 2.7 to 5.5 18 68
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 11 35
• 1/1 frequency division ratio
IDDHALT(9) • HALT mode
• External FsX’tal and FmCF oscillation stopped.
5.0 18 46
• System clock set to internal low speed RC
oscillation.
• Internal medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
3.3 11 27
• 1/1 frequency division ratio
• Ta=-10 to +50°C
IDDHALT(10) • HALT mode
• FsX’tal=32.768kHz crystal oscillation mode 2.7 to 5.5 20 85
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped. 2.7 to 3.6 5.6 30
• 1/2 frequency division ratio
IDDHALT(11) • HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
5.0 20 51 μA
• System clock set to 32.768kHz side
• Internal low speed and medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
3.3 5.6 17
• 1/2 frequency division ratio
• Ta=-10 to +50°C
HOLD mode IDDHOLD(1) HOLD mode 2.7 to 5.5 0.012 23
consumption • CF1=VDD or open (External clock mode) 2.7 to 3.6 0.008 11
current
IDDHOLD(2) HOLD mode 5.0 0.012 1.2
(Note 9-1)
• CF1=VDD or open (External clock mode)
(Note 9-2) 3.3 0.008 0.59
• Ta=-10 to +50°C
IDDHOLD(3) HOLD mode 2.7 to 5.5 2.0 26
• CF1=VDD or open (External clock mode)
• LVD option selected 2.7 to 3.6 1.6 13
IDDHOLD(4) HOLD mode
5.0 2.0 3.8
• CF1=VDD or open (External clock mode)
• Ta=-10 to +50°C
3.3 1.6 2.8
• LVD option selected
Timer HOLD IDDHOLD(5) Timer HOLD mode 2.7 to 5.5 16 70
mode • FsX’tal=32.768 kHz crystal oscillation mode 2.7 to 3.6 4.2 25
consumption
IDDHOLD(6) Timer HOLD mode 5.0 16 42
current
• FsX’tal=32.768kHz crystal oscillation mode
(Note 9-1)
• Ta=-10 to +50°C 3.3 4.2 11
(Note 9-2)
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note9-2: The consumption current values do not include operational current of LVD function if not specified.

No.A1955-22/28
 LC87FBL08A
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = 0V
Specification
Parameter Symbol Pin/Remarks Conditions
VDD[V] min typ max unit
Onboard IDDFW(1) VDD1 • Only current of the Flash block.
programming 2.7 to 5.5 5 10 mA
current
Programming tFW(1) • Erasing time 20 30 ms
time 2.7 to 5.5
tFW(2) • Programming time 40 60 μs

Characteristics of a Sample Main System Clock Oscillation Circuit

Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.

Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
MURATA
Operating Oscillation
Circuit Constant
Nominal Voltage Stabilization Time
Type Oscillator Name Remarks
Frequency C1 C2 Rf Rd Range typ max
[pF] [pF] [Ω] [Ω] [V] [ms] [ms]
12MHz SMD CSTCE12M0G52-R0 (10) (10) Open 680 2.7 to 5.5 0.02 0.3
SMD CSTCE10M0G52-R0 (10) (10) Open 680 2.7 to 5.5 0.02 0.3
10MHz
LEAD CSTLS10M0G53-B0 (15) (15) Open 680 2.7 to 5.5 0.02 0.3
SMD CSTCE8M00G52-R0 (10) (10) Open 1.0k 2.7 to 5.5 0.02 0.3
8MHz Internal
LEAD CSTLS8M00G53-B0 (15) (15) Open 1.0k 2.7 to 5.5 0.02 0.3
C1, C2
SMD CSTCR6M00G53-R0 (15) (15) Open 1.5k 2.7 to 5.5 0.02 0.3
6MHz
LEAD CSTLS6M00G53-B0 (15) (15) Open 1.5k 2.7 to 5.5 0.02 0.3
SMD CSTCR4M00G53-R0 (15) (15) Open 1.5k 2.7 to 5.5 0.03 0.45
4MHz
LEAD CSTLS4M00G53-B0 (15) (15) Open 1.5k 2.7 to 5.5 0.02 0.3

• CF oscillation low amplifier size selected (CFLAMP=1)

MURATA
Operating Oscillation
Circuit Constant
Nominal Voltage Stabilization Time
Type Oscillator Name Remarks
Frequency C1 C2 Rf Rd Range typ max
[pF] [pF] [Ω] [Ω] [V] [ms] [ms]
12MHz SMD CSTCE12M0G52-R0 (10) (10) Open 470 3.9 to 5.5 0.04 0.6
SMD CSTCE10M0G52-R0 (10) (10) Open 470 2.9 to 5.5 0.03 0.45
10MHz CSTLS10M0G53-B0 (15) (15) Open 470 3.6 to 5.5 0.03 0.45
LEAD
CSTLS10M0G53095-B0 (15) (15) Open 470 2.7 to 5.5 0.02 0.3
SMD CSTCE8M00G52-R0 (10) (10) Open 680 2.7 to 5.5 0.03 0.45
8MHz CSTLS8M00G53-B0 (15) (15) Open 680 3.0 to 5.5 0.03 0.45 Internal
LEAD
CSTLS8M00G53093-B0 (15) (15) Open 680 2.7 to 5.5 0.02 0.3 C1, C2

SMD CSTCR6M00G53-R0 (15) (15) Open 1.0k 2.7 to 5.5 0.03 0.45
6MHz CSTLS6M00G53-B0 (15) (15) Open 1.0k 2.8 to 5.5 0.03 0.45
LEAD
CSTLS6M00G53093-B0 (15) (15) Open 1.0k 2.7 to 5.5 0.02 0.3
SMD CSTCR4M00G53-R0 (15) (15) Open 1.0k 2.7 to 5.5 0.04 0.6
4MHz
LEAD CSTLS4M00G53-B0 (15) (15) Open 1.0k 2.7 to 5.5 0.02 0.3
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in
follwing cases (see Figure 3).
• The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock
oscillation circuit is executed.
• The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and oscillation is
started.
• The time interval that is required for the oscillation to get stabilized after the X’tal Hold mode, under the state which
the main clock oscillation is enabled, is reset and oscillation is started.

No.A1955-23/28
 LC87FBL08A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.

Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
EPSON TOYOCOM
Operating Oscillation
Circuit Constant
Nominal Oscillator Voltage Stabilization Time
Type Remarks
Frequency Name C1 C2 Rf Rd Range typ max
[pF] [pF] [Ω] [Ω] [V] [s] [s]
Applicable CL value =
32.768kHz SMD MC-306 9 9 Open 330k 2.7 to 5.5 1.4 4.0
7.0pF

SEIKO INSTRUMENTS
Operating Oscillation
Circuit Constant
Nominal Oscillator Voltage Stabilization Time
Type Remarks
Frequency Name C1 C2 Rf Rd Range typ max
[pF] [pF] [Ω] [Ω] [V] [s] [s]
Applicable CL value =
32.768kHz SMD SSP-T7-F 22 22 Open 0 2.7 to 5.5 0.75 2.0
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 3).
• The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock
oscillation circuit is executed.
• The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which
the subclock oscillation is enabled, is reset and oscillation is started.

(Notes on the implementation of the oscillator circuit)

• Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related
components as close to the CPU chip and to each other as possible with the shortest possible pattern length.
• Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator
circuit as possible and make sure that they do not cross one another.
• Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage
level that is specified as the absolute maximum rating.
• The oscillator circuit constants shown above are sample characteristic values that are measured using the Our
designated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary
according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for
oscillation evaluation of the IC on a user's production board when using the IC for applications that require high
oscillation accuracy. For further information, contact your resonator vendor or Our company Semiconductor sales
representative serving your locality.
• It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their
operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same.

CF1/XT1 CF2/XT2

Rf
Rd

C1 C2 0.5VDD
CF/X’tal

Figure 1 CF and XT Oscillator Circuit Figure 2 AC Timing Measurement Point

No.A1955-24/28
 LC87FBL08A

VDD
Operating VDD
Power supply
lower limit
0V
Reset time
RES

Internal medium speed

RC oscillation

tmsCF/tmsXtal

CF1/XT1

CF2/XT2

tmsMRC

Frequency variable
RC oscillation

Instruction for enabling oscillation

executed
Operating
Unpredictable Reset Instruction execution
mode

Reset Time and Oscillation Stabilization Time

HOLD reset
HOLD reset signal absent HOLD reset signal valid HALT reset signal valid
signal

Internal medium speed

RC oscillation or
low speed RC oscillation

tmsCF/tmsXtal
CF1/XT1,
CF2/XT2
(Note)

tmsMRC

Frequency variable
RC oscillation
Instruction for enabling oscillation
executed
State HOLD HALT Instruction execution

HOLD Reset Signal and Oscillation Stabilization Time

Note: External oscillation circuit is selected.

Figure 3 Oscillation Stabilization Times

No.A1955-25/28
 LC87FBL08A

VDD

RRES Note:
External circuits for reset may vary
depending on the usage of POR and LVD.
RES Please refer to the user’s manual for more
information.
CRES

Figure 4 Reset Circuit

SIOCLK:

DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7

DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7

tSCK
tSCKL tSCKH
SIOCLK:

tsDI thDI
DATAIN:
tdDO

DATAOUT:

Figure 5 Serial I/O Output Waveforms

tPIL tPIH

Figure 6 Pulse Input Timing Signal Waveform

No.A1955-26/28
 LC87FBL08A

POR release voltage

(a) (b) (PORRL)

VDD

Reset period 100μs or longer Reset period

Unknown-state
(POUKS)

RES

Figure 7 Waveform observed when only POR is used (LVD not used)
(RESET pin: Pull-up resistor RRES only)

• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an
external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.

LVD hysteresis width

LVD release voltage
(LVHYS)
(LVDET+LVHYS)

VDD
LVD reset voltage
(LVDET)
Reset period Reset period Reset period
Unknown-state
(LVUKS)

RES

Figure 8 Waveform observed when both POR and LVD functions are used
(RESET pin: Pull-up resistor RRES only)

• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.

No.A1955-27/28
 LC87FBL08A

VDD

LVD release voltage

LVD reset voltage

LVDET-0.5V
TLVDW

VSS

Figure 9 Low voltage detection minimum width

(Example of momentary power loss/Voltage variation waveform)

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PS No.A1955-28/28