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28 views6 pages

Assignment

Uploaded by

prasad140298
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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1st <<<<<<-----gates----->>>>>>>>>

// Block: gates
module gates(y_not,y_and,y_or,y_xor,y_xnor,y_nand,y_nor,a,b);
// Input Ports:
input a;// a: 1-bit
input b;// b: 1-bit
// Output Ports:
output y_not; // y_not: 1-bit
output y_and; // y_and: 1-bit
output y_or; // y_or: 1-bit
output y_xor; // y_xor: 1-bit
output y_xnor; // y_xnor: 1-bit
output y_nand; // y_nand: 1-bit
output/ y_nor; // y_nor: 1-bit
// Description:
// Design all basic gates.
assign y_not = ~a,~b;
assign y_and = a & b;
assign y_or = a | b;
assign y_xor = a^b;
assign y_xnor = ~(a^b);
assign y_nand = ~(a & b);
assign y_nor = ~(a|b);
endmodule

2a <<<<<<-----binary2gray------->>>>>>>>

// Code your design here


//------------------------------------------------------------------------//
module bin2gray(bin_ip,gray_op);// Block: bin2gray
// Input Ports: 4-bit inp
[3:0]bin_ip;// bin_ip: 4-bit Vector
// Output Ports: 4-bit op
[3:0]gray_op;// gray_op: 4-bit Vector
// Description:
// Convert 4-bit Binary to Gray Code.
assign gray_op[3] = bin_ip[3];
assign gray_op[2] = bin_ip[3]^bin_ip[2];
assign gray_op[1] = bin_ip[2]^bin_ip[1];
assign gray_op[0] = bin_ip[1]^bin_ip[0];
endmodule

2b <<<<<<-----gray2binary-------->>>>>>>

module gray2bin(bin_op,gray_ip);// Block: bin2gray


// Input Ports: 4-bit inp
input[3:0]gray_ip;// bin_ip: 4-bit Vector
// Output Ports: 4-bit op
output[3:0]bin_op;// gray_op: 4-bit Vector
// Description:
// Convert 4-bit Binary to Gray Code.
assign bin_op[3] = gray_ip[3];
assign bin_op[2] = gray_ip[3]^gray_ip[2];
assign bin_op[1] = gray_ip[3]^gray_ip[2]^gray_ip[1];
assign bin_op[0] = gray_ip[3]^gray_ip[2]^gray_ip[1]^gray_ip[0];
endmodule
3 <<<<<<<-------count1--------->>>>>>>>

//------------------------------------------------------------------------//
module countones(i_data,o_cnt);// Block: countones
// Input Ports:
input [31:0]i_data;// i_data: 32-bit Vector
// Output Ports:
output reg[5:0]o_cnt;// o_cnt: 6-bit Vector
integer i;
// Description:
// Counts number of 1's in 32-bit input vector.
//------------------------------------------------------------------------//
// Code your design here

always@(i_data)
begin
o_cnt=0;
for(i=0;i<32;i=i+1)
if(i_data[i] == 1'b1)
o_cnt=o_cnt+1;
end
endmodule

4(A)<<<<<<<------mux4*1if------->>>>>>>>>>

//------------------------------------------------------------------------//
module mux4b_if(in0,in1,in2,in3,sel,out);// Block: mux4b_if
// Input Ports:
input [3:0]in0;// in0, in1, in2, in3: 4-bit Vector
input [3:0]in1;
input [3:0]in2;
input [3:0]in3;
input[1:0]sel;// sel: 2-bit Vector
// Output Ports:
output reg [3:0]out;// out: 4-bit Vector
// Description:
// Implement 4:1 Mux using if-statements.
always @(*) begin
if (sel==0)
out <= in0;
else if (sel==1)
out <= in1;
else if (sel==2)
out = in2;
else
out = in3;
end

endmodule

4(b)<<<<<<--------MUX4*1_CASE--------->>>>>>>>>>

//------------------------------------------------------------------------//
module mux4b_case(in0,in1,in2,in3,sel,out);// Block: mux4b_case
// Input Ports:
input [3:0]in0;// in0, in1, in2, in3: 4-bit Vector
input [3:0]in1;
input [3:0]in2;
input [3:0]in3;
input[1:0]sel;// sel: 2-bit Vector
// Output Ports:
output reg [3:0]out;// out: 4-bit Vector
// Description:
// Implement 4:1 Mux using if-statements.
always @ (*)
begin
case(sel)
2'b00: out<=in0;
2'b01: out<=in1;
2'b10: out<=in2;
2'b11: out<=in3;
endcase
end
endmodule

4(C)<<<<<<<--------mux4*1_terinary------->>>>>>>>>

//------------------------------------------------------------------------//
module mux4b_ternary(in0,in1,in2,in3,sel,out);// Block: mux4b_case
// Input Ports:
input [3:0]in0;// in0, in1, in2, in3: 4-bit Vector
input [3:0]in1;
input [3:0]in2;
input [3:0]in3;
input[1:0]sel;// sel: 2-bit Vector
// Output Ports:
output [3:0]out;// out: 4-bit Vector
assign out=(sel[1]?(sel[0]?in3:in2):(sel[0]?in1:in0));
endmodule// Code your design here

5<<<<<<<<<<<-------demux-------->>>>>>>>>>>>>>>

// Code your design here


module demux8_to_1(in,desel,out0,out1,out2,out3,out4,out5,out6,out7);// Block:
demux8_to_1
// Input Ports:
input [3:0]in;// in: 4-bit Vector
input [2:0]desel;// desel: 3-bit Vector
// Output Ports:
output reg [3:0]out0;// out0: 4-bit Vector
output reg [3:0]out1;// out1: 4-bit Vector
output reg [3:0]out2;// out2: 4-bit Vector
output reg [3:0]out3;// out3: 4-bit Vector
output reg [3:0]out4;// out4: 4-bit Vector
output reg [3:0]out5;// out5: 4-bit Vector
output reg [3:0]out6;// out6: 4-bit Vector
output reg [3:0]out7;// out7: 4-bit Vector
// Description:
// Deselect input to one of the output

//------------------------------------------------------------------------//
always@(*)
begin
case(desel)

3'd0:begin
out0=in;out1=0;out2=0;out3=0;out4=0;out5=0;out6=0;out7=0;
end
3'd1:begin
out0=0;out1=in;out2=0;out3=0;out4=0;out5=0;out6=0;out7=0;
end
3'd2:begin
out0=0;out1=0;out2=in;out3=0;out4=0;out5=0;out6=0;out7=0;
end
3'd3:begin
out0=0;out1=0;out2=0;out3=in;out4=0;out5=0;out6=0;out7=0;
end
3'd4:begin
out0=0;out1=0;out2=0;out3=0;out4=in;out5=0;out6=0;out7=0;
end
3'd5:begin
out0=0;out1=0;out2=0;out3=0;out4=0;out5=in;out6=0;out7=0;
end
3'd6:begin
out0=0;out1=0;out2=0;out3=0;out4=0;out5=0;out6=in;out7=0;
end
3'd7:begin
out0=0;out1=0;out2=0;out3=0;out4=0;out5=0;out6=0;out7=in;
end
endcase
end
endmodule

6<<<<<<<<<<-------dec3*8---------->>>>>>>>>>>>>

// Code your design here


//------------------------------------------------------------------------//
module decoder3_to_8(en,i0,i1,i2,d0,d1,d2,d3,d4,d5,d6,d7);// Block:
decoder3_to_8
// Input Ports:
input i0;// i0: 1-bit Vector
input i1;// i1: 1-bit Vector
input i2;// i2: 1-bit Vector
input en;
// Output Ports:
output reg d0;// D0: 1-bit Vector
output reg d1;// D1: 1-bit Vector
output reg d2;// D2: 1-bit Vector
output reg d3;// D3: 1-bit Vector
output reg d4;// D4: 1-bit Vector
output reg d5;// D5: 1-bit Vector
output reg d6;// D6: 1-bit Vector
output reg d7;// D7: 1-bit Vector
// Description:
// 3:8 Decoder implementation
/* assign d0 =(!i0)&(!i1)&(!i2);
assign d1 =(!i0)&(!i1)&(i2);
assign d2 =(!i0)&(i1)&(!i2);
assign d3 =(!i0)&(i1)&(i2);
assign d4 =(i0)&(!i1)&(!i2);
assign d5 =(i0)&(!i1)&(i2);
assign d6 =(i0)&(i1)&(!i2);
assign d7 =(i0)&(i1)&(i2);
endmodule */
always @(i0,i1,i2,en)
begin
if(en==1)
begin
d0 = (!i2)&&(!i1)&&(!i0);
d1 = (!i2)&&(!i1)&&(i0);
d2 = (!i2)&&(i1)&&(!i0);
d3 = (!i2)&&(i1)&&(i0);
d4 = (i2)&&(!i1)&&(!i0);
d5 = (i2)&&(!i1)&&(i0);
d6 = (i2)&&(i1)&&(!i0);
d7 = (i2)&&(i1)&&(i0);
end
else
$display("enable is zero");

end
endmodule

//------------------------------------------------------------------------//

7<<<<<<<<<<-----encoder-------->>>>>>>>>>>>

// Code your design here


//------------------------------------------------------------------------//
module binary_encoder8_to_3(en,i0,i1,i2,i3,i4,i5,i6,i7,e0,e1,e2);// Block:
binary_encoder8_to_3
// Input Ports:
input i0;// i0: 1-bit Vector
input i1;// i1: 1-bit Vector
input i2;// i2: 1-bit Vector
input i3;// i3: 1-bit Vector
input i4;// i4: 1-bit Vector
input i5;// i5: 1-bit Vector
input i6;// i6: 1-bit Vector
input i7;// i7: 1-bit Vector
input en;
// Output Ports:
output reg e0;// E0: 1-bit Vector
output reg e1;// E1: 1-bit Vector
output reg e2;// E2: 1-bit Vector
// Description:
// 8:3 Binary Encoder implementation
//------------------------------------------------------------------------//
always @(i0,i1,i2,i3,i4,i5,i6,i7,en)
begin
if(en==1)
begin
e0=(i7|i5|i3|i1);
e1=(i7|i6|i3|i2);
e2=(i7|i6|i5|i4);

end
else
begin
e0=0;
e1=0;
e2=0;
end
$display("enable zero");
end
endmodule

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