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Lecture #7

MIPS
Part I: Introduction
 Lecture #1: Introduction 1-2

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• All notes are by A/P Aaron Tan
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 Lecture #7: MIPS Part 1: Introduction 3

Lecture #7: MIPS Part 1: Introduction (1/2)

1. Instruction Set Architecture
2. Machine Code vs Assembly Language
3. Walkthrough
4. General Purpose Registers
5. MIPS Assembly Language
5.1 General Instruction Syntax
5.2 Arithmetic Operation: Addition
5.3 Arithmetic Operation: Subtraction
5.4 Complex Expression
5.5 Constant/Immediate Operands
5.6 Register Zero ($0 or $zero)
 Lecture #7: MIPS Part 1: Introduction 4

Lecture #7: MIPS Part 1: Introduction (1/2)

5. MIPS Assembly Language
5.7 Logical Operations: Overview
5.8 Logical Operations: Shifting
5.9 Logical Operations: Bitwise AND
5.10 Logical Operations: Bitwise OR
5.11 Logical Operations: Bitwise NOR
5.12 Logical Operations: Bitwise XOR
6. Large Constant: Case Study
7. MIPS Basic Instructions Checklist
 Lecture #7: MIPS Part 1: Introduction 5

Recap
§ You write programs in high level
programming languages, e.g.,
C/C++, Java:
A + B
§ Compiler translates this into
assembly language statement:

add A, B

§ Assembler translates this statement

into machine language instructions
that the processor can execute:
1000 1100 1010 0000
 Lecture #7: MIPS Part 1: Introduction 6

1. Instruction Set Architecture (1/2)

§ Instruction Set Architecture (ISA):
§ An abstraction on the interface between the hardware
and the low-level software.

Software
(to be translated to
the instruction set)

Instruction Set Architecture

Hardware
(implementing the
instruction set)
 Lecture #7: MIPS Part 1: Introduction 7

1. Instruction Set Architecture (2/2)

§ Instruction Set Architecture
§ Includes everything programmers need to know to make the
machine code work correctly
§ Allows computer designers to talk about functions independently
from the hardware that performs them

§ This abstraction allows many implementations of varying

cost and performance to run identical software.
§ Example: Intel x86/IA-32 ISA has been implemented by a range
of processors starting from 80386 (1985) to Pentium 4 (2005)
§ Other companies such as AMD and Transmeta have implemented
IA-32 ISA as well
§ A program compiled for IA-32 ISA can execute on any of these
implementations
 Lecture #7: MIPS Part 1: Introduction 8

2. Machine Code vs Assembly Language

§ Machine code
§ Instructions are represented in binary
§ 1000110010100000 is an instruction that tells one computer to
add two numbers
§ Hard and tedious for programmer

§ Assembly language
§ Symbolic version of machine code
§ Human readable
§ add A, B is equivalent to 1000110010100000
§ Assembler translates from assembly language to machine code
§ Assembly can provide ‘pseudo-instructions’ as syntactic sugar
§ When considering performance, only real instructions are counted.
 Lecture #7: MIPS Part 1: Introduction 9

3. Walkthrough: An Example Code (1/15)

§ Let us take a journey with the execution of a simple
code:
§ Discover the components in a typical computer
§ Learn the type of instructions required to control the processor
§ Simplified to highlight the important concepts J

// assume res is 0 initially

res ß res + i
for (i=1; i<10; i++) {
compile i ß i + 1
res = res + i; to if i < 10, repeat
}

C-like code “Assembly”

fragment Code
 Lecture #7: MIPS Part 1: Introduction 10

3. Walkthrough: The Components (2/15)

§ The two major components in a computer
§ Processor and Memory
§ Input/Output devices omitted in this example

Processor Memory

Bus
Perform Bridge between the Storage of code
computations two components and data
 Lecture #7: MIPS Part 1: Introduction 11

3. Walkthrough: The Code in Action (3/15)

§ The code and data reside in memory
§ Transferred into the processor during execution

Processor Memory

Inst res ß res + i ………..

Bus res ß res + i
i ßi+1
res+i if i < 10,
ALU
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 12

3. Walkthrough: Memory Access is Slow! (4/15)

§ To avoid frequent access of memory
§ Provide temporary storage for values in the processor
(known as registers)
Processor Memory

Inst ………..
Bus res ß res + i
r0 i ßi+1
r1 if i < 10,
ALU
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 13

3. Walkthrough: Memory Instruction (5/15)

§ Need instruction to move data into registers
§ Also to move data from registers to memory later
Memory
………..
Processor r0 ß load i
Inst r0 ß load i r1 ß load res
Bus res ß res + i
r0 1 i ßi+1
r1 if i < 10,
ALU
.. …
………
i 1
Moving data from memory into a register res 0
– load
………..
Moving data from a register into memory
– store
 Lecture #7: MIPS Part 1: Introduction 14

3. Walkthrough: Memory Instruction (6/15)

§ Need instruction to move data into registers
§ Also to move data from registers to memory later
Memory
………..
Processor r0 ß load i
Inst r1 ß load res r1 ß load res
Bus res ß res + i
r0 1 i ßi+1
r1 0 if i < 10,
ALU
.. …
………
i 1
Moving data from memory into a register res 0
– load
………..
Moving data from a register into memory
– store
 Lecture #7: MIPS Part 1: Introduction 15

3. Walkthrough: Reg-to-Reg Arithmetic (7/15)

§ Arithmetic operations can now work directly on
registers only (much faster!)
Memory
………..
Processor r0 ß load i
Inst r1 ß r1 + r0 r1 ß load res
Bus r1 ß r1 + r0
r0 1 r0 ß r0 + 1
r1 0
1 ALU if r0 < 10,
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 16

3. Walkthrough: Reg-to-Reg Arithmetic (8/15)

§ Sometimes, arithmetic operation uses a
constant value instead of register value
Memory
………..
Processor r0 ß load i
Inst r0 ß r0 + 1 r1 ß load res
Bus r1 ß r1 + r0
r0 2
1 r0 ß r0 + 1
r1 1 ALU if r0 < 10,
1
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 17

3. Walkthrough: Execution Sequence (9/15)

§ Instruction is executed sequentially by default
§ How do we “repeat” or “make a choice”?
Memory
………..
Processor r0 ß load i
Inst r1 ß load res
Bus r1 ß r1 + r0
r0 r0 ß r0 + 1
r1 ALU if r0 < 10,
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 18

3. Walkthrough: Control Flow (10/15)

§ We need instructions to change the control flow based on
condition:
§ Repetition (loop) and Selection (if-else) can both be supported
Memory
………..
Processor r0 ß load i
Inst if r0 < 10, repeat r1 ß load res
Bus r1 ß r1 + r0
r0 2 r0 ß r0 + 1
r1 1 ALU if r0 < 10,
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 19

3. Walkthrough: Looping! (11/15)

§ Since the condition succeeded, execution will
repeat from the indicated position
Memory
………..
Processor r0 ß load i
Inst r1 ß r1 + r0 r1 ß load res
Bus r1 ß r1 + r0
r0 2 r0 ß r0 + 1
r1 1
3 ALU if r0 < 10,
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 20

3. Walkthrough: Looping! (12/15)

§ Execution will continue sequentially
§ Until we see another control flow instruction
Memory
………..
Processor r0 ß load i
Inst r0 ß r0 + 1 r1 ß load res
Bus r1 ß r1 + r0
r0 2
3 r0 ß r0 + 1
r1 3 ALU if r0 < 10,
1
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 21

3. Walkthrough: Looping! (13/15)

§ The three instructions will be repeated until the
condition fails
Memory
………..
Processor r0 ß load i
Inst if r0 < 10, repeat r1 ß load res
Bus r1 ß r1 + r0
r0 10 r0 ß r0 + 1
r1 45 ALU if r0 < 10,
.. …
………
i 1
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 22

3. Walkthrough: Memory Instruction (14/15)

§ We can now move back the values from register to
their “home” in memory
§ Similarly for “r1” to “res” Memory
………..
Processor r0 ß load i
Inst i ß store r0 r1 ß load res
Bus r1 ß r1 + r0
r0 10 r0 ß r0 + 1
r1 45 ALU if r0 < 10,
.. … i ß store r0
………
i 1
10
res 0

………..
 Lecture #7: MIPS Part 1: Introduction 23

3. Walkthrough: Summary (15/15)

§ The stored-memory concept:
§ Both instruction and data are stored in memory
§ The load-store model:
§ Limit memory operations and relies on registers for
storage during execution
§ The major types of assembly instruction:
§ Memory: Move values between memory and registers
§ Calculation: Arithmetic and other operations
§ Control flow: Change the sequential execution
 Lecture #7: MIPS Part 1: Introduction 24

4. General Purpose Registers (1/2)

§ Fast memories in the processor:
§ Data are transferred from memory to registers for faster
processing
§ Limited in number:
§ A typical architecture has 16 to 32 registers
§ Compiler associates variables in program with registers
§ Registers have no data type
§ Unlike program variables!
§ Machine/Assembly instruction assumes the data stored in the
register is of the correct type
 Lecture #7: MIPS Part 1: Introduction 25

4. General Purpose Registers (2/2)

• There are 32 registers in MIPS assembly language:
• Can be referred by a number ($0, $1, …, $31) OR
• Referred by a name (eg: $a0, $t1)

Register Register
Name Usage Name Usage
number number
$zero 0 Constant value 0 More
$t8-$t9 24-25
Values for results temporaries
$v0-$v1 2-3 and expression $gp 28 Global pointer
evaluation $sp 29 Stack pointer
$a0-$a3 4-7 Arguments $fp 30 Frame pointer
$t0-$t7 8-15 Temporaries $ra 31 Return address
$s0-$s7 16-23 Program variables

$at (register 1) is reserved for the assembler.

$k0-$k1 (registers 26-27) are reserved for the operation system.
 Lecture #7: MIPS Part 1: Introduction 26

5. MIPS Assembly Language

§ Each instruction executes a simple command
§ Usually has a counterpart in high level programming
languages like C/C++, Java etc

§ Each line of assembly code contains at most 1

instruction
§ # (hex-sign) is used for comments
§ Anything from # to end of line is a comment and will be
ignored by the assembler

add $t0, $s1, $s2 # $t0 ß $s1 + $s2

sub $s0, $t0, $s3 # $s0 ß $t0 - $s3
 Lecture #7: MIPS Part 1: Introduction 27

5.1 General Instruction Syntax

add $s0, $s1, $s2

Source 2
Operation (op) Source 1
Destination
(gets the result)
$s0 = $s1 + $s2
Naturally, most of the MIPS arithmetic/logic operations
have three operands: 2 sources and 1 destination
 Lecture #7: MIPS Part 1: Introduction 28

5.2 Arithmetic Operation: Addition

C Statement MIPS Assembly Code
a = b + c; add $s0, $s1, $s2

§ We assume the values of "a", "b" and "c" are loaded

into registers "$s0", "$s1" and "$s2"
§ Known as variable mapping
§ Actual code to perform the loading will be shown later in memory
instruction
§ Important concept:
§ MIPS arithmetic operations are mainly register-to-register
 Lecture #7: MIPS Part 1: Introduction 29

5.3 Arithmetic Operation: Subtraction

C Statement MIPS Assembly Code
a = b - c; sub $s0, $s1, $s2
$s0 à variable a
$s1 à variable b
$s2 à variable c

§ Positions of $s1 and $s2 (i.e., source1 and

source2) are important for subtraction
 Lecture #7: MIPS Part 1: Introduction 30

5.4 Complex Expression (1/3)

C Statement MIPS Assembly Code
a = b + c - d; ??? ??? ???
$s0 à variable a
$s1 à variable b
$s2 à variable c
$s3 à variable d

§ A single MIPS instruction can handle at most two source

operands
è Need to break a complex statement into multiple
MIPS instructions
MIPS Assembly Code
Use temporary
add $t0, $s1, $s2 # tmp = b + c registers $t0 to $t7 for
sub $s0, $t0, $s3 # a = tmp - d intermediate results
 Lecture #7: MIPS Part 1: Introduction 31

5.4 Complex Expression: Example (2/3)

C Statement Variable Mappings
$s0 à variable f
f = (g + h) – (i + j); $s1 à variable g
$s2 à variable h
$s3 à variable i
$s4 à variable j

§ Break it up into multiple instructions

§ Use two temporary registers $t0, $t1

add $t0, $s1, $s2 # tmp0 = g + h

add $t1, $s3, $s4 # tmp1 = i + j
sub $s0, $t0, $t1 # f = tmp0 – tmp1
 Lecture #7: MIPS Part 1: Introduction 32

5.4 Complex Expression: Exercise (3/3)

C Statement Variable Mappings
$s0 à variable a
z = a + b + c + d; $s1 à variable b
$s2 à variable c
$s3 à variable d
$s4 à variable z

C Statement Variable Mappings

$s0 à variable a
z = (a – b) + c; $s1 à variable b
$s2 à variable c
$s3 à variable z

±
 Lecture #7: MIPS Part 1: Introduction 33

5.5 Constant/Immediate Operands

C Statement MIPS Assembly Code
a = a + 4; add $s0, $s0, 4

§ Immediate values are numerical constants

§ Frequently used in operations
§ MIPS supplies a set of operations specially for them

§ “Add immediate” (addi)

§ Syntax is similar to add instruction; but source2 is a constant
instead of register
§ The constant ranges from [-215 to 215-1]
Can you guess what number system is used?

±
 Lecture #7: MIPS Part 1: Introduction 34

5.6 Register Zero ($0 or $zero)

§ The number zero (0), appears very often in code
§ Provide register zero ($0 or $zero) which always have the value 0
C Statement MIPS Assembly Code
add $s0, $s1, $zero
f = g;
$s0 à variable f
$s1 à variable g

§ The above assignment is so common that MIPS has an

equivalent pseudo instruction (move):
MIPS Assembly Code Pseudo-Instruction
"Fake" instruction that gets translated to
move $s0, $s1 corresponding MIPS instruction(s).
Provided for convenience in coding only.
 Lecture #7: MIPS Part 1: Introduction 35

5.7 Logical Operations: Overview (1/2)

§ Arithmetic instructions view the content of a register as a
single quantity (signed or unsigned integer)
§ New perspective:
§ View register as 32 raw bits rather than as a single 32-bit number
è Possible to operate on individual bits or bytes within a word

Logical C Java MIPS

operation operator operator instruction
Shift Left << << sll
Shift right >> >>, >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor
 Lecture #7: MIPS Part 1: Introduction 36

5.7 Logical Operations: Overview (2/2)

§ Truth tables of logical operations
§ 0 represents false; 1 represents true

AND a b a AND b OR a b a OR b
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NOR a b a NOR b XOR a b a XOR b

0 0 1 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
 Lecture #7: MIPS Part 1: Introduction 37

5.8 Logical Operations: Shifting (1/2)

Opcode: sll (shift left logical)
Move all the bits in a word to the left by a number of
positions; fill the emptied positions with zeroes.

§ E.g. Shift bits in $s0 to the left by 4 positions

$s0 1011 1000 0000 0000 0000 0000 0000 1001

sll $t2, $s0, 4 # $t2 = $s0<<4

$t2

±
 Lecture #7: MIPS Part 1: Introduction 38

5.8 Logical Operations: Shifting (2/2)

Opcode: srl (shift right logical)
Shifts right and fills emptied positions with zeroes.

§ What is the equivalent math operations for

shifting left/right n bits? Answer: ________________
§ Shifting is faster than multiplication/division
è Good compiler translates such multiplication/division
into shift instructions
C Statement MIPS Assembly Code
a = a * 8; sll $s0, $s0, 3
±
 Lecture #7: MIPS Part 1: Introduction 39

5.9 Logical Operations: Bitwise AND

Opcode: and ( bitwise AND )
Bitwise operation that leaves a 1 only if both the bits of
the operands are 1
§ E.g.: and $t0, $t1, $t2
$t1 0110 0011 0010 1111 0000 1101 0101 1001
mask $t2 0000 0000 0000 0000 0011 1100 0000 0000
$t0 0000 0000 0000 0000 0000 1100 0000 0000

§ and can be used for masking operation:

§ Place 0s into the positions to be ignored è bits will turn into 0s
§ Place 1s for interested positions è bits will remain the same as
the original.
 Lecture #7: MIPS Part 1: Introduction 40

5.9 Exercise: Bitwise AND

§ We are interested in the last 12 bits of the word
in register $t1. Result to be stored in $t0.
§ Q: What’s the mask to use?

$t1 0000 1001 1100 0011 0101 1101 1001 1100

mask

$t0

Notes:
The and instruction has an immediate version, andi

±
 Lecture #7: MIPS Part 1: Introduction 41

5.10 Logical Operations: Bitwise OR

Opcode: or ( bitwise OR )
Bitwise operation that that places a 1 in the result if
either operand bit is 1
Example: or $t0, $t1, $t2

§ The or instruction has an immediate version ori

§ Can be used to force certain bits to 1s
§ E.g.: ori $t0, $t1, 0xFFF

$t1 0000 1001 1100 0011 0101 1101 1001 1100

0xFFF 0000 0000 0000 0000 0000 1111 1111 1111
$t0

±
 Lecture #7: MIPS Part 1: Introduction 42

5.11 Logical Operations: Bitwise NOR

§ Strange fact 1:
§ There is no NOT instruction in MIPS to toggle the bits (1
à 0, 0 à 1)
§ However, a NOR instruction is provided:
Opcode: nor ( bitwise NOR )
Example: nor $t0, $t1, $t2

n Question: How do we get a NOT operation?

n Question: Why do you think is the reason for not

providing a NOT instruction?

±
 Lecture #7: MIPS Part 1: Introduction 43

5.12 Logical Operations: Bitwise XOR

Opcode: xor ( bitwise XOR )
Example: xor $t0, $t1, $t2

n Question: Can we also get NOT operation from

XOR?

n Strange Fact 2:
n There is no NORI, but there is XORI in MIPS

n Why?

±
 Lecture #7: MIPS Part 1: Introduction 44

6. Large Constant: Case Study

§ Question: How to load a 32-bit constant into a
register? e.g 10101010 10101010 11110000 11110000
1. Use “load upper immediate” (lui) to set the upper 16-bit:
lui $t0, 0xAAAA #1010101010101010
Lower-order bits
1010101010101010 0000000000000000
filled with zeros.
2. Use “or immediate” (ori) to set the lower-order bits:
ori $t0, $t0, 0xF0F0 #1111000011110000

1010101010101010 0000000000000000
ori 0000000000000000 1111000011110000

1010101010101010 1111000011110000
 Lecture #7: MIPS Part 1: Introduction 45

7. MIPS Basic Instructions Checklist

Operation Opcode in MIPS Immediate Version
(if applicable)
addi $s0, $s1, C162s
Addition add $s0, $s1, $s2
C162s is [-215 to 215-1]

Subtraction sub $s0, $s1, $s2

sll $s0, $s1, C5

Shift left logical
C5 is [0 to 25-1]
Shift right logical srl $s0, $s1, C5
andi $s0, $s1, C16
AND bitwise and $s0, $s1, $s2
C16 is a 16-bit pattern
OR bitwise or $s0, $s1, $s2 ori $s0, $s1, C16
NOR bitwise nor $s0, $s1, $s2
XOR bitwise xor $s0, $s1, $s2 xori $s0, $s1, C16
Lecture #7: MIPS Part 1: Introduction 46

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